[{"id":3585229,"web_url":"http://patchwork.ozlabs.org/comment/3585229/","msgid":"<20250922160040.GA92842-robh@kernel.org>","list_archive_url":null,"date":"2025-09-22T16:00:40","subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Mon, Sep 15, 2025 at 11:01:49AM +0300, Svyatoslav Ryhel wrote:\n> Add Tegra114 support into existing Tegra124 MC schema with the most\n> notable difference in the amount of EMEM timings.\n> \n> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>\n> ---\n>  .../nvidia,tegra124-mc.yaml                   | 97 ++++++++++++++-----\n>  1 file changed, 74 insertions(+), 23 deletions(-)\n> \n> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> index 7b18b4d11e0a..9cc9360d3bd0 100644\n> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> @@ -19,7 +19,9 @@ description: |\n>  \n>  properties:\n>    compatible:\n> -    const: nvidia,tegra124-mc\n> +    enum:\n> +      - nvidia,tegra114-mc\n> +      - nvidia,tegra124-mc\n>  \n>    reg:\n>      maxItems: 1\n> @@ -64,29 +66,10 @@ patternProperties:\n>  \n>            nvidia,emem-configuration:\n>              $ref: /schemas/types.yaml#/definitions/uint32-array\n> -            description: |\n> +            description:\n>                Values to be written to the EMEM register block. See section\n> -              \"15.6.1 MC Registers\" in the TRM.\n> -            items:\n> -              - description: MC_EMEM_ARB_CFG\n> -              - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> -              - description: MC_EMEM_ARB_TIMING_RCD\n> -              - description: MC_EMEM_ARB_TIMING_RP\n> -              - description: MC_EMEM_ARB_TIMING_RC\n> -              - description: MC_EMEM_ARB_TIMING_RAS\n> -              - description: MC_EMEM_ARB_TIMING_FAW\n> -              - description: MC_EMEM_ARB_TIMING_RRD\n> -              - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> -              - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> -              - description: MC_EMEM_ARB_TIMING_R2R\n> -              - description: MC_EMEM_ARB_TIMING_W2W\n> -              - description: MC_EMEM_ARB_TIMING_R2W\n> -              - description: MC_EMEM_ARB_TIMING_W2R\n> -              - description: MC_EMEM_ARB_DA_TURNS\n> -              - description: MC_EMEM_ARB_DA_COVERS\n> -              - description: MC_EMEM_ARB_MISC0\n> -              - description: MC_EMEM_ARB_MISC1\n> -              - description: MC_EMEM_ARB_RING1_THROTTLE\n> +              \"20.11.1 MC Registers\" in the Tegea114 TRM or\n> +              \"15.6.1 MC Registers\" in the Tegra124 TRM.\n>  \n>          required:\n>            - clock-frequency\n> @@ -109,6 +92,74 @@ required:\n>    - \"#iommu-cells\"\n>    - \"#interconnect-cells\"\n>  \n> +allOf:\n> +  - if:\n> +      properties:\n> +        compatible:\n> +          contains:\n> +            enum:\n> +              - nvidia,tegra114-mc\n> +    then:\n> +      patternProperties:\n> +        \"^emc-timings-[0-9]+$\":\n> +          patternProperties:\n> +            \"^timing-[0-9]+$\":\n> +              properties:\n> +                nvidia,emem-configuration:\n> +                  items:\n> +                    - description: MC_EMEM_ARB_CFG\n> +                    - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> +                    - description: MC_EMEM_ARB_TIMING_RCD\n> +                    - description: MC_EMEM_ARB_TIMING_RP\n> +                    - description: MC_EMEM_ARB_TIMING_RC\n> +                    - description: MC_EMEM_ARB_TIMING_RAS\n> +                    - description: MC_EMEM_ARB_TIMING_FAW\n> +                    - description: MC_EMEM_ARB_TIMING_RRD\n> +                    - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> +                    - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> +                    - description: MC_EMEM_ARB_TIMING_R2R\n> +                    - description: MC_EMEM_ARB_TIMING_W2W\n> +                    - description: MC_EMEM_ARB_TIMING_R2W\n> +                    - description: MC_EMEM_ARB_TIMING_W2R\n> +                    - description: MC_EMEM_ARB_DA_TURNS\n> +                    - description: MC_EMEM_ARB_DA_COVERS\n> +                    - description: MC_EMEM_ARB_MISC0\n> +                    - description: MC_EMEM_ARB_RING1_THROTTLE\n\nLike I said before, I don't think it is worth enumerating the list of \nregisters for every variant. If you want to define the length \n(minItems/maxItems), then that is fine.\n\nRob","headers":{"Return-Path":"\n <devicetree+bounces-220127-incoming-dt=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming-dt@patchwork.ozlabs.org","devicetree@vger.kernel.org"],"Delivered-To":"patchwork-incoming-dt@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=W59gmQgd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org;\n envelope-from=devicetree+bounces-220127-incoming-dt=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"W59gmQgd\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from ny.mirrors.kernel.org (ny.mirrors.kernel.org\n [IPv6:2604:1380:45d1:ec00::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cVnry1YBtz1yCt\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n Tue, 23 Sep 2025 02:00:50 +1000 (AEST)","from smtp.subspace.kernel.org (relay.kernel.org [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ny.mirrors.kernel.org (Postfix) with ESMTPS id 03A28175156\n\tfor <incoming-dt@patchwork.ozlabs.org>; Mon, 22 Sep 2025 16:00:49 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 953183101CD;\n\tMon, 22 Sep 2025 16:00:42 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 40BBEEEC0;\n\tMon, 22 Sep 2025 16:00:41 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 9312AC4CEF0;\n\tMon, 22 Sep 2025 16:00:41 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1758556842; cv=none;\n b=AIZ2Twy7mX9OonUwN+0jFUW1thnaZD1nPNEp3UWCfonmIKl0B1OtGkJlM6neEzHeSyF76GuzsUKUEAMTx9jbcprE6YIvvwy+hNB2NmQIbTal4u9sNVEgCj1kB3AxvnUnFjqoaiV3KhhWnaaofJBfut36hb+Pkj2Hymsb9AN/+t4=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1758556842; c=relaxed/simple;\n\tbh=gurdba/DTsv3U8QqRqFzecsKxs5zCX7qM3Ox+fJp8HQ=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=H9O8i0M1XgZQJ3dHgAVlIeBe+ihdoVNDWiNdnnDKgewTJQJXbNsQ+iKwoB9SV9qgNa3AREVUEnWt7/KNwDLOOvK0gdGUlcafjMafpd/Zitm9PI+c2G/vG4+77ecgt7Pkb31mQmNHhB40tSLS4mbvWarauct1hZgK9QM8AaxbELk=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=W59gmQgd; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1758556841;\n\tbh=gurdba/DTsv3U8QqRqFzecsKxs5zCX7qM3Ox+fJp8HQ=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=W59gmQgdPctUTyG45puWTxq4a/dcWAgxGUxdASo4fqk9kIAuo1Rt7L2MuotxNYoXc\n\t d2mdX20+NU+uYrvBRpOP35HueZEPXa7tm1Nh9WfiRXsINRqceeJtjKa0unyUJxZeal\n\t 8AH3YVieOZfp9JNU/+2eoIghAA+oVyl9J6DwjrWAO+fiBAlfrReDQFyj9BxJwWfHzH\n\t gQiHTxe7IW8YqgfHN/OKpw4Cy8Cgyi+3TO8Im/87UNo1FTzHY3ZTs86UA914UbJu89\n\t 8brQy3zw1JZG/eoAXFcyfTDGpQMvPswjmFwBazEjpPUfF6Zcoo2qk4Vn6Xbi4r/H0u\n\t P/912Bgy/W3Nw==","Date":"Mon, 22 Sep 2025 11:00:40 -0500","From":"Rob Herring <robh@kernel.org>","To":"Svyatoslav Ryhel <clamor95@gmail.com>","Cc":"Krzysztof Kozlowski <krzk@kernel.org>,\n\tConor Dooley <conor+dt@kernel.org>,\n\tThierry Reding <treding@nvidia.com>,\n\tThierry Reding <thierry.reding@gmail.com>,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n\tPrashant Gaikwad <pgaikwad@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@kernel.org>, Dmitry Osipenko <digetx@gmail.com>,\n\tMyungJoo Ham <myungjoo.ham@samsung.com>,\n\tKyungmin Park <kyungmin.park@samsung.com>,\n\tChanwoo Choi <cw00.choi@samsung.com>, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-tegra@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-pm@vger.kernel.org","Subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","Message-ID":"<20250922160040.GA92842-robh@kernel.org>","References":"<20250915080157.28195-1-clamor95@gmail.com>\n <20250915080157.28195-4-clamor95@gmail.com>","Precedence":"bulk","X-Mailing-List":"devicetree@vger.kernel.org","List-Id":"<devicetree.vger.kernel.org>","List-Subscribe":"<mailto:devicetree+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:devicetree+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20250915080157.28195-4-clamor95@gmail.com>"}},{"id":3585255,"web_url":"http://patchwork.ozlabs.org/comment/3585255/","msgid":"<CAPVz0n3cmFC1PdFnLJ0Vf60i3c6pDO9Lvi8dmAHzBgwgsrPXnA@mail.gmail.com>","list_archive_url":null,"date":"2025-09-22T16:18:00","subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/people/84146/","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"content":"пн, 22 вер. 2025 р. о 19:00 Rob Herring <robh@kernel.org> пише:\n>\n> On Mon, Sep 15, 2025 at 11:01:49AM +0300, Svyatoslav Ryhel wrote:\n> > Add Tegra114 support into existing Tegra124 MC schema with the most\n> > notable difference in the amount of EMEM timings.\n> >\n> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>\n> > ---\n> >  .../nvidia,tegra124-mc.yaml                   | 97 ++++++++++++++-----\n> >  1 file changed, 74 insertions(+), 23 deletions(-)\n> >\n> > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > index 7b18b4d11e0a..9cc9360d3bd0 100644\n> > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > @@ -19,7 +19,9 @@ description: |\n> >\n> >  properties:\n> >    compatible:\n> > -    const: nvidia,tegra124-mc\n> > +    enum:\n> > +      - nvidia,tegra114-mc\n> > +      - nvidia,tegra124-mc\n> >\n> >    reg:\n> >      maxItems: 1\n> > @@ -64,29 +66,10 @@ patternProperties:\n> >\n> >            nvidia,emem-configuration:\n> >              $ref: /schemas/types.yaml#/definitions/uint32-array\n> > -            description: |\n> > +            description:\n> >                Values to be written to the EMEM register block. See section\n> > -              \"15.6.1 MC Registers\" in the TRM.\n> > -            items:\n> > -              - description: MC_EMEM_ARB_CFG\n> > -              - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > -              - description: MC_EMEM_ARB_TIMING_RCD\n> > -              - description: MC_EMEM_ARB_TIMING_RP\n> > -              - description: MC_EMEM_ARB_TIMING_RC\n> > -              - description: MC_EMEM_ARB_TIMING_RAS\n> > -              - description: MC_EMEM_ARB_TIMING_FAW\n> > -              - description: MC_EMEM_ARB_TIMING_RRD\n> > -              - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > -              - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > -              - description: MC_EMEM_ARB_TIMING_R2R\n> > -              - description: MC_EMEM_ARB_TIMING_W2W\n> > -              - description: MC_EMEM_ARB_TIMING_R2W\n> > -              - description: MC_EMEM_ARB_TIMING_W2R\n> > -              - description: MC_EMEM_ARB_DA_TURNS\n> > -              - description: MC_EMEM_ARB_DA_COVERS\n> > -              - description: MC_EMEM_ARB_MISC0\n> > -              - description: MC_EMEM_ARB_MISC1\n> > -              - description: MC_EMEM_ARB_RING1_THROTTLE\n> > +              \"20.11.1 MC Registers\" in the Tegea114 TRM or\n> > +              \"15.6.1 MC Registers\" in the Tegra124 TRM.\n> >\n> >          required:\n> >            - clock-frequency\n> > @@ -109,6 +92,74 @@ required:\n> >    - \"#iommu-cells\"\n> >    - \"#interconnect-cells\"\n> >\n> > +allOf:\n> > +  - if:\n> > +      properties:\n> > +        compatible:\n> > +          contains:\n> > +            enum:\n> > +              - nvidia,tegra114-mc\n> > +    then:\n> > +      patternProperties:\n> > +        \"^emc-timings-[0-9]+$\":\n> > +          patternProperties:\n> > +            \"^timing-[0-9]+$\":\n> > +              properties:\n> > +                nvidia,emem-configuration:\n> > +                  items:\n> > +                    - description: MC_EMEM_ARB_CFG\n> > +                    - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > +                    - description: MC_EMEM_ARB_TIMING_RCD\n> > +                    - description: MC_EMEM_ARB_TIMING_RP\n> > +                    - description: MC_EMEM_ARB_TIMING_RC\n> > +                    - description: MC_EMEM_ARB_TIMING_RAS\n> > +                    - description: MC_EMEM_ARB_TIMING_FAW\n> > +                    - description: MC_EMEM_ARB_TIMING_RRD\n> > +                    - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > +                    - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > +                    - description: MC_EMEM_ARB_TIMING_R2R\n> > +                    - description: MC_EMEM_ARB_TIMING_W2W\n> > +                    - description: MC_EMEM_ARB_TIMING_R2W\n> > +                    - description: MC_EMEM_ARB_TIMING_W2R\n> > +                    - description: MC_EMEM_ARB_DA_TURNS\n> > +                    - description: MC_EMEM_ARB_DA_COVERS\n> > +                    - description: MC_EMEM_ARB_MISC0\n> > +                    - description: MC_EMEM_ARB_RING1_THROTTLE\n>\n> Like I said before, I don't think it is worth enumerating the list of\n> registers for every variant. If you want to define the length\n> (minItems/maxItems), then that is fine.\n>\n\nIt worth because position of value matters when reading and list above\nprovides a reference to the order in which register values should be\ngrouped.\n\n> Rob","headers":{"Return-Path":"\n <devicetree+bounces-220144-incoming-dt=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming-dt@patchwork.ozlabs.org","devicetree@vger.kernel.org"],"Delivered-To":"patchwork-incoming-dt@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=CqfXrAFB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org;\n envelope-from=devicetree+bounces-220144-incoming-dt=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"CqfXrAFB\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.128.48","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from sv.mirrors.kernel.org (sv.mirrors.kernel.org\n [IPv6:2604:1380:45e3:2400::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cVpG162Ggz1yCt\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n Tue, 23 Sep 2025 02:19:05 +1000 (AEST)","from smtp.subspace.kernel.org (relay.kernel.org [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby sv.mirrors.kernel.org (Postfix) with ESMTPS id F2E793A5016\n\tfor <incoming-dt@patchwork.ozlabs.org>; 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Mon, 22 Sep 2025\n 09:18:12 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"devicetree@vger.kernel.org","List-Id":"<devicetree.vger.kernel.org>","List-Subscribe":"<mailto:devicetree+subscribe@vger.kernel.org>","List-Unsubscribe":"<mailto:devicetree+unsubscribe@vger.kernel.org>","MIME-Version":"1.0","References":"<20250915080157.28195-1-clamor95@gmail.com>\n <20250915080157.28195-4-clamor95@gmail.com>\n <20250922160040.GA92842-robh@kernel.org>","In-Reply-To":"<20250922160040.GA92842-robh@kernel.org>","From":"Svyatoslav Ryhel <clamor95@gmail.com>","Date":"Mon, 22 Sep 2025 19:18:00 +0300","X-Gm-Features":"AS18NWDpKyD99LSDk4cdtlBB0rRoc7O4fFn4mETqSbvXEWtojMeCyyIIccv8Y9w","Message-ID":"\n <CAPVz0n3cmFC1PdFnLJ0Vf60i3c6pDO9Lvi8dmAHzBgwgsrPXnA@mail.gmail.com>","Subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","To":"Rob Herring <robh@kernel.org>","Cc":"Krzysztof Kozlowski <krzk@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n\tThierry Reding <treding@nvidia.com>,\n Thierry Reding <thierry.reding@gmail.com>,\n\tJonathan Hunter <jonathanh@nvidia.com>,\n Prashant Gaikwad <pgaikwad@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n Michael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@kernel.org>, Dmitry Osipenko <digetx@gmail.com>,\n\tMyungJoo Ham <myungjoo.ham@samsung.com>,\n Kyungmin Park <kyungmin.park@samsung.com>,\n\tChanwoo Choi <cw00.choi@samsung.com>, linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-tegra@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-pm@vger.kernel.org","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3586621,"web_url":"http://patchwork.ozlabs.org/comment/3586621/","msgid":"<20250924152430.GA1735105-robh@kernel.org>","list_archive_url":null,"date":"2025-09-24T15:24:30","subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Mon, Sep 22, 2025 at 07:18:00PM +0300, Svyatoslav Ryhel wrote:\n> пн, 22 вер. 2025 р. о 19:00 Rob Herring <robh@kernel.org> пише:\n> >\n> > On Mon, Sep 15, 2025 at 11:01:49AM +0300, Svyatoslav Ryhel wrote:\n> > > Add Tegra114 support into existing Tegra124 MC schema with the most\n> > > notable difference in the amount of EMEM timings.\n> > >\n> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>\n> > > ---\n> > >  .../nvidia,tegra124-mc.yaml                   | 97 ++++++++++++++-----\n> > >  1 file changed, 74 insertions(+), 23 deletions(-)\n> > >\n> > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > > index 7b18b4d11e0a..9cc9360d3bd0 100644\n> > > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > > @@ -19,7 +19,9 @@ description: |\n> > >\n> > >  properties:\n> > >    compatible:\n> > > -    const: nvidia,tegra124-mc\n> > > +    enum:\n> > > +      - nvidia,tegra114-mc\n> > > +      - nvidia,tegra124-mc\n> > >\n> > >    reg:\n> > >      maxItems: 1\n> > > @@ -64,29 +66,10 @@ patternProperties:\n> > >\n> > >            nvidia,emem-configuration:\n> > >              $ref: /schemas/types.yaml#/definitions/uint32-array\n> > > -            description: |\n> > > +            description:\n> > >                Values to be written to the EMEM register block. See section\n> > > -              \"15.6.1 MC Registers\" in the TRM.\n> > > -            items:\n> > > -              - description: MC_EMEM_ARB_CFG\n> > > -              - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > > -              - description: MC_EMEM_ARB_TIMING_RCD\n> > > -              - description: MC_EMEM_ARB_TIMING_RP\n> > > -              - description: MC_EMEM_ARB_TIMING_RC\n> > > -              - description: MC_EMEM_ARB_TIMING_RAS\n> > > -              - description: MC_EMEM_ARB_TIMING_FAW\n> > > -              - description: MC_EMEM_ARB_TIMING_RRD\n> > > -              - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > > -              - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > > -              - description: MC_EMEM_ARB_TIMING_R2R\n> > > -              - description: MC_EMEM_ARB_TIMING_W2W\n> > > -              - description: MC_EMEM_ARB_TIMING_R2W\n> > > -              - description: MC_EMEM_ARB_TIMING_W2R\n> > > -              - description: MC_EMEM_ARB_DA_TURNS\n> > > -              - description: MC_EMEM_ARB_DA_COVERS\n> > > -              - description: MC_EMEM_ARB_MISC0\n> > > -              - description: MC_EMEM_ARB_MISC1\n> > > -              - description: MC_EMEM_ARB_RING1_THROTTLE\n> > > +              \"20.11.1 MC Registers\" in the Tegea114 TRM or\n> > > +              \"15.6.1 MC Registers\" in the Tegra124 TRM.\n> > >\n> > >          required:\n> > >            - clock-frequency\n> > > @@ -109,6 +92,74 @@ required:\n> > >    - \"#iommu-cells\"\n> > >    - \"#interconnect-cells\"\n> > >\n> > > +allOf:\n> > > +  - if:\n> > > +      properties:\n> > > +        compatible:\n> > > +          contains:\n> > > +            enum:\n> > > +              - nvidia,tegra114-mc\n> > > +    then:\n> > > +      patternProperties:\n> > > +        \"^emc-timings-[0-9]+$\":\n> > > +          patternProperties:\n> > > +            \"^timing-[0-9]+$\":\n> > > +              properties:\n> > > +                nvidia,emem-configuration:\n> > > +                  items:\n> > > +                    - description: MC_EMEM_ARB_CFG\n> > > +                    - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > > +                    - description: MC_EMEM_ARB_TIMING_RCD\n> > > +                    - description: MC_EMEM_ARB_TIMING_RP\n> > > +                    - description: MC_EMEM_ARB_TIMING_RC\n> > > +                    - description: MC_EMEM_ARB_TIMING_RAS\n> > > +                    - description: MC_EMEM_ARB_TIMING_FAW\n> > > +                    - description: MC_EMEM_ARB_TIMING_RRD\n> > > +                    - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > > +                    - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > > +                    - description: MC_EMEM_ARB_TIMING_R2R\n> > > +                    - description: MC_EMEM_ARB_TIMING_W2W\n> > > +                    - description: MC_EMEM_ARB_TIMING_R2W\n> > > +                    - description: MC_EMEM_ARB_TIMING_W2R\n> > > +                    - description: MC_EMEM_ARB_DA_TURNS\n> > > +                    - description: MC_EMEM_ARB_DA_COVERS\n> > > +                    - description: MC_EMEM_ARB_MISC0\n> > > +                    - description: MC_EMEM_ARB_RING1_THROTTLE\n> >\n> > Like I said before, I don't think it is worth enumerating the list of\n> > registers for every variant. If you want to define the length\n> > (minItems/maxItems), then that is fine.\n> >\n> \n> It worth because position of value matters when reading and list above\n> provides a reference to the order in which register values should be\n> grouped.\n\nThe schema does nothing to validate that. The only thing that gets \nvalidated is the length. It is just an opaque blob of data. I'm sure you \nhave to define the order in the driver as well. One place is enough.\n\nRob","headers":{"Return-Path":"\n <devicetree+bounces-220810-incoming-dt=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming-dt@patchwork.ozlabs.org","devicetree@vger.kernel.org"],"Delivered-To":"patchwork-incoming-dt@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=hTKD+yL+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org;\n envelope-from=devicetree+bounces-220810-incoming-dt=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"hTKD+yL+\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sv.mirrors.kernel.org (sv.mirrors.kernel.org\n [IPv6:2604:1380:45e3:2400::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cX12R1Qdwz1y2d\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n Thu, 25 Sep 2025 01:28:15 +1000 (AEST)","from smtp.subspace.kernel.org (relay.kernel.org [52.25.139.140])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby sv.mirrors.kernel.org (Postfix) with ESMTPS id 629574C255D\n\tfor <incoming-dt@patchwork.ozlabs.org>; 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