[{"id":3614515,"web_url":"http://patchwork.ozlabs.org/comment/3614515/","msgid":"<7423636.LvFx2qVVIh@senjougahara>","list_archive_url":null,"date":"2025-11-13T04:47:18","subject":"\n Re: [PATCH v3 05/11] dt-bindings: memory: Add Tegra114 memory client IDs","submitter":{"id":26499,"url":"http://patchwork.ozlabs.org/api/people/26499/","name":"Mikko Perttunen","email":"mperttunen@nvidia.com"},"content":"On Monday, September 15, 2025 5:01 PM Svyatoslav Ryhel wrote:\n> Each memory client has unique hardware ID, add these IDs.\n> \n> Signed-off-by: Svyatoslav Ryhel \n> Acked-by: Rob Herring (Arm) \n> ---\n> include/dt-bindings/memory/tegra114-mc.h | 67 ++++++++++++++++++++++++\n> 1 file changed, 67 insertions(+)\n> \n> diff --git a/include/dt-bindings/memory/tegra114-mc.h b/include/dt-bindings/memory/tegra114-mc.h\n> index dfe99c8a5ba5..5e0d6a1b91f2 100644\n> --- a/include/dt-bindings/memory/tegra114-mc.h\n> +++ b/include/dt-bindings/memory/tegra114-mc.h\n> @@ -40,4 +40,71 @@\n> #define TEGRA114_MC_RESET_VDE\t\t14\n> #define TEGRA114_MC_RESET_VI\t\t15\n> \n> +#define TEGRA114_MC_PTCR\t\t0\n> +#define TEGRA114_MC_DISPLAY0A\t\t1\n> +#define TEGRA114_MC_DISPLAY0AB\t\t2\n> +#define TEGRA114_MC_DISPLAY0B\t\t3\n> +#define TEGRA114_MC_DISPLAY0BB\t\t4\n> +#define TEGRA114_MC_DISPLAY0C\t\t5\n> +#define TEGRA114_MC_DISPLAY0CB\t\t6\n> +#define TEGRA114_MC_DISPLAY1B\t\t7\n> +#define TEGRA114_MC_DISPLAY1BB\t\t8\n> +#define TEGRA114_MC_EPPUP\t\t9\n> +#define TEGRA114_MC_G2PR\t\t10\n> +#define TEGRA114_MC_G2SR\t\t11\n> +#define TEGRA114_MC_MPEUNIFBR\t\t12\n> +#define TEGRA114_MC_VIRUV\t\t13\n> +#define TEGRA114_MC_AFIR\t\t14\n> +#define TEGRA114_MC_AVPCARM7R\t\t15\n> +#define TEGRA114_MC_DISPLAYHC\t\t16\n> +#define TEGRA114_MC_DISPLAYHCB\t\t17\n> +#define TEGRA114_MC_FDCDRD\t\t18\n> +#define TEGRA114_MC_FDCDRD2\t\t19\n> +#define TEGRA114_MC_G2DR\t\t20\n> +#define TEGRA114_MC_HDAR\t\t21\n> +#define TEGRA114_MC_HOST1XDMAR\t\t22\n> +#define TEGRA114_MC_HOST1XR\t\t23\n> +#define TEGRA114_MC_IDXSRD\t\t24\n> +#define TEGRA114_MC_IDXSRD2\t\t25\n> +#define TEGRA114_MC_MPE_IPRED\t\t26\n> +#define TEGRA114_MC_MPEAMEMRD\t\t27\n> +#define TEGRA114_MC_MPECSRD\t\t28\n> +#define TEGRA114_MC_PPCSAHBDMAR\t\t29\n> +#define TEGRA114_MC_PPCSAHBSLVR\t\t30\n> +#define TEGRA114_MC_SATAR\t\t31\n> +#define TEGRA114_MC_TEXSRD\t\t32\n> +#define TEGRA114_MC_TEXSRD2\t\t33\n> +#define TEGRA114_MC_VDEBSEVR\t\t34\n> +#define TEGRA114_MC_VDEMBER\t\t35\n> +#define TEGRA114_MC_VDEMCER\t\t36\n> +#define TEGRA114_MC_VDETPER\t\t37\n> +#define TEGRA114_MC_MPCORELPR\t\t38\n> +#define TEGRA114_MC_MPCORER\t\t39\n> +#define TEGRA114_MC_EPPU\t\t40\n> +#define TEGRA114_MC_EPPV\t\t41\n> +#define TEGRA114_MC_EPPY\t\t42\n> +#define TEGRA114_MC_MPEUNIFBW\t\t43\n> +#define TEGRA114_MC_VIWSB\t\t44\n> +#define TEGRA114_MC_VIWU\t\t45\n> +#define TEGRA114_MC_VIWV\t\t46\n> +#define TEGRA114_MC_VIWY\t\t47\n> +#define TEGRA114_MC_G2DW\t\t48\n> +#define TEGRA114_MC_AFIW\t\t49\n> +#define TEGRA114_MC_AVPCARM7W\t\t50\n> +#define TEGRA114_MC_FDCDWR\t\t51\n> +#define TEGRA114_MC_FDCDWR2\t\t52\n> +#define TEGRA114_MC_HDAW\t\t53\n> +#define TEGRA114_MC_HOST1XW\t\t54\n> +#define TEGRA114_MC_ISPW\t\t55\n> +#define TEGRA114_MC_MPCORELPW\t\t56\n> +#define TEGRA114_MC_MPCOREW\t\t57\n> +#define TEGRA114_MC_MPECSWR\t\t58\n> +#define TEGRA114_MC_PPCSAHBDMAW\t\t59\n> +#define TEGRA114_MC_PPCSAHBSLVW\t\t60\n> +#define TEGRA114_MC_SATAW\t\t61\n> +#define TEGRA114_MC_VDEBSEVW\t\t62\n> +#define TEGRA114_MC_VDEDBGW\t\t63\n> +#define TEGRA114_MC_VDEMBEW\t\t64\n> +#define TEGRA114_MC_VDETPMW\t\t65\n> +\n> #endif\n> \n\nReviewed-by: Mikko Perttunen ","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 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