[{"id":3614514,"web_url":"http://patchwork.ozlabs.org/comment/3614514/","msgid":"<8942558.lOV4Wx5bFT@senjougahara>","list_archive_url":null,"date":"2025-11-13T04:36:24","subject":"\n Re: [PATCH v3 04/11] memory: tegra: implement EMEM regs and ICC ops for\n Tegra114","submitter":{"id":26499,"url":"http://patchwork.ozlabs.org/api/people/26499/","name":"Mikko Perttunen","email":"mperttunen@nvidia.com"},"content":"On Monday, September 15, 2025 5:01 PM Svyatoslav Ryhel wrote:\n> Prepare Internal Memory Controller for introduction of External Memory\n> Controller.\n> \n> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>\n> ---\n>  drivers/memory/tegra/tegra114.c | 193 ++++++++++++++++++++++++++++++++\n>  1 file changed, 193 insertions(+)\n> \n> diff --git a/drivers/memory/tegra/tegra114.c b/drivers/memory/tegra/tegra114.c\n> index d03a5d162dbd..c615857f7fad 100644\n> --- a/drivers/memory/tegra/tegra114.c\n> +++ b/drivers/memory/tegra/tegra114.c\n> @@ -3,6 +3,7 @@\n>   * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.\n>   */\n>  \n> +#include <linux/device.h>\n>  #include <linux/of.h>\n>  #include <linux/mm.h>\n>  \n> @@ -1165,6 +1166,195 @@ static const struct tegra_mc_reset tegra114_mc_resets[] = {\n>  \tTEGRA114_MC_RESET(VI,       0x200, 0x204, 17),\n>  };\n>  \n> +static void tegra114_mc_tune_client_latency(struct tegra_mc *mc,\n> +\t\t\t\t\t    const struct tegra_mc_client *client,\n> +\t\t\t\t\t    unsigned int bandwidth_mbytes_sec)\n> +{\n> +\tu32 arb_tolerance_compensation_nsec, arb_tolerance_compensation_div;\n> +\tunsigned int fifo_size = client->fifo_size;\n> +\tu32 arb_nsec, la_ticks, value;\n> +\n> +\t/* see 20.3.1.1 Client Configuration in Tegra4 TRM v01p */\n> +\tif (bandwidth_mbytes_sec)\n> +\t\tarb_nsec = fifo_size * NSEC_PER_USEC / bandwidth_mbytes_sec;\n> +\telse\n> +\t\tarb_nsec = U32_MAX;\n> +\n> +\t/*\n> +\t * Latency allowness should be set with consideration for the module's\n> +\t * latency tolerance and internal buffering capabilities.\n> +\t *\n> +\t * Display memory clients use isochronous transfers and have very low\n> +\t * tolerance to a belated transfers. Hence we need to compensate the\n> +\t * memory arbitration imperfection for them in order to prevent FIFO\n> +\t * underflow condition when memory bus is busy.\n> +\t *\n> +\t * VI clients also need a stronger compensation.\n> +\t */\n> +\tswitch (client->swgroup) {\n> +\tcase TEGRA_SWGROUP_MPCORE:\n> +\tcase TEGRA_SWGROUP_PTC:\n> +\t\t/*\n> +\t\t * We always want lower latency for these clients, hence\n> +\t\t * don't touch them.\n> +\t\t */\n> +\t\treturn;\n> +\n> +\tcase TEGRA_SWGROUP_DC:\n> +\tcase TEGRA_SWGROUP_DCB:\n> +\t\tarb_tolerance_compensation_nsec = 1050;\n> +\t\tarb_tolerance_compensation_div = 2;\n> +\t\tbreak;\n> +\n> +\tcase TEGRA_SWGROUP_VI:\n> +\t\tarb_tolerance_compensation_nsec = 1050;\n> +\t\tarb_tolerance_compensation_div = 1;\n> +\t\tbreak;\n> +\n> +\tdefault:\n> +\t\tarb_tolerance_compensation_nsec = 150;\n> +\t\tarb_tolerance_compensation_div = 1;\n> +\t\tbreak;\n> +\t}\n> +\n> +\tif (arb_nsec > arb_tolerance_compensation_nsec)\n> +\t\tarb_nsec -= arb_tolerance_compensation_nsec;\n> +\telse\n> +\t\tarb_nsec = 0;\n> +\n> +\tarb_nsec /= arb_tolerance_compensation_div;\n> +\n> +\t/*\n> +\t * Latency allowance is a number of ticks a request from a particular\n> +\t * client may wait in the EMEM arbiter before it becomes a high-priority\n> +\t * request.\n> +\t */\n> +\tla_ticks = arb_nsec / mc->tick;\n> +\tla_ticks = min(la_ticks, client->regs.la.mask);\n> +\n> +\tvalue = mc_readl(mc, client->regs.la.reg);\n> +\tvalue &= ~(client->regs.la.mask << client->regs.la.shift);\n> +\tvalue |= la_ticks << client->regs.la.shift;\n> +\tmc_writel(mc, value, client->regs.la.reg);\n> +}\n> +\n> +static int tegra114_mc_icc_set(struct icc_node *src, struct icc_node *dst)\n> +{\n> +\tstruct tegra_mc *mc = icc_provider_to_tegra_mc(src->provider);\n> +\tconst struct tegra_mc_client *client = &mc->soc->clients[src->id];\n> +\tu64 peak_bandwidth = icc_units_to_bps(src->peak_bw);\n> +\n> +\t/*\n> +\t * Skip pre-initialization that is done by icc_node_add(), which sets\n> +\t * bandwidth to maximum for all clients before drivers are loaded.\n> +\t *\n> +\t * This doesn't make sense for us because we don't have drivers for all\n> +\t * clients and it's okay to keep configuration left from bootloader\n> +\t * during boot, at least for today.\n> +\t */\n> +\tif (src == dst)\n> +\t\treturn 0;\n> +\n> +\t/* convert bytes/sec to megabytes/sec */\n> +\tdo_div(peak_bandwidth, 1000000);\n> +\n> +\ttegra114_mc_tune_client_latency(mc, client, peak_bandwidth);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int tegra114_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,\n> +\t\t\t\t    u32 peak_bw, u32 *agg_avg, u32 *agg_peak)\n> +{\n> +\t/*\n> +\t * ISO clients need to reserve extra bandwidth up-front because\n> +\t * there could be high bandwidth pressure during initial filling\n> +\t * of the client's FIFO buffers.  Secondly, we need to take into\n> +\t * account impurities of the memory subsystem.\n> +\t */\n> +\tif (tag & TEGRA_MC_ICC_TAG_ISO)\n> +\t\tpeak_bw = tegra_mc_scale_percents(peak_bw, 400);\n> +\n> +\t*agg_avg += avg_bw;\n> +\t*agg_peak = max(*agg_peak, peak_bw);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static struct icc_node_data *\n> +tegra114_mc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data)\n> +{\n> +\tstruct tegra_mc *mc = icc_provider_to_tegra_mc(data);\n> +\tconst struct tegra_mc_client *client;\n> +\tunsigned int i, idx = spec->args[0];\n> +\tstruct icc_node_data *ndata;\n> +\tstruct icc_node *node;\n> +\n> +\tlist_for_each_entry(node, &mc->provider.nodes, node_list) {\n> +\t\tif (node->id != idx)\n> +\t\t\tcontinue;\n> +\n> +\t\tndata = kzalloc(sizeof(*ndata), GFP_KERNEL);\n> +\t\tif (!ndata)\n> +\t\t\treturn ERR_PTR(-ENOMEM);\n> +\n> +\t\tclient = &mc->soc->clients[idx];\n> +\t\tndata->node = node;\n> +\n> +\t\tswitch (client->swgroup) {\n> +\t\tcase TEGRA_SWGROUP_DC:\n> +\t\tcase TEGRA_SWGROUP_DCB:\n> +\t\tcase TEGRA_SWGROUP_PTC:\n> +\t\tcase TEGRA_SWGROUP_VI:\n> +\t\t\t/* these clients are isochronous by default */\n> +\t\t\tndata->tag = TEGRA_MC_ICC_TAG_ISO;\n> +\t\t\tbreak;\n> +\n> +\t\tdefault:\n> +\t\t\tndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;\n> +\t\t\tbreak;\n> +\t\t}\n> +\n> +\t\treturn ndata;\n> +\t}\n> +\n> +\tfor (i = 0; i < mc->soc->num_clients; i++) {\n> +\t\tif (mc->soc->clients[i].id == idx)\n> +\t\t\treturn ERR_PTR(-EPROBE_DEFER);\n> +\t}\n> +\n> +\tdev_err(mc->dev, \"invalid ICC client ID %u\\n\", idx);\n> +\n> +\treturn ERR_PTR(-EINVAL);\n> +}\n> +\n> +static const struct tegra_mc_icc_ops tegra114_mc_icc_ops = {\n> +\t.xlate_extended = tegra114_mc_of_icc_xlate_extended,\n> +\t.aggregate = tegra114_mc_icc_aggreate,\n> +\t.set = tegra114_mc_icc_set,\n> +};\n> +\n> +static const unsigned long tegra114_mc_emem_regs[] = {\n> +\tMC_EMEM_ARB_CFG,\n> +\tMC_EMEM_ARB_OUTSTANDING_REQ,\n> +\tMC_EMEM_ARB_TIMING_RCD,\n> +\tMC_EMEM_ARB_TIMING_RP,\n> +\tMC_EMEM_ARB_TIMING_RC,\n> +\tMC_EMEM_ARB_TIMING_RAS,\n> +\tMC_EMEM_ARB_TIMING_FAW,\n> +\tMC_EMEM_ARB_TIMING_RRD,\n> +\tMC_EMEM_ARB_TIMING_RAP2PRE,\n> +\tMC_EMEM_ARB_TIMING_WAP2PRE,\n> +\tMC_EMEM_ARB_TIMING_R2R,\n> +\tMC_EMEM_ARB_TIMING_W2W,\n> +\tMC_EMEM_ARB_TIMING_R2W,\n> +\tMC_EMEM_ARB_TIMING_W2R,\n> +\tMC_EMEM_ARB_DA_TURNS,\n> +\tMC_EMEM_ARB_DA_COVERS,\n> +\tMC_EMEM_ARB_MISC0,\n> +\tMC_EMEM_ARB_RING1_THROTTLE,\n> +};\n> +\n>  const struct tegra_mc_soc tegra114_mc_soc = {\n>  \t.clients = tegra114_mc_clients,\n>  \t.num_clients = ARRAY_SIZE(tegra114_mc_clients),\n> @@ -1172,10 +1362,13 @@ const struct tegra_mc_soc tegra114_mc_soc = {\n>  \t.atom_size = 32,\n>  \t.client_id_mask = 0x7f,\n>  \t.smmu = &tegra114_smmu_soc,\n> +\t.emem_regs = tegra114_mc_emem_regs,\n> +\t.num_emem_regs = ARRAY_SIZE(tegra114_mc_emem_regs),\n>  \t.intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |\n>  \t\t   MC_INT_DECERR_EMEM,\n>  \t.reset_ops = &tegra_mc_reset_ops_common,\n>  \t.resets = tegra114_mc_resets,\n>  \t.num_resets = ARRAY_SIZE(tegra114_mc_resets),\n> +\t.icc_ops = &tegra114_mc_icc_ops,\n>  \t.ops = &tegra30_mc_ops,\n>  };\n> \n\nReviewed-by: Mikko Perttunen <mperttunen@nvidia.com>","headers":{"Return-Path":"\n <linux-tegra+bounces-10398-incoming=patchwork.ozlabs.org@vger.kernel.org>","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=b6rqhx+D;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2a01:60a::1994:3:14; helo=ams.mirrors.kernel.org;\n envelope-from=linux-tegra+bounces-10398-incoming=patchwork.ozlabs.org@vger.kernel.org;\n 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