[{"id":3585228,"web_url":"http://patchwork.ozlabs.org/comment/3585228/","msgid":"<20250922160040.GA92842-robh@kernel.org>","list_archive_url":null,"date":"2025-09-22T16:00:40","subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Mon, Sep 15, 2025 at 11:01:49AM +0300, Svyatoslav Ryhel wrote:\n> Add Tegra114 support into existing Tegra124 MC schema with the most\n> notable difference in the amount of EMEM timings.\n> \n> Signed-off-by: Svyatoslav Ryhel \n> ---\n> .../nvidia,tegra124-mc.yaml | 97 ++++++++++++++-----\n> 1 file changed, 74 insertions(+), 23 deletions(-)\n> \n> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> index 7b18b4d11e0a..9cc9360d3bd0 100644\n> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> @@ -19,7 +19,9 @@ description: |\n> \n> properties:\n> compatible:\n> - const: nvidia,tegra124-mc\n> + enum:\n> + - nvidia,tegra114-mc\n> + - nvidia,tegra124-mc\n> \n> reg:\n> maxItems: 1\n> @@ -64,29 +66,10 @@ patternProperties:\n> \n> nvidia,emem-configuration:\n> $ref: /schemas/types.yaml#/definitions/uint32-array\n> - description: |\n> + description:\n> Values to be written to the EMEM register block. See section\n> - \"15.6.1 MC Registers\" in the TRM.\n> - items:\n> - - description: MC_EMEM_ARB_CFG\n> - - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> - - description: MC_EMEM_ARB_TIMING_RCD\n> - - description: MC_EMEM_ARB_TIMING_RP\n> - - description: MC_EMEM_ARB_TIMING_RC\n> - - description: MC_EMEM_ARB_TIMING_RAS\n> - - description: MC_EMEM_ARB_TIMING_FAW\n> - - description: MC_EMEM_ARB_TIMING_RRD\n> - - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> - - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> - - description: MC_EMEM_ARB_TIMING_R2R\n> - - description: MC_EMEM_ARB_TIMING_W2W\n> - - description: MC_EMEM_ARB_TIMING_R2W\n> - - description: MC_EMEM_ARB_TIMING_W2R\n> - - description: MC_EMEM_ARB_DA_TURNS\n> - - description: MC_EMEM_ARB_DA_COVERS\n> - - description: MC_EMEM_ARB_MISC0\n> - - description: MC_EMEM_ARB_MISC1\n> - - description: MC_EMEM_ARB_RING1_THROTTLE\n> + \"20.11.1 MC Registers\" in the Tegea114 TRM or\n> + \"15.6.1 MC Registers\" in the Tegra124 TRM.\n> \n> required:\n> - clock-frequency\n> @@ -109,6 +92,74 @@ required:\n> - \"#iommu-cells\"\n> - \"#interconnect-cells\"\n> \n> +allOf:\n> + - if:\n> + properties:\n> + compatible:\n> + contains:\n> + enum:\n> + - nvidia,tegra114-mc\n> + then:\n> + patternProperties:\n> + \"^emc-timings-[0-9]+$\":\n> + patternProperties:\n> + \"^timing-[0-9]+$\":\n> + properties:\n> + nvidia,emem-configuration:\n> + items:\n> + - description: MC_EMEM_ARB_CFG\n> + - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> + - description: MC_EMEM_ARB_TIMING_RCD\n> + - description: MC_EMEM_ARB_TIMING_RP\n> + - description: MC_EMEM_ARB_TIMING_RC\n> + - description: MC_EMEM_ARB_TIMING_RAS\n> + - description: MC_EMEM_ARB_TIMING_FAW\n> + - description: MC_EMEM_ARB_TIMING_RRD\n> + - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> + - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> + - description: MC_EMEM_ARB_TIMING_R2R\n> + - description: MC_EMEM_ARB_TIMING_W2W\n> + - description: MC_EMEM_ARB_TIMING_R2W\n> + - description: MC_EMEM_ARB_TIMING_W2R\n> + - description: MC_EMEM_ARB_DA_TURNS\n> + - description: MC_EMEM_ARB_DA_COVERS\n> + - description: MC_EMEM_ARB_MISC0\n> + - description: MC_EMEM_ARB_RING1_THROTTLE\n\nLike I said before, I don't think it is worth enumerating the list of \nregisters for every variant. If you want to define the length \n(minItems/maxItems), then that is fine.\n\nRob","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=W59gmQgd;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45d1:ec00::1; helo=ny.mirrors.kernel.org;\n envelope-from=linux-tegra+bounces-9413-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"W59gmQgd\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from ny.mirrors.kernel.org (ny.mirrors.kernel.org\n [IPv6:2604:1380:45d1:ec00::1])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cVnrv3Fnjz1yCt\n\tfor ; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20250915080157.28195-4-clamor95@gmail.com>"}},{"id":3585253,"web_url":"http://patchwork.ozlabs.org/comment/3585253/","msgid":"","list_archive_url":null,"date":"2025-09-22T16:18:00","subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","submitter":{"id":84146,"url":"http://patchwork.ozlabs.org/api/people/84146/","name":"Svyatoslav Ryhel","email":"clamor95@gmail.com"},"content":"пн, 22 вер. 2025 р. о 19:00 Rob Herring пише:\n>\n> On Mon, Sep 15, 2025 at 11:01:49AM +0300, Svyatoslav Ryhel wrote:\n> > Add Tegra114 support into existing Tegra124 MC schema with the most\n> > notable difference in the amount of EMEM timings.\n> >\n> > Signed-off-by: Svyatoslav Ryhel \n> > ---\n> > .../nvidia,tegra124-mc.yaml | 97 ++++++++++++++-----\n> > 1 file changed, 74 insertions(+), 23 deletions(-)\n> >\n> > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > index 7b18b4d11e0a..9cc9360d3bd0 100644\n> > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > @@ -19,7 +19,9 @@ description: |\n> >\n> > properties:\n> > compatible:\n> > - const: nvidia,tegra124-mc\n> > + enum:\n> > + - nvidia,tegra114-mc\n> > + - nvidia,tegra124-mc\n> >\n> > reg:\n> > maxItems: 1\n> > @@ -64,29 +66,10 @@ patternProperties:\n> >\n> > nvidia,emem-configuration:\n> > $ref: /schemas/types.yaml#/definitions/uint32-array\n> > - description: |\n> > + description:\n> > Values to be written to the EMEM register block. See section\n> > - \"15.6.1 MC Registers\" in the TRM.\n> > - items:\n> > - - description: MC_EMEM_ARB_CFG\n> > - - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > - - description: MC_EMEM_ARB_TIMING_RCD\n> > - - description: MC_EMEM_ARB_TIMING_RP\n> > - - description: MC_EMEM_ARB_TIMING_RC\n> > - - description: MC_EMEM_ARB_TIMING_RAS\n> > - - description: MC_EMEM_ARB_TIMING_FAW\n> > - - description: MC_EMEM_ARB_TIMING_RRD\n> > - - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > - - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > - - description: MC_EMEM_ARB_TIMING_R2R\n> > - - description: MC_EMEM_ARB_TIMING_W2W\n> > - - description: MC_EMEM_ARB_TIMING_R2W\n> > - - description: MC_EMEM_ARB_TIMING_W2R\n> > - - description: MC_EMEM_ARB_DA_TURNS\n> > - - description: MC_EMEM_ARB_DA_COVERS\n> > - - description: MC_EMEM_ARB_MISC0\n> > - - description: MC_EMEM_ARB_MISC1\n> > - - description: MC_EMEM_ARB_RING1_THROTTLE\n> > + \"20.11.1 MC Registers\" in the Tegea114 TRM or\n> > + \"15.6.1 MC Registers\" in the Tegra124 TRM.\n> >\n> > required:\n> > - clock-frequency\n> > @@ -109,6 +92,74 @@ required:\n> > - \"#iommu-cells\"\n> > - \"#interconnect-cells\"\n> >\n> > +allOf:\n> > + - if:\n> > + properties:\n> > + compatible:\n> > + contains:\n> > + enum:\n> > + - nvidia,tegra114-mc\n> > + then:\n> > + patternProperties:\n> > + \"^emc-timings-[0-9]+$\":\n> > + patternProperties:\n> > + \"^timing-[0-9]+$\":\n> > + properties:\n> > + nvidia,emem-configuration:\n> > + items:\n> > + - description: MC_EMEM_ARB_CFG\n> > + - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > + - description: MC_EMEM_ARB_TIMING_RCD\n> > + - description: MC_EMEM_ARB_TIMING_RP\n> > + - description: MC_EMEM_ARB_TIMING_RC\n> > + - description: MC_EMEM_ARB_TIMING_RAS\n> > + - description: MC_EMEM_ARB_TIMING_FAW\n> > + - description: MC_EMEM_ARB_TIMING_RRD\n> > + - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > + - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > + - description: MC_EMEM_ARB_TIMING_R2R\n> > + - description: MC_EMEM_ARB_TIMING_W2W\n> > + - description: MC_EMEM_ARB_TIMING_R2W\n> > + - description: MC_EMEM_ARB_TIMING_W2R\n> > + - description: MC_EMEM_ARB_DA_TURNS\n> > + - description: MC_EMEM_ARB_DA_COVERS\n> > + - description: MC_EMEM_ARB_MISC0\n> > + - description: MC_EMEM_ARB_RING1_THROTTLE\n>\n> Like I said before, I don't think it is worth enumerating the list of\n> registers for every variant. If you want to define the length\n> (minItems/maxItems), then that is fine.\n>\n\nIt worth because position of value matters when reading and list above\nprovides a reference to the order in which register values should be\ngrouped.\n\n> Rob","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=CqfXrAFB;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org;\n envelope-from=linux-tegra+bounces-9414-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"CqfXrAFB\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.221.53","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from am.mirrors.kernel.org (am.mirrors.kernel.org\n [IPv6:2604:1380:4601:e00::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cVpF82MrCz1yCt\n\tfor ; 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Mon, 22 Sep 2025\n 09:18:12 -0700 (PDT)","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20250915080157.28195-1-clamor95@gmail.com>\n <20250915080157.28195-4-clamor95@gmail.com>\n <20250922160040.GA92842-robh@kernel.org>","In-Reply-To":"<20250922160040.GA92842-robh@kernel.org>","From":"Svyatoslav Ryhel ","Date":"Mon, 22 Sep 2025 19:18:00 +0300","X-Gm-Features":"AS18NWDpKyD99LSDk4cdtlBB0rRoc7O4fFn4mETqSbvXEWtojMeCyyIIccv8Y9w","Message-ID":"\n ","Subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","To":"Rob Herring ","Cc":"Krzysztof Kozlowski , Conor Dooley ,\n\tThierry Reding ,\n Thierry Reding ,\n\tJonathan Hunter ,\n Prashant Gaikwad ,\n\tMikko Perttunen ,\n Michael Turquette ,\n\tStephen Boyd , Dmitry Osipenko ,\n\tMyungJoo Ham ,\n Kyungmin Park ,\n\tChanwoo Choi , linux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-tegra@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-pm@vger.kernel.org","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3586617,"web_url":"http://patchwork.ozlabs.org/comment/3586617/","msgid":"<20250924152430.GA1735105-robh@kernel.org>","list_archive_url":null,"date":"2025-09-24T15:24:30","subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Mon, Sep 22, 2025 at 07:18:00PM +0300, Svyatoslav Ryhel wrote:\n> пн, 22 вер. 2025 р. о 19:00 Rob Herring пише:\n> >\n> > On Mon, Sep 15, 2025 at 11:01:49AM +0300, Svyatoslav Ryhel wrote:\n> > > Add Tegra114 support into existing Tegra124 MC schema with the most\n> > > notable difference in the amount of EMEM timings.\n> > >\n> > > Signed-off-by: Svyatoslav Ryhel \n> > > ---\n> > > .../nvidia,tegra124-mc.yaml | 97 ++++++++++++++-----\n> > > 1 file changed, 74 insertions(+), 23 deletions(-)\n> > >\n> > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > > index 7b18b4d11e0a..9cc9360d3bd0 100644\n> > > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > > @@ -19,7 +19,9 @@ description: |\n> > >\n> > > properties:\n> > > compatible:\n> > > - const: nvidia,tegra124-mc\n> > > + enum:\n> > > + - nvidia,tegra114-mc\n> > > + - nvidia,tegra124-mc\n> > >\n> > > reg:\n> > > maxItems: 1\n> > > @@ -64,29 +66,10 @@ patternProperties:\n> > >\n> > > nvidia,emem-configuration:\n> > > $ref: /schemas/types.yaml#/definitions/uint32-array\n> > > - description: |\n> > > + description:\n> > > Values to be written to the EMEM register block. See section\n> > > - \"15.6.1 MC Registers\" in the TRM.\n> > > - items:\n> > > - - description: MC_EMEM_ARB_CFG\n> > > - - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > > - - description: MC_EMEM_ARB_TIMING_RCD\n> > > - - description: MC_EMEM_ARB_TIMING_RP\n> > > - - description: MC_EMEM_ARB_TIMING_RC\n> > > - - description: MC_EMEM_ARB_TIMING_RAS\n> > > - - description: MC_EMEM_ARB_TIMING_FAW\n> > > - - description: MC_EMEM_ARB_TIMING_RRD\n> > > - - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > > - - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > > - - description: MC_EMEM_ARB_TIMING_R2R\n> > > - - description: MC_EMEM_ARB_TIMING_W2W\n> > > - - description: MC_EMEM_ARB_TIMING_R2W\n> > > - - description: MC_EMEM_ARB_TIMING_W2R\n> > > - - description: MC_EMEM_ARB_DA_TURNS\n> > > - - description: MC_EMEM_ARB_DA_COVERS\n> > > - - description: MC_EMEM_ARB_MISC0\n> > > - - description: MC_EMEM_ARB_MISC1\n> > > - - description: MC_EMEM_ARB_RING1_THROTTLE\n> > > + \"20.11.1 MC Registers\" in the Tegea114 TRM or\n> > > + \"15.6.1 MC Registers\" in the Tegra124 TRM.\n> > >\n> > > required:\n> > > - clock-frequency\n> > > @@ -109,6 +92,74 @@ required:\n> > > - \"#iommu-cells\"\n> > > - \"#interconnect-cells\"\n> > >\n> > > +allOf:\n> > > + - if:\n> > > + properties:\n> > > + compatible:\n> > > + contains:\n> > > + enum:\n> > > + - nvidia,tegra114-mc\n> > > + then:\n> > > + patternProperties:\n> > > + \"^emc-timings-[0-9]+$\":\n> > > + patternProperties:\n> > > + \"^timing-[0-9]+$\":\n> > > + properties:\n> > > + nvidia,emem-configuration:\n> > > + items:\n> > > + - description: MC_EMEM_ARB_CFG\n> > > + - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > > + - description: MC_EMEM_ARB_TIMING_RCD\n> > > + - description: MC_EMEM_ARB_TIMING_RP\n> > > + - description: MC_EMEM_ARB_TIMING_RC\n> > > + - description: MC_EMEM_ARB_TIMING_RAS\n> > > + - description: MC_EMEM_ARB_TIMING_FAW\n> > > + - description: MC_EMEM_ARB_TIMING_RRD\n> > > + - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > > + - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > > + - description: MC_EMEM_ARB_TIMING_R2R\n> > > + - description: MC_EMEM_ARB_TIMING_W2W\n> > > + - description: MC_EMEM_ARB_TIMING_R2W\n> > > + - description: MC_EMEM_ARB_TIMING_W2R\n> > > + - description: MC_EMEM_ARB_DA_TURNS\n> > > + - description: MC_EMEM_ARB_DA_COVERS\n> > > + - description: MC_EMEM_ARB_MISC0\n> > > + - description: MC_EMEM_ARB_RING1_THROTTLE\n> >\n> > Like I said before, I don't think it is worth enumerating the list of\n> > registers for every variant. If you want to define the length\n> > (minItems/maxItems), then that is fine.\n> >\n> \n> It worth because position of value matters when reading and list above\n> provides a reference to the order in which register values should be\n> grouped.\n\nThe schema does nothing to validate that. The only thing that gets \nvalidated is the length. It is just an opaque blob of data. I'm sure you \nhave to define the order in the driver as well. One place is enough.\n\nRob","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=hTKD+yL+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org;\n envelope-from=linux-tegra+bounces-9455-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"hTKD+yL+\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from am.mirrors.kernel.org (am.mirrors.kernel.org\n [IPv6:2604:1380:4601:e00::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4cX0yH4yRHz1yFv\n\tfor ; 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charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"\n "}},{"id":3621432,"web_url":"http://patchwork.ozlabs.org/comment/3621432/","msgid":"","list_archive_url":null,"date":"2025-12-01T14:18:48","subject":"Re: [PATCH v3 03/11] dt-bindings: memory: Document Tegra114 Memory\n Controller","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Wed, Sep 24, 2025 at 10:24:30AM -0500, Rob Herring wrote:\n> On Mon, Sep 22, 2025 at 07:18:00PM +0300, Svyatoslav Ryhel wrote:\n> > пн, 22 вер. 2025 р. о 19:00 Rob Herring пише:\n> > >\n> > > On Mon, Sep 15, 2025 at 11:01:49AM +0300, Svyatoslav Ryhel wrote:\n> > > > Add Tegra114 support into existing Tegra124 MC schema with the most\n> > > > notable difference in the amount of EMEM timings.\n> > > >\n> > > > Signed-off-by: Svyatoslav Ryhel \n> > > > ---\n> > > > .../nvidia,tegra124-mc.yaml | 97 ++++++++++++++-----\n> > > > 1 file changed, 74 insertions(+), 23 deletions(-)\n> > > >\n> > > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > > > index 7b18b4d11e0a..9cc9360d3bd0 100644\n> > > > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > > > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml\n> > > > @@ -19,7 +19,9 @@ description: |\n> > > >\n> > > > properties:\n> > > > compatible:\n> > > > - const: nvidia,tegra124-mc\n> > > > + enum:\n> > > > + - nvidia,tegra114-mc\n> > > > + - nvidia,tegra124-mc\n> > > >\n> > > > reg:\n> > > > maxItems: 1\n> > > > @@ -64,29 +66,10 @@ patternProperties:\n> > > >\n> > > > nvidia,emem-configuration:\n> > > > $ref: /schemas/types.yaml#/definitions/uint32-array\n> > > > - description: |\n> > > > + description:\n> > > > Values to be written to the EMEM register block. See section\n> > > > - \"15.6.1 MC Registers\" in the TRM.\n> > > > - items:\n> > > > - - description: MC_EMEM_ARB_CFG\n> > > > - - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > > > - - description: MC_EMEM_ARB_TIMING_RCD\n> > > > - - description: MC_EMEM_ARB_TIMING_RP\n> > > > - - description: MC_EMEM_ARB_TIMING_RC\n> > > > - - description: MC_EMEM_ARB_TIMING_RAS\n> > > > - - description: MC_EMEM_ARB_TIMING_FAW\n> > > > - - description: MC_EMEM_ARB_TIMING_RRD\n> > > > - - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > > > - - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > > > - - description: MC_EMEM_ARB_TIMING_R2R\n> > > > - - description: MC_EMEM_ARB_TIMING_W2W\n> > > > - - description: MC_EMEM_ARB_TIMING_R2W\n> > > > - - description: MC_EMEM_ARB_TIMING_W2R\n> > > > - - description: MC_EMEM_ARB_DA_TURNS\n> > > > - - description: MC_EMEM_ARB_DA_COVERS\n> > > > - - description: MC_EMEM_ARB_MISC0\n> > > > - - description: MC_EMEM_ARB_MISC1\n> > > > - - description: MC_EMEM_ARB_RING1_THROTTLE\n> > > > + \"20.11.1 MC Registers\" in the Tegea114 TRM or\n> > > > + \"15.6.1 MC Registers\" in the Tegra124 TRM.\n> > > >\n> > > > required:\n> > > > - clock-frequency\n> > > > @@ -109,6 +92,74 @@ required:\n> > > > - \"#iommu-cells\"\n> > > > - \"#interconnect-cells\"\n> > > >\n> > > > +allOf:\n> > > > + - if:\n> > > > + properties:\n> > > > + compatible:\n> > > > + contains:\n> > > > + enum:\n> > > > + - nvidia,tegra114-mc\n> > > > + then:\n> > > > + patternProperties:\n> > > > + \"^emc-timings-[0-9]+$\":\n> > > > + patternProperties:\n> > > > + \"^timing-[0-9]+$\":\n> > > > + properties:\n> > > > + nvidia,emem-configuration:\n> > > > + items:\n> > > > + - description: MC_EMEM_ARB_CFG\n> > > > + - description: MC_EMEM_ARB_OUTSTANDING_REQ\n> > > > + - description: MC_EMEM_ARB_TIMING_RCD\n> > > > + - description: MC_EMEM_ARB_TIMING_RP\n> > > > + - description: MC_EMEM_ARB_TIMING_RC\n> > > > + - description: MC_EMEM_ARB_TIMING_RAS\n> > > > + - description: MC_EMEM_ARB_TIMING_FAW\n> > > > + - description: MC_EMEM_ARB_TIMING_RRD\n> > > > + - description: MC_EMEM_ARB_TIMING_RAP2PRE\n> > > > + - description: MC_EMEM_ARB_TIMING_WAP2PRE\n> > > > + - description: MC_EMEM_ARB_TIMING_R2R\n> > > > + - description: MC_EMEM_ARB_TIMING_W2W\n> > > > + - description: MC_EMEM_ARB_TIMING_R2W\n> > > > + - description: MC_EMEM_ARB_TIMING_W2R\n> > > > + - description: MC_EMEM_ARB_DA_TURNS\n> > > > + - description: MC_EMEM_ARB_DA_COVERS\n> > > > + - description: MC_EMEM_ARB_MISC0\n> > > > + - description: MC_EMEM_ARB_RING1_THROTTLE\n> > >\n> > > Like I said before, I don't think it is worth enumerating the list of\n> > > registers for every variant. If you want to define the length\n> > > (minItems/maxItems), then that is fine.\n> > >\n> > \n> > It worth because position of value matters when reading and list above\n> > provides a reference to the order in which register values should be\n> > grouped.\n> \n> The schema does nothing to validate that. The only thing that gets \n> validated is the length. It is just an opaque blob of data. I'm sure you \n> have to define the order in the driver as well. One place is enough.\n\nHi Rob,\n\nSorry for being so late on this, but I just noticed that v4 had dropped\nthese items descriptions and then saw that you had suggested this. I\nhave always found the explicit mention useful because it allows DT\nwriters to know what to put into the properties without having to look\nup a specific implementation.\n\nIf the DT bindings don't specify the order, then how do we guarantee\nthat all implementations agree on the order? While it's true that no\nvalidation is done via the schema, the schema is the only specification\nthat we have for this. Without it there is no reason for an\nimplementation to pick one order over another.\n\nThierry","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=Lfhlw4OD;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=142.0.200.124; helo=dfw.mirrors.kernel.org;\n envelope-from=linux-tegra+bounces-10672-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"Lfhlw4OD\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.128.50","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from dfw.mirrors.kernel.org (dfw.mirrors.kernel.org [142.0.200.124])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dKmH66dJXz1yDq\n\tfor ; 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