[{"id":3613568,"web_url":"http://patchwork.ozlabs.org/comment/3613568/","msgid":"<3455911.aeNJFYEL58@senjougahara>","list_archive_url":null,"date":"2025-11-11T08:55:39","subject":"\n Re: [PATCH v3 01/11] devfreq: tegra30-devfreq: add support for Tegra114","submitter":{"id":26499,"url":"http://patchwork.ozlabs.org/api/people/26499/","name":"Mikko Perttunen","email":"mperttunen@nvidia.com"},"content":"On Monday, September 15, 2025 5:01 PM Svyatoslav Ryhel wrote:\n> Lets add Tegra114 support to activity monitor device as a preparation to\n> upcoming EMC controller support.\n> \n> Signed-off-by: Svyatoslav Ryhel \n> ---\n> drivers/devfreq/tegra30-devfreq.c | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c\n> index 8ea5b482bfb3..d976077d4757 100644\n> --- a/drivers/devfreq/tegra30-devfreq.c\n> +++ b/drivers/devfreq/tegra30-devfreq.c\n> @@ -980,6 +980,7 @@ static const struct tegra_devfreq_soc_data tegra30_soc = {\n> \n> static const struct of_device_id tegra_devfreq_of_match[] = {\n> \t{ .compatible = \"nvidia,tegra30-actmon\", .data = &tegra30_soc, },\n> +\t{ .compatible = \"nvidia,tegra114-actmon\", .data = &tegra124_soc, },\n> \t{ .compatible = \"nvidia,tegra124-actmon\", .data = &tegra124_soc, },\n> \t{ },\n> };\n> \n\nLooking at my copy of L4T r21, the EMC count_weight should be 256 on Tegra114, while it is 4*256 on Tegra124, so different SoC data should be used. (I haven't checked if anything else is different)\n\nCheers,\nMikko","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=Rinlr2Hn;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:4601:e00::3; helo=am.mirrors.kernel.org;\n envelope-from=linux-tegra+bounces-10325-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com\n header.b=\"Rinlr2Hn\"","smtp.subspace.kernel.org;\n arc=fail smtp.client-ip=40.107.200.1","smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) 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Prashant Gaikwad ,\n Michael Turquette , Stephen Boyd ,\n Dmitry Osipenko , MyungJoo Ham ,\n Kyungmin Park ,\n Chanwoo Choi , Svyatoslav Ryhel ,\n Svyatoslav Ryhel ","Cc":"linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,\n linux-pm@vger.kernel.org","Subject":"\n Re: [PATCH v3 01/11] devfreq: tegra30-devfreq: add support for Tegra114","Date":"Tue, 11 Nov 2025 17:55:39 +0900","Message-ID":"<3455911.aeNJFYEL58@senjougahara>","In-Reply-To":"<20250915080157.28195-2-clamor95@gmail.com>","References":"\n <20250915080157.28195-1-clamor95@gmail.com>\n <20250915080157.28195-2-clamor95@gmail.com>","Content-Transfer-Encoding":"quoted-printable","Content-Type":"text/plain; charset=\"utf-8\"","X-ClientProxiedBy":"TYCPR01CA0004.jpnprd01.prod.outlook.com (2603:1096:405::16)\n To DM4PR12MB6494.namprd12.prod.outlook.com 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Ryhel","email":"clamor95@gmail.com"},"content":"вт, 11 лист. 2025 р. о 10:55 Mikko Perttunen пише:\n>\n> On Monday, September 15, 2025 5:01 PM Svyatoslav Ryhel wrote:\n> > Lets add Tegra114 support to activity monitor device as a preparation to\n> > upcoming EMC controller support.\n> >\n> > Signed-off-by: Svyatoslav Ryhel \n> > ---\n> > drivers/devfreq/tegra30-devfreq.c | 1 +\n> > 1 file changed, 1 insertion(+)\n> >\n> > diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c\n> > index 8ea5b482bfb3..d976077d4757 100644\n> > --- a/drivers/devfreq/tegra30-devfreq.c\n> > +++ b/drivers/devfreq/tegra30-devfreq.c\n> > @@ -980,6 +980,7 @@ static const struct tegra_devfreq_soc_data tegra30_soc = {\n> >\n> > static const struct of_device_id tegra_devfreq_of_match[] = {\n> > { .compatible = \"nvidia,tegra30-actmon\", .data = &tegra30_soc, },\n> > + { .compatible = \"nvidia,tegra114-actmon\", .data = &tegra124_soc, },\n> > { .compatible = \"nvidia,tegra124-actmon\", .data = &tegra124_soc, },\n> > { },\n> > };\n> >\n>\n> Looking at my copy of L4T r21, the EMC count_weight should be 256 on Tegra114, while it is 4*256 on Tegra124, so different SoC data should be used. (I haven't checked if anything else is different)\n>\n\nYou are correct, tegra114 seems to use 1 EMC clock per transaction. I\nwill move and expand comment from tegra124 entry regarding\ncount_weight to include info about all 3 supported entries if you\ndon't mind.\n\nI have a question regarding tegra_devfreq_device_config to be used\nwith tegra114. From tegratab kernel I have, existing\ntegra124_device_configs configuration seems to fit tegra114, may you\nconfirm this? Or, if L4T r21 you use, uses different values, may you\nprovide those to fill up tegra_devfreq_device_config for tegra114.\n\n> Cheers,\n> Mikko\n>\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=TogU5/CQ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2605:f480:58:1:0:1994:3:14; helo=dfw.mirrors.kernel.org;\n envelope-from=linux-tegra+bounces-10340-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com\n header.b=\"TogU5/CQ\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=209.85.221.43","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=gmail.com"],"Received":["from dfw.mirrors.kernel.org (dfw.mirrors.kernel.org\n [IPv6:2605:f480:58:1:0:1994:3:14])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4d5SG016Bcz1xnT\n\tfor ; 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Tue, 11 Nov 2025\n 05:35:09 -0800 (PST)","Precedence":"bulk","X-Mailing-List":"linux-tegra@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","References":"<20250915080157.28195-1-clamor95@gmail.com>\n <20250915080157.28195-2-clamor95@gmail.com>\n <3455911.aeNJFYEL58@senjougahara>","In-Reply-To":"<3455911.aeNJFYEL58@senjougahara>","From":"Svyatoslav Ryhel ","Date":"Tue, 11 Nov 2025 15:34:57 +0200","X-Gm-Features":"AWmQ_blV6d3G7hE5fg-sUlAJ4jm_DAmDeF4LDT7xiVBDSmfK9MhRSP1-jMuZj_A","Message-ID":"\n ","Subject":"Re: [PATCH v3 01/11] devfreq: tegra30-devfreq: add support for\n Tegra114","To":"Mikko Perttunen ","Cc":"Krzysztof Kozlowski , Rob Herring ,\n Conor Dooley ,\n\tThierry Reding ,\n Thierry Reding ,\n\tJonathan Hunter ,\n Prashant Gaikwad ,\n\tMichael Turquette , Stephen Boyd ,\n\tDmitry Osipenko , MyungJoo Ham ,\n\tKyungmin Park ,\n Chanwoo Choi ,\n\tlinux-kernel@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-pm@vger.kernel.org","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable"}},{"id":3614511,"web_url":"http://patchwork.ozlabs.org/comment/3614511/","msgid":"<15510199.O9o76ZdvQC@senjougahara>","list_archive_url":null,"date":"2025-11-13T04:20:06","subject":"\n Re: [PATCH v3 01/11] devfreq: tegra30-devfreq: add support for Tegra114","submitter":{"id":26499,"url":"http://patchwork.ozlabs.org/api/people/26499/","name":"Mikko Perttunen","email":"mperttunen@nvidia.com"},"content":"On Tuesday, November 11, 2025 10:34 PM Svyatoslav Ryhel wrote:\n> вт, 11 лист. 2025 р. о 10:55 Mikko Perttunen пише:\n> >\n> > On Monday, September 15, 2025 5:01 PM Svyatoslav Ryhel wrote:\n> > > Lets add Tegra114 support to activity monitor device as a preparation to\n> > > upcoming EMC controller support.\n> > >\n> > > Signed-off-by: Svyatoslav Ryhel \n> > > ---\n> > > drivers/devfreq/tegra30-devfreq.c | 1 +\n> > > 1 file changed, 1 insertion(+)\n> > >\n> > > diff --git a/drivers/devfreq/tegra30-devfreq.c b/drivers/devfreq/tegra30-devfreq.c\n> > > index 8ea5b482bfb3..d976077d4757 100644\n> > > --- a/drivers/devfreq/tegra30-devfreq.c\n> > > +++ b/drivers/devfreq/tegra30-devfreq.c\n> > > @@ -980,6 +980,7 @@ static const struct tegra_devfreq_soc_data tegra30_soc = {\n> > >\n> > > static const struct of_device_id tegra_devfreq_of_match[] = {\n> > > { .compatible = \"nvidia,tegra30-actmon\", .data = &tegra30_soc, },\n> > > + { .compatible = \"nvidia,tegra114-actmon\", .data = &tegra124_soc, },\n> > > { .compatible = \"nvidia,tegra124-actmon\", .data = &tegra124_soc, },\n> > > { },\n> > > };\n> > >\n> >\n> > Looking at my copy of L4T r21, the EMC count_weight should be 256 on Tegra114, while it is 4*256 on Tegra124, so different SoC data should be used. (I haven't checked if anything else is different)\n> >\n> \n> You are correct, tegra114 seems to use 1 EMC clock per transaction. I\n> will move and expand comment from tegra124 entry regarding\n> count_weight to include info about all 3 supported entries if you\n> don't mind.\n> \n> I have a question regarding tegra_devfreq_device_config to be used\n> with tegra114. From tegratab kernel I have, existing\n> tegra124_device_configs configuration seems to fit tegra114, may you\n> confirm this? Or, if L4T r21 you use, uses different values, may you\n> provide those to fill up tegra_devfreq_device_config for tegra114.\n\nCan confirm the offset and irq mask are the same. The coefficients are a bit different in the L4T tree but they don't match the upstream tegra124 values either so I guess that's fine.\n\nHere's the exact values:\n\nstatic struct actmon_dev actmon_dev_emc = {\n .reg = 0x1c0,\n .glb_status_irq_mask = (0x1 << 26),\n .dev_id = \"tegra_actmon\",\n .con_id = \"emc\",\n\n /* EMC suspend floor to guarantee suspend entry on PLLM */\n .suspend_freq = EMC_PLLP_FREQ_MAX + 2000,\n\n .boost_freq_step = 16000,\n .boost_up_coef = 200,\n .boost_down_coef = 50,\n#if (defined(CONFIG_ARCH_TEGRA_14x_SOC) || \\\n defined(CONFIG_ARCH_TEGRA_12x_SOC) || \\\n defined(CONFIG_ARCH_TEGRA_13x_SOC))\n .boost_up_threshold = 70,\n .boost_down_threshold = 50,\n#else\n .boost_up_threshold = 60,\n .boost_down_threshold = 40,\n#endif\n\n .up_wmark_window = 1,\n .down_wmark_window = 3,\n .avg_window_log2 = ACTMON_DEFAULT_AVG_WINDOW_LOG2,\n#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)\n .count_weight = 0x200,\n#elif defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)\n .count_weight = 0x400,\n#else\n .count_weight = 0x100,\n#endif\n\n .type = ACTMON_FREQ_SAMPLER,\n .state = ACTMON_UNINITIALIZED,\n\n .rate_change_nb = {\n .notifier_call = actmon_rate_notify_cb,\n },\n};\n\n\n\n#if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)\n#define CPU_AVG_ACT_THRESHOLD 2000\n#else\n#define CPU_AVG_ACT_THRESHOLD 50000\n#endif\n/* EMC-cpu activity monitor: frequency sampling device:\n * activity counter is incremented every 256 memory transactions, and\n * each transaction takes 2 EMC clocks; count_weight = 512 on Tegra3.\n * On Tegra11 there is only 1 clock per transaction, hence weight = 256.\n */\nstatic struct actmon_dev actmon_dev_cpu_emc = {\n .reg = 0x200,\n .glb_status_irq_mask = (0x1 << 25),\n .dev_id = \"tegra_mon\",\n .con_id = \"cpu_emc\",\n\n .boost_freq_step = 16000,\n .boost_up_coef = 800,\n .boost_down_coef = 90,\n .boost_up_threshold = 27,\n .boost_down_threshold = 10,\n .avg_dependency_threshold = CPU_AVG_ACT_THRESHOLD,\n\n .up_wmark_window = 1,\n .down_wmark_window = 3,\n .avg_window_log2 = ACTMON_DEFAULT_AVG_WINDOW_LOG2,\n#if defined(CONFIG_ARCH_TEGRA_3x_SOC) || defined(CONFIG_ARCH_TEGRA_14x_SOC)\n .count_weight = 0x200,\n#elif defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_13x_SOC)\n .count_weight = 0x400,\n#else\n .count_weight = 0x100,\n#endif\n\n .type = ACTMON_FREQ_SAMPLER,\n .state = ACTMON_UNINITIALIZED,\n\n .rate_change_nb = {\n .notifier_call = actmon_rate_notify_cb,\n },\n};\n\n\n> \n> > Cheers,\n> > Mikko\n> >\n> >","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-tegra@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 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