[{"id":3318852,"web_url":"http://patchwork.ozlabs.org/comment/3318852/","msgid":"","list_archive_url":null,"date":"2024-05-29T13:06:36","subject":"Re: [DO NOT MERGE v8 13/36] dt-bindings: clock: sh7750-cpg: Add\n renesas,sh7750-cpg header.","submitter":{"id":703,"url":"http://patchwork.ozlabs.org/api/people/703/","name":"Geert Uytterhoeven","email":"geert@linux-m68k.org"},"content":"Hi Sato-san,\n\nThanks for the update!\n\nOn Wed, May 29, 2024 at 10:01 AM Yoshinori Sato\n wrote:\n> SH7750 CPG Clock output define.\n\n(from my comments on v6 and v7) Please improve the patch description.\n\n> Signed-off-by: Yoshinori Sato \n\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/clock/renesas,sh7750-cpg.yaml\n> @@ -0,0 +1,107 @@\n\n> +examples:\n> + - |\n> + #include \n> + cpg: clock-controller@ffc00000 {\n> + compatible = \"renesas,sh7751r-cpg\";\n> + reg = <0xffc00000 20>, <0xfe0a0000 16>;\n> + reg-names = \"FRQCR\", \"CLKSTP00\";\n> + clocks = <&extal>;\n> + clock-names = \"extal\";\n> + renesas,mode = <0>;\n\nNit: please move \"renesas,mode\" last.\n\n> + #clock-cells = <1>;\n> + #power-domain-cells = <0>;\n> + };\n\nGr{oetje,eeting}s,\n\n Geert","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=147.75.199.223; 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