[{"id":3245665,"web_url":"http://patchwork.ozlabs.org/comment/3245665/","msgid":"","list_archive_url":null,"date":"2024-01-11T23:29:17","subject":"Re: [PATCH v2 25/43] target/riscv: Validate misa_mxl_max only once","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Jan 4, 2024 at 5:04 AM Alex Bennée wrote:\n>\n> From: Akihiko Odaki \n>\n> misa_mxl_max is now a class member and initialized only once for each\n> class. This also moves the initialization of gdb_core_xml_file which\n> will be referenced before realization in the future.\n>\n> Signed-off-by: Akihiko Odaki \n> Message-Id: <20231213-riscv-v7-4-a760156a337f@daynix.com>\n> Signed-off-by: Alex Bennée \n\nAcked-by: Alistair Francis \n\nAlistair\n\n> ---\n> target/riscv/cpu.c | 21 +++++++++++++++++++++\n> target/riscv/tcg/tcg-cpu.c | 23 -----------------------\n> 2 files changed, 21 insertions(+), 23 deletions(-)\n>\n> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\n> index 2ab61df2217..b799f133604 100644\n> --- a/target/riscv/cpu.c\n> +++ b/target/riscv/cpu.c\n> @@ -1247,6 +1247,26 @@ static const MISAExtInfo misa_ext_info_arr[] = {\n> MISA_EXT_INFO(RVG, \"g\", \"General purpose (IMAFD_Zicsr_Zifencei)\"),\n> };\n>\n> +static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)\n> +{\n> + CPUClass *cc = CPU_CLASS(mcc);\n> +\n> + /* Validate that MISA_MXL is set properly. */\n> + switch (mcc->misa_mxl_max) {\n> +#ifdef TARGET_RISCV64\n> + case MXL_RV64:\n> + case MXL_RV128:\n> + cc->gdb_core_xml_file = \"riscv-64bit-cpu.xml\";\n> + break;\n> +#endif\n> + case MXL_RV32:\n> + cc->gdb_core_xml_file = \"riscv-32bit-cpu.xml\";\n> + break;\n> + default:\n> + g_assert_not_reached();\n> + }\n> +}\n> +\n> static int riscv_validate_misa_info_idx(uint32_t bit)\n> {\n> int idx;\n> @@ -1695,6 +1715,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)\n> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);\n>\n> mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;\n> + riscv_cpu_validate_misa_mxl(mcc);\n> }\n>\n> static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,\n> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\n> index 7f6712c81a4..eb243e011ca 100644\n> --- a/target/riscv/tcg/tcg-cpu.c\n> +++ b/target/riscv/tcg/tcg-cpu.c\n> @@ -148,27 +148,6 @@ static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)\n> }\n> }\n>\n> -static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu)\n> -{\n> - RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);\n> - CPUClass *cc = CPU_CLASS(mcc);\n> -\n> - /* Validate that MISA_MXL is set properly. */\n> - switch (mcc->misa_mxl_max) {\n> -#ifdef TARGET_RISCV64\n> - case MXL_RV64:\n> - case MXL_RV128:\n> - cc->gdb_core_xml_file = \"riscv-64bit-cpu.xml\";\n> - break;\n> -#endif\n> - case MXL_RV32:\n> - cc->gdb_core_xml_file = \"riscv-32bit-cpu.xml\";\n> - break;\n> - default:\n> - g_assert_not_reached();\n> - }\n> -}\n> -\n> static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)\n> {\n> CPURISCVState *env = &cpu->env;\n> @@ -676,8 +655,6 @@ static bool tcg_cpu_realize(CPUState *cs, Error **errp)\n> return false;\n> }\n>\n> - riscv_cpu_validate_misa_mxl(cpu);\n> -\n> #ifndef CONFIG_USER_ONLY\n> CPURISCVState *env = &cpu->env;\n> Error *local_err = NULL;\n> --\n> 2.39.2\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=gKIMRs13;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 11 Jan\n 2024 15:29:43 -0800 (PST)","MIME-Version":"1.0","References":"<20240103173349.398526-1-alex.bennee@linaro.org>\n <20240103173349.398526-26-alex.bennee@linaro.org>","In-Reply-To":"<20240103173349.398526-26-alex.bennee@linaro.org>","From":"Alistair Francis ","Date":"Fri, 12 Jan 2024 09:29:17 +1000","Message-ID":"\n ","Subject":"Re: [PATCH v2 25/43] target/riscv: Validate misa_mxl_max only once","To":"=?utf-8?q?Alex_Benn=C3=A9e?= ","Cc":"qemu-devel@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org,\n Richard Henderson ,\n Song Gao ,\n =?utf-8?q?Marc-Andr=C3=A9_Lureau?= ,\n David Hildenbrand , Aurelien Jarno ,\n Yoshinori Sato ,\n Yanan Wang , Bin Meng ,\n Laurent Vivier , Michael Rolnik ,\n Alexandre Iooss , David Woodhouse ,\n Laurent Vivier , Paolo Bonzini ,\n Brian Cain ,\n Daniel Henrique Barboza ,\n Beraldo Leal , Paul Durrant ,\n Mahmoud Mandour , Thomas Huth ,\n Liu Zhiwei , Cleber Rosa ,\n kvm@vger.kernel.org, Peter Maydell ,\n Wainer dos Santos Moschetta , qemu-arm@nongnu.org,\n Weiwei Li ,\n =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ,\n John Snow ,\n Daniel Henrique Barboza ,\n Nicholas Piggin , Palmer Dabbelt ,\n Marcel Apfelbaum ,\n Ilya Leoshkevich ,\n =?utf-8?q?C=C3=A9dric_Le_Goater?= ,\n \"Edgar E. Iglesias\" ,\n Eduardo Habkost ,\n Pierrick Bouvier , qemu-riscv@nongnu.org,\n Alistair Francis ,\n Akihiko Odaki ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2607:f8b0:4864:20::b34;\n envelope-from=alistair23@gmail.com; helo=mail-yb1-xb34.google.com","X-Spam_score_int":"-18","X-Spam_score":"-1.9","X-Spam_bar":"-","X-Spam_report":"(-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]