[{"id":3188632,"web_url":"http://patchwork.ozlabs.org/comment/3188632/","msgid":"","list_archive_url":null,"date":"2023-09-27T10:32:57","subject":"Re: [PATCH]AArch64 Add special patterns for creating DI scalar and\n vector constant 1 << 63 [PR109154]","submitter":{"id":64746,"url":"http://patchwork.ozlabs.org/api/people/64746/","name":"Richard Sandiford","email":"richard.sandiford@arm.com"},"content":"Tamar Christina writes:\n> Hi All,\n>\n> This adds a way to generate special sequences for creation of constants for\n> which we don't have single instructions sequences which would have normally\n> lead to a GP -> FP transfer or a literal load.\n>\n> The patch starts out by adding support for creating 1 << 63 using fneg (mov 0).\n>\n> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n>\n> Ok for master?\n>\n> Thanks,\n> Tamar\n>\n> gcc/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* config/aarch64/aarch64-protos.h (aarch64_simd_special_constant_p):\n> \tNew.\n> \t* config/aarch64/aarch64-simd.md (*aarch64_simd_mov): Add\n> \tnew coden for special constants.\n> \t* config/aarch64/aarch64.cc (aarch64_extract_vec_duplicate_wide_int):\n> \tTake optional mode.\n> \t(aarch64_simd_special_constant_p): New.\n> \t* config/aarch64/aarch64.md (*movdi_aarch64): Add new codegen for\n> \tspecial constants.\n> \t* config/aarch64/constraints.md (Dx): new.\n>\n> gcc/testsuite/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* gcc.target/aarch64/fneg-abs_1.c: Updated.\n> \t* gcc.target/aarch64/fneg-abs_2.c: Updated.\n> \t* gcc.target/aarch64/fneg-abs_4.c: Updated.\n>\n> --- inline copy of patch -- \n> diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h\n> index 70303d6fd953e0c397b9138ede8858c2db2e53db..2af9f6a774c20268bf90756c17064bbff8f8ff87 100644\n> --- a/gcc/config/aarch64/aarch64-protos.h\n> +++ b/gcc/config/aarch64/aarch64-protos.h\n> @@ -827,6 +827,7 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);\n> bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,\n> \t\t\tenum simd_immediate_check w = AARCH64_CHECK_MOV);\n> rtx aarch64_check_zero_based_sve_index_immediate (rtx);\n> +bool aarch64_simd_special_constant_p (rtx, rtx, machine_mode);\n> bool aarch64_sve_index_immediate_p (rtx);\n> bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool);\n> bool aarch64_sve_sqadd_sqsub_immediate_p (machine_mode, rtx, bool);\n> diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\n> index 7b4d5a37a9795fefda785aaacc246918826ed0a2..63c802d942a186b5a94c66d2e83828a82a88ffa8 100644\n> --- a/gcc/config/aarch64/aarch64-simd.md\n> +++ b/gcc/config/aarch64/aarch64-simd.md\n> @@ -181,17 +181,28 @@ (define_insn_and_split \"*aarch64_simd_mov\"\n> [?r , r ; multiple , * , 8] #\n> [w , Dn; neon_move , simd, 4] << aarch64_output_simd_mov_immediate (operands[1], 128);\n> [w , Dz; fmov , * , 4] fmov\\t%d0, xzr\n> + [w , Dx; neon_move , simd, 8] #\n> }\n> \"&& reload_completed\n> - && !(FP_REGNUM_P (REGNO (operands[0]))\n> -\t&& FP_REGNUM_P (REGNO (operands[1])))\"\n> + && (!(FP_REGNUM_P (REGNO (operands[0]))\n> +\t && FP_REGNUM_P (REGNO (operands[1])))\n> + || (aarch64_simd_special_constant_p (operands[1], NULL_RTX, mode)\n> +\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n\nUnless I'm missing something, the new test is already covered by the:\n\n !(FP_REGNUM_P (REGNO (operands[0]))\n && FP_REGNUM_P (REGNO (operands[1]))\n\n> [(const_int 0)]\n> {\n> if (GP_REGNUM_P (REGNO (operands[0]))\n> \t&& GP_REGNUM_P (REGNO (operands[1])))\n> aarch64_simd_emit_reg_reg_move (operands, DImode, 2);\n> else\n> - aarch64_split_simd_move (operands[0], operands[1]);\n> + {\n> +\tif (FP_REGNUM_P (REGNO (operands[0]))\n> +\t && mode == V2DImode\n> +\t && aarch64_simd_special_constant_p (operands[1], operands[0],\n> +\t\t\t\t\t\tmode))\n> +\t ;\n\nThis looked odd at first, since _p functions don't normally have\nside effects. So it looked like this case was expanding to nothing.\n\nHow about renaming aarch64_simd_special_constant_p to\naarch64_maybe_generate_simd_constant, and then making\naarch64_simd_special_constant_p a wrapper that passes the NULL_RTX?\nMinor nit, but most other functions put the destination first.\n\n> +\telse\n> +\t aarch64_split_simd_move (operands[0], operands[1]);\n> + }\n> DONE;\n> }\n> )\n> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\n> index 3739a44bfd909b69a76529cc6b0ae2f01d6fb36e..6e7ee446f1b31ee8bcf121c97c1c6fa87725bf42 100644\n> --- a/gcc/config/aarch64/aarch64.cc\n> +++ b/gcc/config/aarch64/aarch64.cc\n> @@ -11799,16 +11799,18 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)\n> /* Return true if X is a CONST_INT, CONST_WIDE_INT or a constant vector\n> duplicate of such constants. If so, store in RET_WI the wide_int\n> representation of the constant paired with the inner mode of the vector mode\n> - or TImode for scalar X constants. */\n> + or SMODE for scalar X constants. If SMODE is not provided then TImode is\n> + used. */\n\ns/SMODE/MODE/, based on the code.\n\n> \n> static bool\n> -aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi)\n> +aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi,\n> +\t\t\t\t\tscalar_mode mode = TImode)\n> {\n> rtx elt = unwrap_const_vec_duplicate (x);\n> if (!CONST_SCALAR_INT_P (elt))\n> return false;\n> scalar_mode smode\n> - = CONST_SCALAR_INT_P (x) ? TImode : GET_MODE_INNER (GET_MODE (x));\n> + = CONST_SCALAR_INT_P (x) ? mode : GET_MODE_INNER (GET_MODE (x));\n> *ret_wi = rtx_mode_t (elt, smode);\n> return true;\n> }\n> @@ -11857,6 +11859,43 @@ aarch64_const_vec_all_same_in_range_p (rtx x,\n> \t && IN_RANGE (INTVAL (elt), minval, maxval));\n> }\n> \n> +/* Some constants can't be made using normal mov instructions in Advanced SIMD\n> + but we can still create them in various ways. If the constant in VAL can be\n> + created using alternate methods then if TARGET then return true and set\n> + TARGET to the rtx for the sequence, otherwise return false if sequence is\n> + not possible. */\n\nThe return true bit applies regardless of TARGET.\n\n> +\n> +bool\n> +aarch64_simd_special_constant_p (rtx val, rtx target, machine_mode mode)\n> +{\n> + wide_int wval;\n> + machine_mode tmode = GET_MODE (val);\n> + auto smode = GET_MODE_INNER (tmode != VOIDmode ? tmode : mode);\n\nCan we not use \"mode\" unconditionally?\n\n> + if (!aarch64_extract_vec_duplicate_wide_int (val, &wval, smode))\n> + return false;\n> +\n> + /* For Advanced SIMD we can create an integer with only the top bit set\n> + using fneg (0.0f). */\n> + if (TARGET_SIMD\n> + && !TARGET_SVE\n> + && smode == DImode\n> + && wi::only_sign_bit_p (wval))\n> + {\n> + if (!target)\n> +\treturn true;\n> +\n> + /* Use the same base type as aarch64_gen_shareable_zero. */\n> + rtx zero = CONST0_RTX (V4SImode);\n> + emit_move_insn (target, lowpart_subreg (mode, zero, V4SImode));\n\nThe lowpart_subreg should simplify this back into CONST0_RTX (mode),\nmaking it no different from:\n\n emti_move_insn (target, CONST0_RTX (mode));\n\nIf the intention is to share zeros between modes (sounds good!),\nthen I think the subreg needs to be on the lhs instead.\n\n> + rtx neg = lowpart_subreg (V2DFmode, target, mode);\n> + emit_insn (gen_negv2df2 (neg, lowpart_subreg (V2DFmode, target, mode)));\n\nThe rhs seems simpler as copy_rtx (neg). (Even the copy_rtx shouldn't\nbe needed after RA, but it's probably more future-proof to keep it.)\n\n> + emit_move_insn (target, lowpart_subreg (mode, neg, V2DFmode));\n\nThis shouldn't be needed, since neg is already a reference to target.\n\nOverall, looks like a nice change/framework.\n\nThanks,\nRichard\n\n> + return true;\n> + }\n> +\n> + return false;\n> +}\n> +\n> bool\n> aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val)\n> {\n> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\n> index 634cfd33b41d0f945ca00d8efc9eff1ede490544..b51f979dba12b726bff0c1109b75c6d2c7ae41ab 100644\n> --- a/gcc/config/aarch64/aarch64.md\n> +++ b/gcc/config/aarch64/aarch64.md\n> @@ -1340,13 +1340,21 @@ (define_insn_and_split \"*movdi_aarch64\"\n> [r, w ; f_mrc , fp , 4] fmov\\t%x0, %d1\n> [w, w ; fmov , fp , 4] fmov\\t%d0, %d1\n> [w, Dd ; neon_move, simd, 4] << aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);\n> + [w, Dx ; neon_move, simd, 8] #\n> }\n> - \"CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode)\n> - && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))\"\n> + \"CONST_INT_P (operands[1])\n> + && REG_P (operands[0])\n> + && ((!aarch64_move_imm (INTVAL (operands[1]), DImode)\n> +\t&& GP_REGNUM_P (REGNO (operands[0])))\n> + || (aarch64_simd_special_constant_p (operands[1], NULL_RTX, DImode)\n> +\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n> [(const_int 0)]\n> {\n> + if (GP_REGNUM_P (REGNO (operands[0])))\n> aarch64_expand_mov_immediate (operands[0], operands[1]);\n> - DONE;\n> + else\n> + aarch64_simd_special_constant_p (operands[1], operands[0], DImode);\n> + DONE;\n> }\n> )\n> \n> diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md\n> index 371a00827d84d8ea4a06ba2b00a761d3b179ae90..11cf5a0d16b3364a7a4d0b2a2e5bb33063151479 100644\n> --- a/gcc/config/aarch64/constraints.md\n> +++ b/gcc/config/aarch64/constraints.md\n> @@ -488,6 +488,14 @@ (define_constraint \"Dr\"\n> (and (match_code \"const,const_vector\")\n> (match_test \"aarch64_simd_shift_imm_p (op, GET_MODE (op),\n> \t\t\t\t\t\t false)\")))\n> +\n> +(define_constraint \"Dx\"\n> + \"@internal\n> + A constraint that matches a vector of 64-bit immediates which we don't have a\n> + single instruction to create but that we can create in creative ways.\"\n> + (and (match_code \"const_int,const,const_vector\")\n> + (match_test \"aarch64_simd_special_constant_p (op, NULL_RTX, DImode)\")))\n> +\n> (define_constraint \"Dz\"\n> \"@internal\n> A constraint that matches a vector of immediate zero.\"\n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n> index f823013c3ddf6b3a266c3abfcbf2642fc2a75fa6..43c37e21b50e13c09b8d6850686e88465cd8482a 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n> @@ -28,8 +28,8 @@ float32x4_t t2 (float32x4_t a)\n> \n> /*\n> ** t3:\n> -**\tadrp\tx0, .LC[0-9]+\n> -**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n> +**\tmovi\tv[0-9]+.4s, 0\n> +**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n> **\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n> **\tret\n> */\n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> index 141121176b309e4b2aa413dc55271a6e3c93d5e1..fb14ec3e2210e0feeff80f2410d777d3046a9f78 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> @@ -20,8 +20,8 @@ float32_t f1 (float32_t a)\n> \n> /*\n> ** f2:\n> -**\tmov\tx0, -9223372036854775808\n> -**\tfmov\td[0-9]+, x0\n> +**\tfmov\td[0-9]+, xzr\n> +**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n> **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> **\tret\n> */\n> @@ -29,3 +29,4 @@ float64_t f2 (float64_t a)\n> {\n> return -fabs (a);\n> }\n> +\n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> index 10879dea74462d34b26160eeb0bd54ead063166b..4ea0105f6c0a9756070bcc60d34f142f53d8242c 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> @@ -8,8 +8,8 @@\n> \n> /*\n> ** negabs:\n> -**\tmov\tx0, -9223372036854775808\n> -**\tfmov\td[0-9]+, x0\n> +**\tfmov\td[0-9]+, xzr\n> +**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n> **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> **\tret\n> */","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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(Even the copy_rtx shouldn't be\n> needed after RA, but it's probably more future-proof to keep it.)\n> \n> > + emit_move_insn (target, lowpart_subreg (mode, neg, V2DFmode));\n> \n> This shouldn't be needed, since neg is already a reference to target.\n> \n> Overall, looks like a nice change/framework.\n\nUpdated the patch, and in te process also realized this can be used for the\nvector variants:\n\nHi All,\n\nThis adds a way to generate special sequences for creation of constants for\nwhich we don't have single instructions sequences which would have normally\nlead to a GP -> FP transfer or a literal load.\n\nThe patch starts out by adding support for creating 1 << 63 using fneg (mov 0).\n\nBootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n\nOk for master?\n\nThanks,\nTamar\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* config/aarch64/aarch64-protos.h (aarch64_simd_special_constant_p,\n\taarch64_maybe_generate_simd_constant): New.\n\t* config/aarch64/aarch64-simd.md (*aarch64_simd_mov,\n\t*aarch64_simd_mov): Add new coden for special constants.\n\t* config/aarch64/aarch64.cc (aarch64_extract_vec_duplicate_wide_int):\n\tTake optional mode.\n\t(aarch64_simd_special_constant_p,\n\taarch64_maybe_generate_simd_constant): New.\n\t* config/aarch64/aarch64.md (*movdi_aarch64): Add new codegen for\n\tspecial constants.\n\t* config/aarch64/constraints.md (Dx): new.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* gcc.target/aarch64/fneg-abs_1.c: Updated.\n\t* gcc.target/aarch64/fneg-abs_2.c: Updated.\n\t* gcc.target/aarch64/fneg-abs_4.c: Updated.\n\t* gcc.target/aarch64/dbl_mov_immediate_1.c: Updated.\n\n--- inline copy of patch ---\n\ndiff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h\nindex 60a55f4bc1956786ea687fc7cad7ec9e4a84e1f0..36d6c688bc888a51a9de174bd3665aebe891b8b1 100644\n--- a/gcc/config/aarch64/aarch64-protos.h\n+++ b/gcc/config/aarch64/aarch64-protos.h\n@@ -831,6 +831,8 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);\n bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,\n \t\t\tenum simd_immediate_check w = AARCH64_CHECK_MOV);\n rtx aarch64_check_zero_based_sve_index_immediate (rtx);\n+bool aarch64_maybe_generate_simd_constant (rtx, rtx, machine_mode);\n+bool aarch64_simd_special_constant_p (rtx, machine_mode);\n bool aarch64_sve_index_immediate_p (rtx);\n bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool);\n bool aarch64_sve_sqadd_sqsub_immediate_p (machine_mode, rtx, bool);\ndiff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 81ff5bad03d598fa0d48df93d172a28bc0d1d92e..33eceb436584ff73c7271f93639f2246d1af19e0 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -142,26 +142,35 @@ (define_insn \"aarch64_dup_lane_\"\n [(set_attr \"type\" \"neon_dup\")]\n )\n \n-(define_insn \"*aarch64_simd_mov\"\n+(define_insn_and_split \"*aarch64_simd_mov\"\n [(set (match_operand:VDMOV 0 \"nonimmediate_operand\")\n \t(match_operand:VDMOV 1 \"general_operand\"))]\n \"TARGET_FLOAT\n && (register_operand (operands[0], mode)\n || aarch64_simd_reg_or_zero (operands[1], mode))\"\n- {@ [cons: =0, 1; attrs: type, arch]\n- [w , m ; neon_load1_1reg , * ] ldr\\t%d0, %1\n- [r , m ; load_8 , * ] ldr\\t%x0, %1\n- [m , Dz; store_8 , * ] str\\txzr, %0\n- [m , w ; neon_store1_1reg, * ] str\\t%d1, %0\n- [m , r ; store_8 , * ] str\\t%x1, %0\n- [w , w ; neon_logic , simd] mov\\t%0., %1.\n- [w , w ; neon_logic , * ] fmov\\t%d0, %d1\n- [?r, w ; neon_to_gp , simd] umov\\t%0, %1.d[0]\n- [?r, w ; neon_to_gp , * ] fmov\\t%x0, %d1\n- [?w, r ; f_mcr , * ] fmov\\t%d0, %1\n- [?r, r ; mov_reg , * ] mov\\t%0, %1\n- [w , Dn; neon_move , simd] << aarch64_output_simd_mov_immediate (operands[1], 64);\n- [w , Dz; f_mcr , * ] fmov\\t%d0, xzr\n+ {@ [cons: =0, 1; attrs: type, arch, length]\n+ [w , m ; neon_load1_1reg , * , *] ldr\\t%d0, %1\n+ [r , m ; load_8 , * , *] ldr\\t%x0, %1\n+ [m , Dz; store_8 , * , *] str\\txzr, %0\n+ [m , w ; neon_store1_1reg, * , *] str\\t%d1, %0\n+ [m , r ; store_8 , * , *] str\\t%x1, %0\n+ [w , w ; neon_logic , simd, *] mov\\t%0., %1.\n+ [w , w ; neon_logic , * , *] fmov\\t%d0, %d1\n+ [?r, w ; neon_to_gp , simd, *] umov\\t%0, %1.d[0]\n+ [?r, w ; neon_to_gp , * , *] fmov\\t%x0, %d1\n+ [?w, r ; f_mcr , * , *] fmov\\t%d0, %1\n+ [?r, r ; mov_reg , * , *] mov\\t%0, %1\n+ [w , Dn; neon_move , simd, *] << aarch64_output_simd_mov_immediate (operands[1], 64);\n+ [w , Dz; f_mcr , * , *] fmov\\t%d0, xzr\n+ [w , Dx; neon_move , simd, 8] #\n+ }\n+ \"CONST_INT_P (operands[1])\n+ && aarch64_simd_special_constant_p (operands[1], mode)\n+ && FP_REGNUM_P (REGNO (operands[0]))\"\n+ [(const_int 0)]\n+ {\n+ aarch64_maybe_generate_simd_constant (operands[0], operands[1], mode);\n+ DONE;\n }\n )\n \n@@ -181,19 +190,30 @@ (define_insn_and_split \"*aarch64_simd_mov\"\n [?r , r ; multiple , * , 8] #\n [w , Dn; neon_move , simd, 4] << aarch64_output_simd_mov_immediate (operands[1], 128);\n [w , Dz; fmov , * , 4] fmov\\t%d0, xzr\n+ [w , Dx; neon_move , simd, 8] #\n }\n \"&& reload_completed\n- && (REG_P (operands[0])\n+ && ((REG_P (operands[0])\n \t&& REG_P (operands[1])\n \t&& !(FP_REGNUM_P (REGNO (operands[0]))\n-\t && FP_REGNUM_P (REGNO (operands[1]))))\"\n+\t && FP_REGNUM_P (REGNO (operands[1]))))\n+ || (aarch64_simd_special_constant_p (operands[1], mode)\n+\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n [(const_int 0)]\n {\n if (GP_REGNUM_P (REGNO (operands[0]))\n \t&& GP_REGNUM_P (REGNO (operands[1])))\n aarch64_simd_emit_reg_reg_move (operands, DImode, 2);\n else\n- aarch64_split_simd_move (operands[0], operands[1]);\n+ {\n+\tif (FP_REGNUM_P (REGNO (operands[0]))\n+\t && mode == V2DImode\n+\t && aarch64_maybe_generate_simd_constant (operands[0], operands[1],\n+\t\t\t\t\t\t mode))\n+\t ;\n+\telse\n+\t aarch64_split_simd_move (operands[0], operands[1]);\n+ }\n DONE;\n }\n )\ndiff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 9fbfc548a891f5d11940c6fd3c49a14bfbdec886..c5cf42f7801b291754840dcc5b304577e8e0d391 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -11873,16 +11873,18 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)\n /* Return true if X is a CONST_INT, CONST_WIDE_INT or a constant vector\n duplicate of such constants. If so, store in RET_WI the wide_int\n representation of the constant paired with the inner mode of the vector mode\n- or TImode for scalar X constants. */\n+ or MODE for scalar X constants. If MODE is not provided then TImode is\n+ used. */\n \n static bool\n-aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi)\n+aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi,\n+\t\t\t\t\tscalar_mode mode = TImode)\n {\n rtx elt = unwrap_const_vec_duplicate (x);\n if (!CONST_SCALAR_INT_P (elt))\n return false;\n scalar_mode smode\n- = CONST_SCALAR_INT_P (x) ? TImode : GET_MODE_INNER (GET_MODE (x));\n+ = CONST_SCALAR_INT_P (x) ? mode : GET_MODE_INNER (GET_MODE (x));\n *ret_wi = rtx_mode_t (elt, smode);\n return true;\n }\n@@ -11931,6 +11933,49 @@ aarch64_const_vec_all_same_in_range_p (rtx x,\n \t && IN_RANGE (INTVAL (elt), minval, maxval));\n }\n \n+/* Some constants can't be made using normal mov instructions in Advanced SIMD\n+ but we can still create them in various ways. If the constant in VAL can be\n+ created using alternate methods then if possible then return true and\n+ additionally set TARGET to the rtx for the sequence if TARGET is not NULL.\n+ Otherwise return false if sequence is not possible. */\n+\n+bool\n+aarch64_maybe_generate_simd_constant (rtx target, rtx val, machine_mode mode)\n+{\n+ wide_int wval;\n+ auto smode = GET_MODE_INNER (mode);\n+ if (!aarch64_extract_vec_duplicate_wide_int (val, &wval, smode))\n+ return false;\n+\n+ /* For Advanced SIMD we can create an integer with only the top bit set\n+ using fneg (0.0f). */\n+ if (TARGET_SIMD\n+ && !TARGET_SVE\n+ && smode == DImode\n+ && wi::only_sign_bit_p (wval))\n+ {\n+ if (!target)\n+\treturn true;\n+\n+ /* Use the same base type as aarch64_gen_shareable_zero. */\n+ rtx zero = CONST0_RTX (V4SImode);\n+ emit_move_insn (lowpart_subreg (V4SImode, target, mode), zero);\n+ rtx neg = lowpart_subreg (V2DFmode, target, mode);\n+ emit_insn (gen_negv2df2 (neg, copy_rtx (neg)));\n+ return true;\n+ }\n+\n+ return false;\n+}\n+\n+/* Check if the value in VAL with mode MODE can be created using special\n+ instruction sequences. */\n+\n+bool aarch64_simd_special_constant_p (rtx val, machine_mode mode)\n+{\n+ return aarch64_maybe_generate_simd_constant (NULL_RTX, val, mode);\n+}\n+\n bool\n aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val)\n {\ndiff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 32c7adc89281b249b52ecedf2f1678749c289d18..6f7a6cd1830e5b7cdb3eab76f3143964278a8561 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -1341,13 +1341,21 @@ (define_insn_and_split \"*movdi_aarch64\"\n [r, w ; f_mrc , fp , 4] fmov\\t%x0, %d1\n [w, w ; fmov , fp , 4] fmov\\t%d0, %d1\n [w, Dd ; neon_move, simd, 4] << aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);\n- }\n- \"CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode)\n- && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))\"\n+ [w, Dx ; neon_move, simd, 8] #\n+ }\n+ \"CONST_INT_P (operands[1])\n+ && REG_P (operands[0])\n+ && ((!aarch64_move_imm (INTVAL (operands[1]), DImode)\n+\t&& GP_REGNUM_P (REGNO (operands[0])))\n+ || (aarch64_simd_special_constant_p (operands[1], DImode)\n+\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n [(const_int 0)]\n {\n+ if (GP_REGNUM_P (REGNO (operands[0])))\n aarch64_expand_mov_immediate (operands[0], operands[1]);\n- DONE;\n+ else\n+ aarch64_maybe_generate_simd_constant (operands[0], operands[1], DImode);\n+ DONE;\n }\n )\n \ndiff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md\nindex 371a00827d84d8ea4a06ba2b00a761d3b179ae90..b3922bcb9a8b362c995c96c6d1c6eef034990251 100644\n--- a/gcc/config/aarch64/constraints.md\n+++ b/gcc/config/aarch64/constraints.md\n@@ -488,6 +488,14 @@ (define_constraint \"Dr\"\n (and (match_code \"const,const_vector\")\n (match_test \"aarch64_simd_shift_imm_p (op, GET_MODE (op),\n \t\t\t\t\t\t false)\")))\n+\n+(define_constraint \"Dx\"\n+ \"@internal\n+ A constraint that matches a vector of 64-bit immediates which we don't have a\n+ single instruction to create but that we can create in creative ways.\"\n+ (and (match_code \"const_int,const,const_vector\")\n+ (match_test \"aarch64_simd_special_constant_p (op, DImode)\")))\n+\n (define_constraint \"Dz\"\n \"@internal\n A constraint that matches a vector of immediate zero.\"\ndiff --git a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c\nindex ba6a230457ba7a86f1939665fe9177ecdb45f935..fb9088e9d2849c0ea10a8741795181a0543c3cb2 100644\n--- a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c\n@@ -48,6 +48,8 @@ double d4(void)\n \n /* { dg-final { scan-assembler-times \"mov\\tx\\[0-9\\]+, 25838523252736\" 1 } } */\n /* { dg-final { scan-assembler-times \"movk\\tx\\[0-9\\]+, 0x40fe, lsl 48\" 1 } } */\n-/* { dg-final { scan-assembler-times \"mov\\tx\\[0-9\\]+, -9223372036854775808\" 1 } } */\n-/* { dg-final { scan-assembler-times \"fmov\\td\\[0-9\\]+, x\\[0-9\\]+\" 2 } } */\n+/* { dg-final { scan-assembler-times \"mov\\tx\\[0-9\\]+, -9223372036854775808\" 0 } } */\n+/* { dg-final { scan-assembler-times {movi\\tv[0-9]+.2d, #0} 1 } } */\n+/* { dg-final { scan-assembler-times {fneg\\tv[0-9]+.2d, v[0-9]+.2d} 1 } } */\n+/* { dg-final { scan-assembler-times \"fmov\\td\\[0-9\\]+, x\\[0-9\\]+\" 1 } } */\n \ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\nindex f823013c3ddf6b3a266c3abfcbf2642fc2a75fa6..43c37e21b50e13c09b8d6850686e88465cd8482a 100644\n--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n@@ -28,8 +28,8 @@ float32x4_t t2 (float32x4_t a)\n \n /*\n ** t3:\n-**\tadrp\tx0, .LC[0-9]+\n-**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n+**\tmovi\tv[0-9]+.4s, 0\n+**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n **\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n **\tret\n */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\nindex 141121176b309e4b2aa413dc55271a6e3c93d5e1..fb14ec3e2210e0feeff80f2410d777d3046a9f78 100644\n--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n@@ -20,8 +20,8 @@ float32_t f1 (float32_t a)\n \n /*\n ** f2:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n+**\tfmov\td[0-9]+, xzr\n+**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n **\tret\n */\n@@ -29,3 +29,4 @@ float64_t f2 (float64_t a)\n {\n return -fabs (a);\n }\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\nindex 10879dea74462d34b26160eeb0bd54ead063166b..4ea0105f6c0a9756070bcc60d34f142f53d8242c 100644\n--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n@@ -8,8 +8,8 @@\n \n /*\n ** negabs:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n+**\tfmov\td[0-9]+, xzr\n+**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n **\tret\n */","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com\n header.b=uh7+OxoF;\n\tdkim=pass (1024-bit key) header.d=armh.onmicrosoft.com\n header.i=@armh.onmicrosoft.com header.a=rsa-sha256\n header.s=selector2-armh-onmicrosoft-com header.b=uh7+OxoF;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=8.43.85.97; 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","Errors-To":"gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3193963,"web_url":"http://patchwork.ozlabs.org/comment/3193963/","msgid":"","list_archive_url":null,"date":"2023-10-05T19:47:01","subject":"Re: [PATCH]AArch64 Add special patterns for creating DI scalar and\n vector constant 1 << 63 [PR109154]","submitter":{"id":64746,"url":"http://patchwork.ozlabs.org/api/people/64746/","name":"Richard Sandiford","email":"richard.sandiford@arm.com"},"content":"Tamar Christina writes:\n> Hi,\n>\n>> The lowpart_subreg should simplify this back into CONST0_RTX (mode),\n>> making it no different from:\n>> \n>> emti_move_insn (target, CONST0_RTX (mode));\n>> \n>> If the intention is to share zeros between modes (sounds good!), then I think\n>> the subreg needs to be on the lhs instead.\n>> \n>> > + rtx neg = lowpart_subreg (V2DFmode, target, mode);\n>> > + emit_insn (gen_negv2df2 (neg, lowpart_subreg (V2DFmode, target,\n>> > + mode)));\n>> \n>> The rhs seems simpler as copy_rtx (neg). (Even the copy_rtx shouldn't be\n>> needed after RA, but it's probably more future-proof to keep it.)\n>> \n>> > + emit_move_insn (target, lowpart_subreg (mode, neg, V2DFmode));\n>> \n>> This shouldn't be needed, since neg is already a reference to target.\n>> \n>> Overall, looks like a nice change/framework.\n>\n> Updated the patch, and in te process also realized this can be used for the\n> vector variants:\n>\n> Hi All,\n>\n> This adds a way to generate special sequences for creation of constants for\n> which we don't have single instructions sequences which would have normally\n> lead to a GP -> FP transfer or a literal load.\n>\n> The patch starts out by adding support for creating 1 << 63 using fneg (mov 0).\n>\n> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n>\n> Ok for master?\n>\n> Thanks,\n> Tamar\n>\n> gcc/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* config/aarch64/aarch64-protos.h (aarch64_simd_special_constant_p,\n> \taarch64_maybe_generate_simd_constant): New.\n> \t* config/aarch64/aarch64-simd.md (*aarch64_simd_mov,\n> \t*aarch64_simd_mov): Add new coden for special constants.\n> \t* config/aarch64/aarch64.cc (aarch64_extract_vec_duplicate_wide_int):\n> \tTake optional mode.\n> \t(aarch64_simd_special_constant_p,\n> \taarch64_maybe_generate_simd_constant): New.\n> \t* config/aarch64/aarch64.md (*movdi_aarch64): Add new codegen for\n> \tspecial constants.\n> \t* config/aarch64/constraints.md (Dx): new.\n>\n> gcc/testsuite/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* gcc.target/aarch64/fneg-abs_1.c: Updated.\n> \t* gcc.target/aarch64/fneg-abs_2.c: Updated.\n> \t* gcc.target/aarch64/fneg-abs_4.c: Updated.\n> \t* gcc.target/aarch64/dbl_mov_immediate_1.c: Updated.\n>\n> --- inline copy of patch ---\n>\n> diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h\n> index 60a55f4bc1956786ea687fc7cad7ec9e4a84e1f0..36d6c688bc888a51a9de174bd3665aebe891b8b1 100644\n> --- a/gcc/config/aarch64/aarch64-protos.h\n> +++ b/gcc/config/aarch64/aarch64-protos.h\n> @@ -831,6 +831,8 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);\n> bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,\n> \t\t\tenum simd_immediate_check w = AARCH64_CHECK_MOV);\n> rtx aarch64_check_zero_based_sve_index_immediate (rtx);\n> +bool aarch64_maybe_generate_simd_constant (rtx, rtx, machine_mode);\n> +bool aarch64_simd_special_constant_p (rtx, machine_mode);\n> bool aarch64_sve_index_immediate_p (rtx);\n> bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool);\n> bool aarch64_sve_sqadd_sqsub_immediate_p (machine_mode, rtx, bool);\n> diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\n> index 81ff5bad03d598fa0d48df93d172a28bc0d1d92e..33eceb436584ff73c7271f93639f2246d1af19e0 100644\n> --- a/gcc/config/aarch64/aarch64-simd.md\n> +++ b/gcc/config/aarch64/aarch64-simd.md\n> @@ -142,26 +142,35 @@ (define_insn \"aarch64_dup_lane_\"\n> [(set_attr \"type\" \"neon_dup\")]\n> )\n> \n> -(define_insn \"*aarch64_simd_mov\"\n> +(define_insn_and_split \"*aarch64_simd_mov\"\n> [(set (match_operand:VDMOV 0 \"nonimmediate_operand\")\n> \t(match_operand:VDMOV 1 \"general_operand\"))]\n> \"TARGET_FLOAT\n> && (register_operand (operands[0], mode)\n> || aarch64_simd_reg_or_zero (operands[1], mode))\"\n> - {@ [cons: =0, 1; attrs: type, arch]\n> - [w , m ; neon_load1_1reg , * ] ldr\\t%d0, %1\n> - [r , m ; load_8 , * ] ldr\\t%x0, %1\n> - [m , Dz; store_8 , * ] str\\txzr, %0\n> - [m , w ; neon_store1_1reg, * ] str\\t%d1, %0\n> - [m , r ; store_8 , * ] str\\t%x1, %0\n> - [w , w ; neon_logic , simd] mov\\t%0., %1.\n> - [w , w ; neon_logic , * ] fmov\\t%d0, %d1\n> - [?r, w ; neon_to_gp , simd] umov\\t%0, %1.d[0]\n> - [?r, w ; neon_to_gp , * ] fmov\\t%x0, %d1\n> - [?w, r ; f_mcr , * ] fmov\\t%d0, %1\n> - [?r, r ; mov_reg , * ] mov\\t%0, %1\n> - [w , Dn; neon_move , simd] << aarch64_output_simd_mov_immediate (operands[1], 64);\n> - [w , Dz; f_mcr , * ] fmov\\t%d0, xzr\n> + {@ [cons: =0, 1; attrs: type, arch, length]\n> + [w , m ; neon_load1_1reg , * , *] ldr\\t%d0, %1\n> + [r , m ; load_8 , * , *] ldr\\t%x0, %1\n> + [m , Dz; store_8 , * , *] str\\txzr, %0\n> + [m , w ; neon_store1_1reg, * , *] str\\t%d1, %0\n> + [m , r ; store_8 , * , *] str\\t%x1, %0\n> + [w , w ; neon_logic , simd, *] mov\\t%0., %1.\n> + [w , w ; neon_logic , * , *] fmov\\t%d0, %d1\n> + [?r, w ; neon_to_gp , simd, *] umov\\t%0, %1.d[0]\n> + [?r, w ; neon_to_gp , * , *] fmov\\t%x0, %d1\n> + [?w, r ; f_mcr , * , *] fmov\\t%d0, %1\n> + [?r, r ; mov_reg , * , *] mov\\t%0, %1\n> + [w , Dn; neon_move , simd, *] << aarch64_output_simd_mov_immediate (operands[1], 64);\n> + [w , Dz; f_mcr , * , *] fmov\\t%d0, xzr\n> + [w , Dx; neon_move , simd, 8] #\n> + }\n> + \"CONST_INT_P (operands[1])\n> + && aarch64_simd_special_constant_p (operands[1], mode)\n> + && FP_REGNUM_P (REGNO (operands[0]))\"\n> + [(const_int 0)]\n> + {\n> + aarch64_maybe_generate_simd_constant (operands[0], operands[1], mode);\n> + DONE;\n> }\n> )\n> \n> @@ -181,19 +190,30 @@ (define_insn_and_split \"*aarch64_simd_mov\"\n> [?r , r ; multiple , * , 8] #\n> [w , Dn; neon_move , simd, 4] << aarch64_output_simd_mov_immediate (operands[1], 128);\n> [w , Dz; fmov , * , 4] fmov\\t%d0, xzr\n> + [w , Dx; neon_move , simd, 8] #\n> }\n> \"&& reload_completed\n> - && (REG_P (operands[0])\n> + && ((REG_P (operands[0])\n> \t&& REG_P (operands[1])\n> \t&& !(FP_REGNUM_P (REGNO (operands[0]))\n> -\t && FP_REGNUM_P (REGNO (operands[1]))))\"\n> +\t && FP_REGNUM_P (REGNO (operands[1]))))\n> + || (aarch64_simd_special_constant_p (operands[1], mode)\n> +\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n> [(const_int 0)]\n> {\n> if (GP_REGNUM_P (REGNO (operands[0]))\n> \t&& GP_REGNUM_P (REGNO (operands[1])))\n> aarch64_simd_emit_reg_reg_move (operands, DImode, 2);\n> else\n> - aarch64_split_simd_move (operands[0], operands[1]);\n> + {\n> +\tif (FP_REGNUM_P (REGNO (operands[0]))\n> +\t && mode == V2DImode\n> +\t && aarch64_maybe_generate_simd_constant (operands[0], operands[1],\n> +\t\t\t\t\t\t mode))\n> +\t ;\n> +\telse\n> +\t aarch64_split_simd_move (operands[0], operands[1]);\n> + }\n> DONE;\n> }\n> )\n> diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\n> index 9fbfc548a891f5d11940c6fd3c49a14bfbdec886..c5cf42f7801b291754840dcc5b304577e8e0d391 100644\n> --- a/gcc/config/aarch64/aarch64.cc\n> +++ b/gcc/config/aarch64/aarch64.cc\n> @@ -11873,16 +11873,18 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)\n> /* Return true if X is a CONST_INT, CONST_WIDE_INT or a constant vector\n> duplicate of such constants. If so, store in RET_WI the wide_int\n> representation of the constant paired with the inner mode of the vector mode\n> - or TImode for scalar X constants. */\n> + or MODE for scalar X constants. If MODE is not provided then TImode is\n> + used. */\n> \n> static bool\n> -aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi)\n> +aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi,\n> +\t\t\t\t\tscalar_mode mode = TImode)\n> {\n> rtx elt = unwrap_const_vec_duplicate (x);\n> if (!CONST_SCALAR_INT_P (elt))\n> return false;\n> scalar_mode smode\n> - = CONST_SCALAR_INT_P (x) ? TImode : GET_MODE_INNER (GET_MODE (x));\n> + = CONST_SCALAR_INT_P (x) ? mode : GET_MODE_INNER (GET_MODE (x));\n> *ret_wi = rtx_mode_t (elt, smode);\n> return true;\n> }\n> @@ -11931,6 +11933,49 @@ aarch64_const_vec_all_same_in_range_p (rtx x,\n> \t && IN_RANGE (INTVAL (elt), minval, maxval));\n> }\n> \n> +/* Some constants can't be made using normal mov instructions in Advanced SIMD\n> + but we can still create them in various ways. If the constant in VAL can be\n> + created using alternate methods then if possible then return true and\n> + additionally set TARGET to the rtx for the sequence if TARGET is not NULL.\n> + Otherwise return false if sequence is not possible. */\n> +\n> +bool\n> +aarch64_maybe_generate_simd_constant (rtx target, rtx val, machine_mode mode)\n> +{\n> + wide_int wval;\n> + auto smode = GET_MODE_INNER (mode);\n> + if (!aarch64_extract_vec_duplicate_wide_int (val, &wval, smode))\n> + return false;\n> +\n> + /* For Advanced SIMD we can create an integer with only the top bit set\n> + using fneg (0.0f). */\n> + if (TARGET_SIMD\n> + && !TARGET_SVE\n> + && smode == DImode\n> + && wi::only_sign_bit_p (wval))\n> + {\n> + if (!target)\n> +\treturn true;\n> +\n> + /* Use the same base type as aarch64_gen_shareable_zero. */\n> + rtx zero = CONST0_RTX (V4SImode);\n> + emit_move_insn (lowpart_subreg (V4SImode, target, mode), zero);\n> + rtx neg = lowpart_subreg (V2DFmode, target, mode);\n> + emit_insn (gen_negv2df2 (neg, copy_rtx (neg)));\n> + return true;\n> + }\n> +\n> + return false;\n> +}\n> +\n> +/* Check if the value in VAL with mode MODE can be created using special\n> + instruction sequences. */\n> +\n> +bool aarch64_simd_special_constant_p (rtx val, machine_mode mode)\n\nNit: should be line break after \"bool\".\n\n> +{\n> + return aarch64_maybe_generate_simd_constant (NULL_RTX, val, mode);\n> +}\n> +\n> bool\n> aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val)\n> {\n> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\n> index 32c7adc89281b249b52ecedf2f1678749c289d18..6f7a6cd1830e5b7cdb3eab76f3143964278a8561 100644\n> --- a/gcc/config/aarch64/aarch64.md\n> +++ b/gcc/config/aarch64/aarch64.md\n> @@ -1341,13 +1341,21 @@ (define_insn_and_split \"*movdi_aarch64\"\n> [r, w ; f_mrc , fp , 4] fmov\\t%x0, %d1\n> [w, w ; fmov , fp , 4] fmov\\t%d0, %d1\n> [w, Dd ; neon_move, simd, 4] << aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);\n> - }\n> - \"CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode)\n> - && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))\"\n> + [w, Dx ; neon_move, simd, 8] #\n> + }\n> + \"CONST_INT_P (operands[1])\n> + && REG_P (operands[0])\n> + && ((!aarch64_move_imm (INTVAL (operands[1]), DImode)\n> +\t&& GP_REGNUM_P (REGNO (operands[0])))\n> + || (aarch64_simd_special_constant_p (operands[1], DImode)\n> +\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n> [(const_int 0)]\n> {\n> + if (GP_REGNUM_P (REGNO (operands[0])))\n> aarch64_expand_mov_immediate (operands[0], operands[1]);\n> - DONE;\n> + else\n> + aarch64_maybe_generate_simd_constant (operands[0], operands[1], DImode);\n> + DONE;\n> }\n> )\n> \n> diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md\n> index 371a00827d84d8ea4a06ba2b00a761d3b179ae90..b3922bcb9a8b362c995c96c6d1c6eef034990251 100644\n> --- a/gcc/config/aarch64/constraints.md\n> +++ b/gcc/config/aarch64/constraints.md\n> @@ -488,6 +488,14 @@ (define_constraint \"Dr\"\n> (and (match_code \"const,const_vector\")\n> (match_test \"aarch64_simd_shift_imm_p (op, GET_MODE (op),\n> \t\t\t\t\t\t false)\")))\n> +\n> +(define_constraint \"Dx\"\n> + \"@internal\n> + A constraint that matches a vector of 64-bit immediates which we don't have a\n> + single instruction to create but that we can create in creative ways.\"\n> + (and (match_code \"const_int,const,const_vector\")\n> + (match_test \"aarch64_simd_special_constant_p (op, DImode)\")))\n\nSince this is used by vector iterators that span multiple modes,\nI suppose we should test the mode too:\n\n (and (match_code \"const_int,const,const_vector\")\n (match_test \"GET_MODE_INNER (GET_MODE (op)) == DImode\n\t\t || GET_MODE (op) == VOIDmode\")\n (match_test \"aarch64_simd_special_constant_p (op, DImode)\")))\n\nAlternatively, and I think this is probably better than adding the\ntest above, we could have a separate constraint for vectors and\nkeep Dx for DImode scalars:\n\n(define_constraint \"Dx\"\n \"@internal\n A constraint that matches a scalar 64-bit immediate which we don't have a\n single instruction to create but that we can create in creative ways.\"\n (and (match_code \"const_int\")\n (match_test \"aarch64_simd_special_constant_p (op, DImode)\")))\n\n(define_constraint \"Dy\"\n \"@internal\n Like Dx, but for a vector of immediates (of any mode).\"\n (and (match_code \"const_vector\")\n (match_test \"aarch64_simd_special_constant_p\n (op, GET_MODE_INNER (GET_MODE (op)))\")))\n\n(No need for the \"const\", that's legacy from before the VLA const_vector\nencoding.)\n\nI think we would need a split like that if we ever wanted to extend\nthis to SImode scalars.\n\nOK with those changes, thanks.\n\nRichard\n\n> +\n> (define_constraint \"Dz\"\n> \"@internal\n> A constraint that matches a vector of immediate zero.\"\n> diff --git a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c\n> index ba6a230457ba7a86f1939665fe9177ecdb45f935..fb9088e9d2849c0ea10a8741795181a0543c3cb2 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/dbl_mov_immediate_1.c\n> @@ -48,6 +48,8 @@ double d4(void)\n> \n> /* { dg-final { scan-assembler-times \"mov\\tx\\[0-9\\]+, 25838523252736\" 1 } } */\n> /* { dg-final { scan-assembler-times \"movk\\tx\\[0-9\\]+, 0x40fe, lsl 48\" 1 } } */\n> -/* { dg-final { scan-assembler-times \"mov\\tx\\[0-9\\]+, -9223372036854775808\" 1 } } */\n> -/* { dg-final { scan-assembler-times \"fmov\\td\\[0-9\\]+, x\\[0-9\\]+\" 2 } } */\n> +/* { dg-final { scan-assembler-times \"mov\\tx\\[0-9\\]+, -9223372036854775808\" 0 } } */\n> +/* { dg-final { scan-assembler-times {movi\\tv[0-9]+.2d, #0} 1 } } */\n> +/* { dg-final { scan-assembler-times {fneg\\tv[0-9]+.2d, v[0-9]+.2d} 1 } } */\n> +/* { dg-final { scan-assembler-times \"fmov\\td\\[0-9\\]+, x\\[0-9\\]+\" 1 } } */\n> \n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n> index f823013c3ddf6b3a266c3abfcbf2642fc2a75fa6..43c37e21b50e13c09b8d6850686e88465cd8482a 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n> @@ -28,8 +28,8 @@ float32x4_t t2 (float32x4_t a)\n> \n> /*\n> ** t3:\n> -**\tadrp\tx0, .LC[0-9]+\n> -**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n> +**\tmovi\tv[0-9]+.4s, 0\n> +**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n> **\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n> **\tret\n> */\n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> index 141121176b309e4b2aa413dc55271a6e3c93d5e1..fb14ec3e2210e0feeff80f2410d777d3046a9f78 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> @@ -20,8 +20,8 @@ float32_t f1 (float32_t a)\n> \n> /*\n> ** f2:\n> -**\tmov\tx0, -9223372036854775808\n> -**\tfmov\td[0-9]+, x0\n> +**\tfmov\td[0-9]+, xzr\n> +**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n> **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> **\tret\n> */\n> @@ -29,3 +29,4 @@ float64_t f2 (float64_t a)\n> {\n> return -fabs (a);\n> }\n> +\n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> index 10879dea74462d34b26160eeb0bd54ead063166b..4ea0105f6c0a9756070bcc60d34f142f53d8242c 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> @@ -8,8 +8,8 @@\n> \n> /*\n> ** negabs:\n> -**\tmov\tx0, -9223372036854775808\n> -**\tfmov\td[0-9]+, x0\n> +**\tfmov\td[0-9]+, xzr\n> +**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n> **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> **\tret\n> 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","Subject":"Re: [PATCH]AArch64 Add special patterns for creating DI scalar and\n vector constant 1 << 63 [PR109154]","References":" \n ","Date":"Thu, 05 Oct 2023 20:47:01 +0100","In-Reply-To":"\n \n (Tamar Christina's message of \"Thu, 5 Oct 2023 18:18:15 +0000\")","Message-ID":"","User-Agent":"Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux)","MIME-Version":"1.0","Content-Type":"text/plain","X-Spam-Status":"No, score=-24.8 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LOTSOFHASH, KAM_SHORT, SPF_HELO_NONE,\n TXREP, T_SPF_TEMPERROR,\n URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n 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