[{"id":3188526,"web_url":"http://patchwork.ozlabs.org/comment/3188526/","msgid":"","list_archive_url":null,"date":"2023-09-27T08:50:07","subject":"Re: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when\n Advanced SIMD inefficient [PR109154]","submitter":{"id":64746,"url":"http://patchwork.ozlabs.org/api/people/64746/","name":"Richard Sandiford","email":"richard.sandiford@arm.com"},"content":"Tamar Christina writes:\n> Hi All,\n>\n> SVE has much bigger immediate encoding range for bitmasks than Advanced SIMD has\n> and so on a system that is SVE capable if we need an Advanced SIMD Inclusive-OR\n> by immediate and would require a reload then an unpredicated SVE ORR instead.\n>\n> This has both speed and size improvements.\n>\n> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n>\n> Ok for master?\n>\n> Thanks,\n> Tamar\n>\n> gcc/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* config/aarch64/aarch64.md (3): Convert to new syntax and\n> \tSVE split case.\n> \t* config/aarch64/iterators.md (VCONV, vconv): New.\n>\n> gcc/testsuite/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* gcc.target/aarch64/sve/fneg-abs_2.c: Updated.\n> \t* gcc.target/aarch64/sve/fneg-abs_4.c: Updated.\n>\n> --- inline copy of patch -- \n> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\n> index 60c92213c75a2a4c18a6b59ae52fe45d1e872718..377c5cafedd43d8d1320489a36267cc6e5f15239 100644\n> --- a/gcc/config/aarch64/aarch64.md\n> +++ b/gcc/config/aarch64/aarch64.md\n> @@ -4551,17 +4551,27 @@ (define_insn_and_split \"*aarch64_and_imm2\"\n> }\n> )\n> \n> -(define_insn \"3\"\n> - [(set (match_operand:GPI 0 \"register_operand\" \"=r,rk,w\")\n> -\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\" \"%r,r,w\")\n> -\t\t (match_operand:GPI 2 \"aarch64_logical_operand\" \"r,,w\")))]\n> - \"\"\n> - \"@\n> - \\\\t%0, %1, %2\n> - \\\\t%0, %1, %2\n> - \\\\t%0., %1., %2.\"\n> - [(set_attr \"type\" \"logic_reg,logic_imm,neon_logic\")\n> - (set_attr \"arch\" \"*,*,simd\")]\n> +(define_insn_and_split \"3\"\n> + [(set (match_operand:GPI 0 \"register_operand\")\n> +\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\")\n> +\t\t (match_operand:GPI 2 \"aarch64_logical_operand\")))]\n> + \"\"\n> + {@ [cons: =0, 1, 2; attrs: type, arch]\n> + [r , %r, r ; logic_reg , * ] \\t%0, %1, %2\n> + [rk, r , ; logic_imm , * ] \\t%0, %1, %2\n> + [w , 0 , ; * , sve ] #\n> + [w , w , w ; neon_logic, simd] \\t%0., %1., %2.\n> + }\n> + \"&& TARGET_SVE && rtx_equal_p (operands[0], operands[1])\n> + && satisfies_constraint_ (operands[2])\n> + && FP_REGNUM_P (REGNO (operands[0]))\"\n> + [(const_int 0)]\n> + {\n> + rtx op1 = lowpart_subreg (mode, operands[1], mode);\n> + rtx op2 = gen_const_vec_duplicate (mode, operands[2]);\n> + emit_insn (gen_3 (op1, op1, op2));\n> + DONE;\n> + }\n> )\n\nThe WIP SME patches add a %Z modifier for 'z' register prefixes,\nsimilarly to b/h/s/d for scalar FP. With that I think the alternative\ncan be:\n\n [w , 0 , ; * , sve ] \\t%Z0., %Z0., #%2\n\nalthough it would be nice to keep the hex constant.\n\nWill try to post the patches up to that part soon.\n\nThanks,\nRichard\n\n> \n> ;; zero_extend version of above\n> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\n> index d17becc37e230684beaee3c69e2a0f0ce612eda5..568cd5d1a3a9e00475376177ad13de72609df3d8 100644\n> --- a/gcc/config/aarch64/iterators.md\n> +++ b/gcc/config/aarch64/iterators.md\n> @@ -1432,6 +1432,11 @@ (define_mode_attr VCONQ [(V8QI \"V16QI\") (V16QI \"V16QI\")\n> \t\t\t (HI \"V8HI\") (QI \"V16QI\")\n> \t\t\t (SF \"V4SF\") (DF \"V2DF\")])\n> \n> +;; 128-bit container modes for the lower part of an SVE vector to the inner or\n> +;; scalar source mode.\n> +(define_mode_attr VCONV [(SI \"VNx4SI\") (DI \"VNx2DI\")])\n> +(define_mode_attr vconv [(SI \"vnx4si\") (DI \"vnx2di\")])\n> +\n> ;; Half modes of all vector modes.\n> (define_mode_attr VHALF [(V8QI \"V4QI\") (V16QI \"V8QI\")\n> \t\t\t (V4HI \"V2HI\") (V8HI \"V4HI\")\n> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> index a60cd31b9294af2dac69eed1c93f899bd5c78fca..fe9f27bf91b8fb18205a5891a5d5e847a5d88e4b 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> @@ -7,8 +7,7 @@\n> \n> /*\n> ** f1:\n> -**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n> -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> +**\torr\tz0.s, z0.s, #0x80000000\n> **\tret\n> */\n> float32_t f1 (float32_t a)\n> @@ -18,9 +17,7 @@ float32_t f1 (float32_t a)\n> \n> /*\n> ** f2:\n> -**\tmov\tx0, -9223372036854775808\n> -**\tfmov\td[0-9]+, x0\n> -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> +**\torr\tz0.d, z0.d, #0x8000000000000000\n> **\tret\n> */\n> float64_t f2 (float64_t a)\n> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> index 21f2a8da2a5d44e3d01f6604ca7be87e3744d494..707bcb0b6c53e212b55a255f500e9e548e9ccd80 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> @@ -6,9 +6,7 @@\n> \n> /*\n> ** negabs:\n> -**\tmov\tx0, -9223372036854775808\n> -**\tfmov\td[0-9]+, x0\n> -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> +**\torr\tz0.d, z0.d, #0x8000000000000000\n> **\tret\n> */\n> double negabs (double x)\n> @@ -22,8 +20,7 @@ double negabs (double x)\n> \n> /*\n> ** negabsf:\n> -**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n> -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> +**\torr\tz0.s, z0.s, #0x80000000\n> **\tret\n> */\n> float negabsf (float x)","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=8.43.85.97; helo=server2.sourceware.org;\n envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=arm.com","sourceware.org; spf=pass smtp.mailfrom=arm.com"],"Received":["from server2.sourceware.org (ip-8-43-85-97.sourceware.org\n [8.43.85.97])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4RwVgZ5K0dz1ypJ\n\tfor ; Wed, 27 Sep 2023 18:50:34 +1000 (AEST)","from server2.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id A04FE3861882\n\tfor ; Wed, 27 Sep 2023 08:50:32 +0000 (GMT)","from foss.arm.com (foss.arm.com [217.140.110.172])\n by sourceware.org (Postfix) with ESMTP id BB8B03858035\n for ; Wed, 27 Sep 2023 08:50:09 +0000 (GMT)","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8B0F21FB;\n Wed, 27 Sep 2023 01:50:47 -0700 (PDT)","from localhost (e121540-lin.manchester.arm.com [10.32.110.72])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6F2C53F59C;\n Wed, 27 Sep 2023 01:50:08 -0700 (PDT)"],"DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org BB8B03858035","From":"Richard Sandiford ","To":"Tamar Christina ","Mail-Followup-To":"Tamar Christina ,\n gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com,\n Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com","Cc":"gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com,\n Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com","Subject":"Re: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when\n Advanced SIMD inefficient [PR109154]","References":"","Date":"Wed, 27 Sep 2023 09:50:07 +0100","In-Reply-To":" (Tamar Christina's message of \"Wed,\n 27 Sep 2023 01:51:30 +0100\")","Message-ID":"","User-Agent":"Gnus/5.13 (Gnus v5.13) Emacs/26.3 (gnu/linux)","MIME-Version":"1.0","Content-Type":"text/plain","X-Spam-Status":"No, score=-24.5 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH,\n KAM_SHORT, SPF_HELO_NONE, SPF_NONE,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3188534,"web_url":"http://patchwork.ozlabs.org/comment/3188534/","msgid":"","list_archive_url":null,"date":"2023-09-27T08:54:17","subject":"RE: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when\n Advanced SIMD inefficient [PR109154]","submitter":{"id":69689,"url":"http://patchwork.ozlabs.org/api/people/69689/","name":"Tamar Christina","email":"Tamar.Christina@arm.com"},"content":"> -----Original Message-----\n> From: Richard Sandiford \n> Sent: Wednesday, September 27, 2023 9:50 AM\n> To: Tamar Christina \n> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw\n> ; Marcus Shawcroft\n> ; Kyrylo Tkachov \n> Subject: Re: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions\n> when Advanced SIMD inefficient [PR109154]\n> \n> Tamar Christina writes:\n> > Hi All,\n> >\n> > SVE has much bigger immediate encoding range for bitmasks than\n> > Advanced SIMD has and so on a system that is SVE capable if we need an\n> > Advanced SIMD Inclusive-OR by immediate and would require a reload then\n> an unpredicated SVE ORR instead.\n> >\n> > This has both speed and size improvements.\n> >\n> > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n> >\n> > Ok for master?\n> >\n> > Thanks,\n> > Tamar\n> >\n> > gcc/ChangeLog:\n> >\n> > \tPR tree-optimization/109154\n> > \t* config/aarch64/aarch64.md (3): Convert to new\n> syntax and\n> > \tSVE split case.\n> > \t* config/aarch64/iterators.md (VCONV, vconv): New.\n> >\n> > gcc/testsuite/ChangeLog:\n> >\n> > \tPR tree-optimization/109154\n> > \t* gcc.target/aarch64/sve/fneg-abs_2.c: Updated.\n> > \t* gcc.target/aarch64/sve/fneg-abs_4.c: Updated.\n> >\n> > --- inline copy of patch --\n> > diff --git a/gcc/config/aarch64/aarch64.md\n> > b/gcc/config/aarch64/aarch64.md index\n> >\n> 60c92213c75a2a4c18a6b59ae52fe45d1e872718..377c5cafedd43d8d13204\n> 89a3626\n> > 7cc6e5f15239 100644\n> > --- a/gcc/config/aarch64/aarch64.md\n> > +++ b/gcc/config/aarch64/aarch64.md\n> > @@ -4551,17 +4551,27 @@ (define_insn_and_split\n> \"*aarch64_and_imm2\"\n> > }\n> > )\n> >\n> > -(define_insn \"3\"\n> > - [(set (match_operand:GPI 0 \"register_operand\" \"=r,rk,w\")\n> > -\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\" \"%r,r,w\")\n> > -\t\t (match_operand:GPI 2 \"aarch64_logical_operand\"\n> \"r,,w\")))]\n> > - \"\"\n> > - \"@\n> > - \\\\t%0, %1, %2\n> > - \\\\t%0, %1, %2\n> > - \\\\t%0., %1., %2.\"\n> > - [(set_attr \"type\" \"logic_reg,logic_imm,neon_logic\")\n> > - (set_attr \"arch\" \"*,*,simd\")]\n> > +(define_insn_and_split \"3\"\n> > + [(set (match_operand:GPI 0 \"register_operand\")\n> > +\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\")\n> > +\t\t (match_operand:GPI 2 \"aarch64_logical_operand\")))]\n> > + \"\"\n> > + {@ [cons: =0, 1, 2; attrs: type, arch]\n> > + [r , %r, r ; logic_reg , * ] \\t%0, %1, %2\n> > + [rk, r , ; logic_imm , * ] \\t%0, %1, %2\n> > + [w , 0 , ; * , sve ] #\n> > + [w , w , w ; neon_logic, simd] \\t%0., %1.,\n> %2.\n> > + }\n> > + \"&& TARGET_SVE && rtx_equal_p (operands[0], operands[1])\n> > + && satisfies_constraint_ (operands[2])\n> > + && FP_REGNUM_P (REGNO (operands[0]))\"\n> > + [(const_int 0)]\n> > + {\n> > + rtx op1 = lowpart_subreg (mode, operands[1], mode);\n> > + rtx op2 = gen_const_vec_duplicate (mode, operands[2]);\n> > + emit_insn (gen_3 (op1, op1, op2));\n> > + DONE;\n> > + }\n> > )\n> \n> The WIP SME patches add a %Z modifier for 'z' register prefixes, similarly to\n> b/h/s/d for scalar FP. With that I think the alternative can be:\n> \n> [w , 0 , ; * , sve ] \\t%Z0., %Z0., #%2\n> \n> although it would be nice to keep the hex constant.\n\nMy original patch added a %u for (undecorated) which just prints the register\nnumber and changed %C to also accept a single constant instead of only a uniform vector.\n\nBut I figured you wouldn't like that? 😊\n\nCheers,\nTamar\n\n> \n> Will try to post the patches up to that part soon.\n> \n> Thanks,\n> Richard\n> \n> >\n> > ;; zero_extend version of above\n> > diff --git a/gcc/config/aarch64/iterators.md\n> > b/gcc/config/aarch64/iterators.md index\n> >\n> d17becc37e230684beaee3c69e2a0f0ce612eda5..568cd5d1a3a9e00475376\n> 177ad13\n> > de72609df3d8 100644\n> > --- a/gcc/config/aarch64/iterators.md\n> > +++ b/gcc/config/aarch64/iterators.md\n> > @@ -1432,6 +1432,11 @@ (define_mode_attr VCONQ [(V8QI \"V16QI\")\n> (V16QI \"V16QI\")\n> > \t\t\t (HI \"V8HI\") (QI \"V16QI\")\n> > \t\t\t (SF \"V4SF\") (DF \"V2DF\")])\n> >\n> > +;; 128-bit container modes for the lower part of an SVE vector to the\n> > +inner or ;; scalar source mode.\n> > +(define_mode_attr VCONV [(SI \"VNx4SI\") (DI \"VNx2DI\")])\n> > +(define_mode_attr vconv [(SI \"vnx4si\") (DI \"vnx2di\")])\n> > +\n> > ;; Half modes of all vector modes.\n> > (define_mode_attr VHALF [(V8QI \"V4QI\") (V16QI \"V8QI\")\n> > \t\t\t (V4HI \"V2HI\") (V8HI \"V4HI\")\n> > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> > b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> > index\n> >\n> a60cd31b9294af2dac69eed1c93f899bd5c78fca..fe9f27bf91b8fb18205a589\n> 1a5d5\n> > e847a5d88e4b 100644\n> > --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> > +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> > @@ -7,8 +7,7 @@\n> >\n> > /*\n> > ** f1:\n> > -**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n> > -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> > +**\torr\tz0.s, z0.s, #0x80000000\n> > **\tret\n> > */\n> > float32_t f1 (float32_t a)\n> > @@ -18,9 +17,7 @@ float32_t f1 (float32_t a)\n> >\n> > /*\n> > ** f2:\n> > -**\tmov\tx0, -9223372036854775808\n> > -**\tfmov\td[0-9]+, x0\n> > -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> > +**\torr\tz0.d, z0.d, #0x8000000000000000\n> > **\tret\n> > */\n> > float64_t f2 (float64_t a)\n> > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> > b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> > index\n> >\n> 21f2a8da2a5d44e3d01f6604ca7be87e3744d494..707bcb0b6c53e212b55a\n> 255f500e\n> > 9e548e9ccd80 100644\n> > --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> > +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> > @@ -6,9 +6,7 @@\n> >\n> > /*\n> > ** negabs:\n> > -**\tmov\tx0, -9223372036854775808\n> > -**\tfmov\td[0-9]+, x0\n> > -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> > +**\torr\tz0.d, z0.d, #0x8000000000000000\n> > **\tret\n> > */\n> > double negabs (double x)\n> > @@ -22,8 +20,7 @@ double negabs (double x)\n> >\n> > /*\n> > ** negabsf:\n> > -**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n> > -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> > +**\torr\tz0.s, z0.s, #0x80000000\n> > **\tret\n> > */\n> > float negabsf (float x)","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com\n header.b=vJ/uCyNs;\n\tdkim=pass (1024-bit key) header.d=armh.onmicrosoft.com\n header.i=@armh.onmicrosoft.com header.a=rsa-sha256\n header.s=selector2-armh-onmicrosoft-com header.b=vJ/uCyNs;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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Ip=[63.35.35.123];\n Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n AM7EUR03FT065.eop-EUR03.prod.protection.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-Spam-Status":"No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH,\n KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE,\n TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3188643,"web_url":"http://patchwork.ozlabs.org/comment/3188643/","msgid":"","list_archive_url":null,"date":"2023-09-27T10:45:54","subject":"Re: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when\n Advanced SIMD inefficient [PR109154]","submitter":{"id":64746,"url":"http://patchwork.ozlabs.org/api/people/64746/","name":"Richard Sandiford","email":"richard.sandiford@arm.com"},"content":"Tamar Christina writes:\n>> -----Original Message-----\n>> From: Richard Sandiford \n>> Sent: Wednesday, September 27, 2023 9:50 AM\n>> To: Tamar Christina \n>> Cc: gcc-patches@gcc.gnu.org; nd ; Richard Earnshaw\n>> ; Marcus Shawcroft\n>> ; Kyrylo Tkachov \n>> Subject: Re: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions\n>> when Advanced SIMD inefficient [PR109154]\n>> \n>> Tamar Christina writes:\n>> > Hi All,\n>> >\n>> > SVE has much bigger immediate encoding range for bitmasks than\n>> > Advanced SIMD has and so on a system that is SVE capable if we need an\n>> > Advanced SIMD Inclusive-OR by immediate and would require a reload then\n>> an unpredicated SVE ORR instead.\n>> >\n>> > This has both speed and size improvements.\n>> >\n>> > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n>> >\n>> > Ok for master?\n>> >\n>> > Thanks,\n>> > Tamar\n>> >\n>> > gcc/ChangeLog:\n>> >\n>> > \tPR tree-optimization/109154\n>> > \t* config/aarch64/aarch64.md (3): Convert to new\n>> syntax and\n>> > \tSVE split case.\n>> > \t* config/aarch64/iterators.md (VCONV, vconv): New.\n>> >\n>> > gcc/testsuite/ChangeLog:\n>> >\n>> > \tPR tree-optimization/109154\n>> > \t* gcc.target/aarch64/sve/fneg-abs_2.c: Updated.\n>> > \t* gcc.target/aarch64/sve/fneg-abs_4.c: Updated.\n>> >\n>> > --- inline copy of patch --\n>> > diff --git a/gcc/config/aarch64/aarch64.md\n>> > b/gcc/config/aarch64/aarch64.md index\n>> >\n>> 60c92213c75a2a4c18a6b59ae52fe45d1e872718..377c5cafedd43d8d13204\n>> 89a3626\n>> > 7cc6e5f15239 100644\n>> > --- a/gcc/config/aarch64/aarch64.md\n>> > +++ b/gcc/config/aarch64/aarch64.md\n>> > @@ -4551,17 +4551,27 @@ (define_insn_and_split\n>> \"*aarch64_and_imm2\"\n>> > }\n>> > )\n>> >\n>> > -(define_insn \"3\"\n>> > - [(set (match_operand:GPI 0 \"register_operand\" \"=r,rk,w\")\n>> > -\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\" \"%r,r,w\")\n>> > -\t\t (match_operand:GPI 2 \"aarch64_logical_operand\"\n>> \"r,,w\")))]\n>> > - \"\"\n>> > - \"@\n>> > - \\\\t%0, %1, %2\n>> > - \\\\t%0, %1, %2\n>> > - \\\\t%0., %1., %2.\"\n>> > - [(set_attr \"type\" \"logic_reg,logic_imm,neon_logic\")\n>> > - (set_attr \"arch\" \"*,*,simd\")]\n>> > +(define_insn_and_split \"3\"\n>> > + [(set (match_operand:GPI 0 \"register_operand\")\n>> > +\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\")\n>> > +\t\t (match_operand:GPI 2 \"aarch64_logical_operand\")))]\n>> > + \"\"\n>> > + {@ [cons: =0, 1, 2; attrs: type, arch]\n>> > + [r , %r, r ; logic_reg , * ] \\t%0, %1, %2\n>> > + [rk, r , ; logic_imm , * ] \\t%0, %1, %2\n>> > + [w , 0 , ; * , sve ] #\n>> > + [w , w , w ; neon_logic, simd] \\t%0., %1.,\n>> %2.\n>> > + }\n>> > + \"&& TARGET_SVE && rtx_equal_p (operands[0], operands[1])\n>> > + && satisfies_constraint_ (operands[2])\n>> > + && FP_REGNUM_P (REGNO (operands[0]))\"\n>> > + [(const_int 0)]\n>> > + {\n>> > + rtx op1 = lowpart_subreg (mode, operands[1], mode);\n>> > + rtx op2 = gen_const_vec_duplicate (mode, operands[2]);\n>> > + emit_insn (gen_3 (op1, op1, op2));\n>> > + DONE;\n>> > + }\n>> > )\n>> \n>> The WIP SME patches add a %Z modifier for 'z' register prefixes, similarly to\n>> b/h/s/d for scalar FP. With that I think the alternative can be:\n>> \n>> [w , 0 , ; * , sve ] \\t%Z0., %Z0., #%2\n>> \n>> although it would be nice to keep the hex constant.\n>\n> My original patch added a %u for (undecorated) which just prints the register\n> number and changed %C to also accept a single constant instead of only a uniform vector.\n\nNot saying no to %u in future, but %Z seems more consistent with the\ncurrent approach. And yeah, I'd also wondered about extending %C.\nThe problem is guessing whether to print a 32-bit, 64-bit or 128-bit\nconstant for negative immediates.\n\nThanks,\nRichard\n\n> But I figured you wouldn't like that? 😊\n>\n> Cheers,\n> Tamar\n>\n>> \n>> Will try to post the patches up to that part soon.\n>> \n>> Thanks,\n>> Richard\n>> \n>> >\n>> > ;; zero_extend version of above\n>> > diff --git a/gcc/config/aarch64/iterators.md\n>> > b/gcc/config/aarch64/iterators.md index\n>> >\n>> d17becc37e230684beaee3c69e2a0f0ce612eda5..568cd5d1a3a9e00475376\n>> 177ad13\n>> > de72609df3d8 100644\n>> > --- a/gcc/config/aarch64/iterators.md\n>> > +++ b/gcc/config/aarch64/iterators.md\n>> > @@ -1432,6 +1432,11 @@ (define_mode_attr VCONQ [(V8QI \"V16QI\")\n>> (V16QI \"V16QI\")\n>> > \t\t\t (HI \"V8HI\") (QI \"V16QI\")\n>> > \t\t\t (SF \"V4SF\") (DF \"V2DF\")])\n>> >\n>> > +;; 128-bit container modes for the lower part of an SVE vector to the\n>> > +inner or ;; scalar source mode.\n>> > +(define_mode_attr VCONV [(SI \"VNx4SI\") (DI \"VNx2DI\")])\n>> > +(define_mode_attr vconv [(SI \"vnx4si\") (DI \"vnx2di\")])\n>> > +\n>> > ;; Half modes of all vector modes.\n>> > (define_mode_attr VHALF [(V8QI \"V4QI\") (V16QI \"V8QI\")\n>> > \t\t\t (V4HI \"V2HI\") (V8HI \"V4HI\")\n>> > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n>> > b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n>> > index\n>> >\n>> a60cd31b9294af2dac69eed1c93f899bd5c78fca..fe9f27bf91b8fb18205a589\n>> 1a5d5\n>> > e847a5d88e4b 100644\n>> > --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n>> > +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n>> > @@ -7,8 +7,7 @@\n>> >\n>> > /*\n>> > ** f1:\n>> > -**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n>> > -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n>> > +**\torr\tz0.s, z0.s, #0x80000000\n>> > **\tret\n>> > */\n>> > float32_t f1 (float32_t a)\n>> > @@ -18,9 +17,7 @@ float32_t f1 (float32_t a)\n>> >\n>> > /*\n>> > ** f2:\n>> > -**\tmov\tx0, -9223372036854775808\n>> > -**\tfmov\td[0-9]+, x0\n>> > -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n>> > +**\torr\tz0.d, z0.d, #0x8000000000000000\n>> > **\tret\n>> > */\n>> > float64_t f2 (float64_t a)\n>> > diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n>> > b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n>> > index\n>> >\n>> 21f2a8da2a5d44e3d01f6604ca7be87e3744d494..707bcb0b6c53e212b55a\n>> 255f500e\n>> > 9e548e9ccd80 100644\n>> > --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n>> > +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n>> > @@ -6,9 +6,7 @@\n>> >\n>> > /*\n>> > ** negabs:\n>> > -**\tmov\tx0, -9223372036854775808\n>> > -**\tfmov\td[0-9]+, x0\n>> > -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n>> > +**\torr\tz0.d, z0.d, #0x8000000000000000\n>> > **\tret\n>> > */\n>> > double negabs (double x)\n>> > @@ -22,8 +20,7 @@ double negabs (double x)\n>> >\n>> > /*\n>> > ** negabsf:\n>> > -**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n>> > -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n>> > +**\torr\tz0.s, z0.s, #0x80000000\n>> > **\tret\n>> > */\n>> > float negabsf (float x)","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=8.43.85.97; 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charset=utf-8","Content-Transfer-Encoding":"quoted-printable","X-Spam-Status":"No, score=-24.5 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_LOTSOFHASH,\n KAM_SHORT, SPF_HELO_NONE, SPF_NONE,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3193899,"web_url":"http://patchwork.ozlabs.org/comment/3193899/","msgid":"","list_archive_url":null,"date":"2023-10-05T18:15:26","subject":"RE: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when\n Advanced SIMD inefficient [PR109154]","submitter":{"id":69689,"url":"http://patchwork.ozlabs.org/api/people/69689/","name":"Tamar Christina","email":"Tamar.Christina@arm.com"},"content":"> >>\n> >> The WIP SME patches add a %Z modifier for 'z' register prefixes,\n> >> similarly to b/h/s/d for scalar FP. With that I think the alternative can be:\n> >>\n> >> [w , 0 , ; * , sve ] \\t%Z0., %Z0., #%2\n> >>\n> >> although it would be nice to keep the hex constant.\n> >\n> > My original patch added a %u for (undecorated) which just prints the\n> > register number and changed %C to also accept a single constant instead of\n> only a uniform vector.\n> \n> Not saying no to %u in future, but %Z seems more consistent with the current\n> approach. And yeah, I'd also wondered about extending %C.\n> The problem is guessing whether to print a 32-bit, 64-bit or 128-bit constant\n> for negative immediates.\n> \n\nI know we're waiting for the %Z but I've updated the remainder of the series and for\ncompleteness and CI purposes I'm sending the updated patch before the change to\nuse %Z.\n\n--\n\nSVE has much bigger immediate encoding range for bitmasks than Advanced SIMD has\nand so on a system that is SVE capable if we need an Advanced SIMD Inclusive-OR\nby immediate and would require a reload then use an unpredicated SVE ORR instead.\n\nThis has both speed and size improvements.\n\nBootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n\nOk for master?\n\nThanks,\nTamar\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* config/aarch64/aarch64.md (3): Add SVE split case.\n\t* config/aarch64/aarch64-simd.md (ior3): Likewise.\n\t* config/aarch64/iterators.md (VCONV, vconv): New.\n\t* config/aarch64/predicates.md(aarch64_orr_imm_sve_advsimd): New.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* gcc.target/aarch64/sve/fneg-abs_1.c: Updated.\n\t* gcc.target/aarch64/sve/fneg-abs_2.c: Updated.\n\t* gcc.target/aarch64/sve/fneg-abs_4.c: Updated.\n\n--- inline copy of patch ---\n\ndiff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 33eceb436584ff73c7271f93639f2246d1af19e0..25a1e4e8ecf767636c0ff3cdab6cad6e1482f73e 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -1216,14 +1216,29 @@ (define_insn \"and3\"\n )\n \n ;; For ORR (vector, register) and ORR (vector, immediate)\n-(define_insn \"ior3\"\n+(define_insn_and_split \"ior3\"\n [(set (match_operand:VDQ_I 0 \"register_operand\")\n \t(ior:VDQ_I (match_operand:VDQ_I 1 \"register_operand\")\n-\t\t (match_operand:VDQ_I 2 \"aarch64_reg_or_orr_imm\")))]\n+\t\t (match_operand:VDQ_I 2 \"aarch64_orr_imm_sve_advsimd\")))]\n \"TARGET_SIMD\"\n- {@ [ cons: =0 , 1 , 2 ]\n- [ w , w , w ] orr\\t%0., %1., %2.\n- [ w , 0 , Do ] << aarch64_output_simd_mov_immediate (operands[2], , AARCH64_CHECK_ORR);\n+ {@ [ cons: =0 , 1 , 2; attrs: arch ]\n+ [ w , w , w ; simd ] orr\\t%0., %1., %2.\n+ [ w , 0 , vsl; sve ] #\n+ [ w , 0 , Do ; simd ] \\\n+ << aarch64_output_simd_mov_immediate (operands[2], , \\\n+\t\t\t\t\t AARCH64_CHECK_ORR);\n+ }\n+ \"&& TARGET_SVE && rtx_equal_p (operands[0], operands[1])\n+ && satisfies_constraint_vsl (operands[2])\n+ && FP_REGNUM_P (REGNO (operands[0]))\"\n+ [(const_int 0)]\n+ {\n+ rtx op1 = lowpart_subreg (mode, operands[1], mode);\n+ rtx op2 =\n+ gen_const_vec_duplicate (mode,\n+\t\t\t unwrap_const_vec_duplicate (operands[2]));\n+ emit_insn (gen_ior3 (op1, op1, op2));\n+ DONE;\n }\n [(set_attr \"type\" \"neon_logic\")]\n )\ndiff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 064d68ceb22533434468b22c4e5848e85a8c6eff..24349ecdbbab875f21975f116732a9e53762d4c1 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -4545,7 +4545,7 @@ (define_insn_and_split \"*aarch64_and_imm2\"\n }\n )\n \n-(define_insn \"3\"\n+(define_insn_and_split \"3\"\n [(set (match_operand:GPI 0 \"register_operand\")\n \t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\")\n \t\t (match_operand:GPI 2 \"aarch64_logical_operand\")))]\n@@ -4553,8 +4553,19 @@ (define_insn \"3\"\n {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ]\n [ r , %r , r ; logic_reg , * ] \\t%0, %1, %2\n [ rk , r , ; logic_imm , * ] \\t%0, %1, %2\n+ [ w , 0 , ; * , sve ] #\n [ w , w , w ; neon_logic , simd ] \\t%0., %1., %2.\n }\n+ \"&& TARGET_SVE && rtx_equal_p (operands[0], operands[1])\n+ && satisfies_constraint_ (operands[2])\n+ && FP_REGNUM_P (REGNO (operands[0]))\"\n+ [(const_int 0)]\n+ {\n+ rtx op1 = lowpart_subreg (mode, operands[1], mode);\n+ rtx op2 = gen_const_vec_duplicate (mode, operands[2]);\n+ emit_insn (gen_3 (op1, op1, op2));\n+ DONE;\n+ }\n )\n \n ;; zero_extend version of above\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex d17becc37e230684beaee3c69e2a0f0ce612eda5..5ec854a364e41b9827271ca6e870c8027336c7cd 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -1432,6 +1432,19 @@ (define_mode_attr VCONQ [(V8QI \"V16QI\") (V16QI \"V16QI\")\n \t\t\t (HI \"V8HI\") (QI \"V16QI\")\n \t\t\t (SF \"V4SF\") (DF \"V2DF\")])\n \n+;; 128-bit container modes for the lower part of an SVE vector to the inner or\n+;; neon source mode.\n+(define_mode_attr VCONV [(SI \"VNx4SI\") (DI \"VNx2DI\")\n+\t\t\t (V8QI \"VNx16QI\") (V16QI \"VNx16QI\")\n+\t\t\t (V4HI \"VNx8HI\") (V8HI \"VNx8HI\")\n+\t\t\t (V2SI \"VNx4SI\") (V4SI \"VNx4SI\")\n+\t\t\t (V2DI \"VNx2DI\")])\n+(define_mode_attr vconv [(SI \"vnx4si\") (DI \"vnx2di\")\n+\t\t\t (V8QI \"vnx16qi\") (V16QI \"vnx16qi\")\n+\t\t\t (V4HI \"vnx8hi\") (V8HI \"vnx8hi\")\n+\t\t\t (V2SI \"vnx4si\") (V4SI \"vnx4si\")\n+\t\t\t (V2DI \"vnx2di\")])\n+\n ;; Half modes of all vector modes.\n (define_mode_attr VHALF [(V8QI \"V4QI\") (V16QI \"V8QI\")\n \t\t\t (V4HI \"V2HI\") (V8HI \"V4HI\")\ndiff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md\nindex 01de47439744acb3708c645b98eaa607294a1f1f..a73724a7fc05636d4c0643a291f40f2609564778 100644\n--- a/gcc/config/aarch64/predicates.md\n+++ b/gcc/config/aarch64/predicates.md\n@@ -871,6 +871,11 @@ (define_predicate \"aarch64_sve_logical_operand\"\n (ior (match_operand 0 \"register_operand\")\n (match_operand 0 \"aarch64_sve_logical_immediate\")))\n \n+(define_predicate \"aarch64_orr_imm_sve_advsimd\"\n+ (ior (match_operand 0 \"aarch64_reg_or_orr_imm\")\n+ (and (match_test \"TARGET_SVE\")\n+\t (match_operand 0 \"aarch64_sve_logical_operand\"))))\n+\n (define_predicate \"aarch64_sve_gather_offset_b\"\n (ior (match_operand 0 \"register_operand\")\n (match_operand 0 \"aarch64_sve_gather_immediate_b\")))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\nindex 0c7664e6de77a497682952653ffd417453854d52..68e6ef0bdb234f26d0c3b055e777a9e1fb214c6d 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\n@@ -6,7 +6,7 @@\n \n /*\n ** t1:\n-**\torr\tv[0-9]+.2s, #128, lsl #24\n+**\torr\tz[0-9]+.s, z[0-9]+.s, #0x80000000\n **\tret\n */\n float32x2_t t1 (float32x2_t a)\n@@ -16,7 +16,7 @@ float32x2_t t1 (float32x2_t a)\n \n /*\n ** t2:\n-**\torr\tv[0-9]+.4s, #128, lsl #24\n+**\torr\tz[0-9]+.s, z[0-9]+.s, #0x80000000\n **\tret\n */\n float32x4_t t2 (float32x4_t a)\n@@ -26,9 +26,7 @@ float32x4_t t2 (float32x4_t a)\n \n /*\n ** t3:\n-**\tadrp\tx0, .LC[0-9]+\n-**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n-**\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n+**\torr\tz[0-9]+.d, z[0-9]+.d, #0x8000000000000000\n **\tret\n */\n float64x2_t t3 (float64x2_t a)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\nindex a60cd31b9294af2dac69eed1c93f899bd5c78fca..fe9f27bf91b8fb18205a5891a5d5e847a5d88e4b 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n@@ -7,8 +7,7 @@\n \n /*\n ** f1:\n-**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.s, z0.s, #0x80000000\n **\tret\n */\n float32_t f1 (float32_t a)\n@@ -18,9 +17,7 @@ float32_t f1 (float32_t a)\n \n /*\n ** f2:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.d, z0.d, #0x8000000000000000\n **\tret\n */\n float64_t f2 (float64_t a)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\nindex 21f2a8da2a5d44e3d01f6604ca7be87e3744d494..707bcb0b6c53e212b55a255f500e9e548e9ccd80 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n@@ -6,9 +6,7 @@\n \n /*\n ** negabs:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.d, z0.d, #0x8000000000000000\n **\tret\n */\n double negabs (double x)\n@@ -22,8 +20,7 @@ double negabs (double x)\n \n /*\n ** negabsf:\n-**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.s, z0.s, #0x80000000\n **\tret\n */\n float negabsf (float x)","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com\n header.b=FqtBhDgC;\n\tdkim=pass (1024-bit key) header.d=armh.onmicrosoft.com\n header.i=@armh.onmicrosoft.com header.a=rsa-sha256\n header.s=selector2-armh-onmicrosoft-com header.b=FqtBhDgC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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Ip=[63.35.35.123];\n Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n AM7EUR03FT025.eop-EUR03.prod.protection.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-Spam-Status":"No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH,\n KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, TXREP, T_SPF_TEMPERROR,\n UNPARSEABLE_RELAY,\n URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3213546,"web_url":"http://patchwork.ozlabs.org/comment/3213546/","msgid":"","list_archive_url":null,"date":"2023-11-08T14:21:25","subject":"RE: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when\n Advanced SIMD inefficient [PR109154]","submitter":{"id":69689,"url":"http://patchwork.ozlabs.org/api/people/69689/","name":"Tamar Christina","email":"Tamar.Christina@arm.com"},"content":"> >> > + \"&& TARGET_SVE && rtx_equal_p (operands[0], operands[1])\n> >> > + && satisfies_constraint_ (operands[2])\n> >> > + && FP_REGNUM_P (REGNO (operands[0]))\"\n> >> > + [(const_int 0)]\n> >> > + {\n> >> > + rtx op1 = lowpart_subreg (mode, operands[1],\n> mode);\n> >> > + rtx op2 = gen_const_vec_duplicate (mode, operands[2]);\n> >> > + emit_insn (gen_3 (op1, op1, op2));\n> >> > + DONE;\n> >> > + }\n> >> > )\n> >>\n> >> The WIP SME patches add a %Z modifier for 'z' register prefixes,\n> >> similarly to b/h/s/d for scalar FP. With that I think the alternative can be:\n> >>\n> >> [w , 0 , ; * , sve ] \\t%Z0., %Z0., #%2\n> >>\n> >> although it would be nice to keep the hex constant.\n> >\n> > My original patch added a %u for (undecorated) which just prints the\n> > register number and changed %C to also accept a single constant instead of\n> only a uniform vector.\n> \n> Not saying no to %u in future, but %Z seems more consistent with the current\n> approach. And yeah, I'd also wondered about extending %C.\n> The problem is guessing whether to print a 32-bit, 64-bit or 128-bit constant\n> for negative immediates.\n> \n\nRebased patch,\n\nBootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n\nOk for master?\n\nThanks,\nTamar\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* config/aarch64/aarch64.md (3): Add SVE case.\n\t* config/aarch64/aarch64-simd.md (ior3): Likewise.\n\t* config/aarch64/iterators.md (VCONV, vconv): New.\n\t* config/aarch64/predicates.md(aarch64_orr_imm_sve_advsimd): New.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* gcc.target/aarch64/sve/fneg-abs_1.c: Updated.\n\t* gcc.target/aarch64/sve/fneg-abs_2.c: Updated.\n\t* gcc.target/aarch64/sve/fneg-abs_4.c: Updated.\n\n--- inline copy of patch --\n\ndiff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 33eceb436584ff73c7271f93639f2246d1af19e0..98c418c54a82a348c597310caa23916f9c16f9b6 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -1219,11 +1219,14 @@ (define_insn \"and3\"\n (define_insn \"ior3\"\n [(set (match_operand:VDQ_I 0 \"register_operand\")\n \t(ior:VDQ_I (match_operand:VDQ_I 1 \"register_operand\")\n-\t\t (match_operand:VDQ_I 2 \"aarch64_reg_or_orr_imm\")))]\n- \"TARGET_SIMD\"\n- {@ [ cons: =0 , 1 , 2 ]\n- [ w , w , w ] orr\\t%0., %1., %2.\n- [ w , 0 , Do ] << aarch64_output_simd_mov_immediate (operands[2], , AARCH64_CHECK_ORR);\n+\t\t (match_operand:VDQ_I 2 \"aarch64_orr_imm_sve_advsimd\")))]\n+ \"TARGET_SIMD\"\n+ {@ [ cons: =0 , 1 , 2; attrs: arch ]\n+ [ w , w , w ; simd ] orr\\t%0., %1., %2.\n+ [ w , 0 , vsl; sve ] orr\\t%Z0., %Z0., #%2\n+ [ w , 0 , Do ; simd ] \\\n+ << aarch64_output_simd_mov_immediate (operands[2], , \\\n+\t\t\t\t\t AARCH64_CHECK_ORR);\n }\n [(set_attr \"type\" \"neon_logic\")]\n )\ndiff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 4fcd71a2e9d1e8c35f35593255c4f66a68856a79..c6b1506fe7b47dd40741f26ef0cc92692008a631 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -4599,7 +4599,8 @@ (define_insn \"3\"\n \"\"\n {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ]\n [ r , %r , r ; logic_reg , * ] \\t%0, %1, %2\n- [ rk , r , ; logic_imm , * ] \\t%0, %1, %2\n+ [ rk , ^r , ; logic_imm , * ] \\t%0, %1, %2\n+ [ w , 0 , ; * , sve ] \\t%Z0., %Z0., #%2\n [ w , w , w ; neon_logic , simd ] \\t%0., %1., %2.\n }\n )\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex 1593a8fd04f91259295d0e393cbc7973daf7bf73..d24109b4fe6a867125b9474d34d616155bc36b3f 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -1435,6 +1435,19 @@ (define_mode_attr VCONQ [(V8QI \"V16QI\") (V16QI \"V16QI\")\n \t\t\t (HI \"V8HI\") (QI \"V16QI\")\n \t\t\t (SF \"V4SF\") (DF \"V2DF\")])\n \n+;; 128-bit container modes for the lower part of an SVE vector to the inner or\n+;; neon source mode.\n+(define_mode_attr VCONV [(SI \"VNx4SI\") (DI \"VNx2DI\")\n+\t\t\t (V8QI \"VNx16QI\") (V16QI \"VNx16QI\")\n+\t\t\t (V4HI \"VNx8HI\") (V8HI \"VNx8HI\")\n+\t\t\t (V2SI \"VNx4SI\") (V4SI \"VNx4SI\")\n+\t\t\t (V2DI \"VNx2DI\")])\n+(define_mode_attr vconv [(SI \"vnx4si\") (DI \"vnx2di\")\n+\t\t\t (V8QI \"vnx16qi\") (V16QI \"vnx16qi\")\n+\t\t\t (V4HI \"vnx8hi\") (V8HI \"vnx8hi\")\n+\t\t\t (V2SI \"vnx4si\") (V4SI \"vnx4si\")\n+\t\t\t (V2DI \"vnx2di\")])\n+\n ;; Half modes of all vector modes.\n (define_mode_attr VHALF [(V8QI \"V4QI\") (V16QI \"V8QI\")\n \t\t\t (V4HI \"V2HI\") (V8HI \"V4HI\")\ndiff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md\nindex 01de47439744acb3708c645b98eaa607294a1f1f..a73724a7fc05636d4c0643a291f40f2609564778 100644\n--- a/gcc/config/aarch64/predicates.md\n+++ b/gcc/config/aarch64/predicates.md\n@@ -871,6 +871,11 @@ (define_predicate \"aarch64_sve_logical_operand\"\n (ior (match_operand 0 \"register_operand\")\n (match_operand 0 \"aarch64_sve_logical_immediate\")))\n \n+(define_predicate \"aarch64_orr_imm_sve_advsimd\"\n+ (ior (match_operand 0 \"aarch64_reg_or_orr_imm\")\n+ (and (match_test \"TARGET_SVE\")\n+\t (match_operand 0 \"aarch64_sve_logical_operand\"))))\n+\n (define_predicate \"aarch64_sve_gather_offset_b\"\n (ior (match_operand 0 \"register_operand\")\n (match_operand 0 \"aarch64_sve_gather_immediate_b\")))\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\nindex 0c7664e6de77a497682952653ffd417453854d52..a8b27199ff83d0eebadfc7dcf03f94e1229d76b8 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\n@@ -6,7 +6,7 @@\n \n /*\n ** t1:\n-**\torr\tv[0-9]+.2s, #128, lsl #24\n+**\torr\tz[0-9]+.s, z[0-9]+.s, #-2147483648\n **\tret\n */\n float32x2_t t1 (float32x2_t a)\n@@ -16,7 +16,7 @@ float32x2_t t1 (float32x2_t a)\n \n /*\n ** t2:\n-**\torr\tv[0-9]+.4s, #128, lsl #24\n+**\torr\tz[0-9]+.s, z[0-9]+.s, #-2147483648\n **\tret\n */\n float32x4_t t2 (float32x4_t a)\n@@ -26,9 +26,7 @@ float32x4_t t2 (float32x4_t a)\n \n /*\n ** t3:\n-**\tadrp\tx0, .LC[0-9]+\n-**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n-**\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n+**\torr\tz[0-9]+.d, z[0-9]+.d, #-9223372036854775808\n **\tret\n */\n float64x2_t t3 (float64x2_t a)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\nindex a60cd31b9294af2dac69eed1c93f899bd5c78fca..19a7695e605bc8aced486a9c450d1cdc6be4691a 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n@@ -7,8 +7,7 @@\n \n /*\n ** f1:\n-**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.s, z0.s, #-2147483648\n **\tret\n */\n float32_t f1 (float32_t a)\n@@ -18,9 +17,7 @@ float32_t f1 (float32_t a)\n \n /*\n ** f2:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.d, z0.d, #-9223372036854775808\n **\tret\n */\n float64_t f2 (float64_t a)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\nindex 21f2a8da2a5d44e3d01f6604ca7be87e3744d494..663d5fe17e091d128313b6b8b8dc918a01a96c4f 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n@@ -6,9 +6,7 @@\n \n /*\n ** negabs:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.d, z0.d, #-9223372036854775808\n **\tret\n */\n double negabs (double x)\n@@ -22,8 +20,7 @@ double negabs (double x)\n \n /*\n ** negabsf:\n-**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.s, z0.s, #-2147483648\n **\tret\n */\n float negabsf (float x)","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com\n header.b=gm0UAKl+;\n\tdkim=pass (1024-bit key) header.d=armh.onmicrosoft.com\n header.i=@armh.onmicrosoft.com header.a=rsa-sha256\n header.s=selector2-armh-onmicrosoft-com header.b=gm0UAKl+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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Ip=[63.35.35.123];\n Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com]","X-MS-Exchange-CrossTenant-AuthSource":"\n DB5PEPF00014B8C.eurprd02.prod.outlook.com","X-MS-Exchange-CrossTenant-AuthAs":"Anonymous","X-MS-Exchange-CrossTenant-FromEntityHeader":"HybridOnPrem","X-Spam-Status":"No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH,\n KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE,\n TXREP, T_SCC_BODY_TEXT_LINE,\n UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3214101,"web_url":"http://patchwork.ozlabs.org/comment/3214101/","msgid":"","list_archive_url":null,"date":"2023-11-09T10:39:00","subject":"Re: [PATCH]AArch64: Use SVE unpredicated LOGICAL expressions when\n Advanced SIMD inefficient [PR109154]","submitter":{"id":64746,"url":"http://patchwork.ozlabs.org/api/people/64746/","name":"Richard Sandiford","email":"richard.sandiford@arm.com"},"content":"Tamar Christina writes:\n>> >> > + \"&& TARGET_SVE && rtx_equal_p (operands[0], operands[1])\n>> >> > + && satisfies_constraint_ (operands[2])\n>> >> > + && FP_REGNUM_P (REGNO (operands[0]))\"\n>> >> > + [(const_int 0)]\n>> >> > + {\n>> >> > + rtx op1 = lowpart_subreg (mode, operands[1],\n>> mode);\n>> >> > + rtx op2 = gen_const_vec_duplicate (mode, operands[2]);\n>> >> > + emit_insn (gen_3 (op1, op1, op2));\n>> >> > + DONE;\n>> >> > + }\n>> >> > )\n>> >>\n>> >> The WIP SME patches add a %Z modifier for 'z' register prefixes,\n>> >> similarly to b/h/s/d for scalar FP. With that I think the alternative can be:\n>> >>\n>> >> [w , 0 , ; * , sve ] \\t%Z0., %Z0., #%2\n>> >>\n>> >> although it would be nice to keep the hex constant.\n>> >\n>> > My original patch added a %u for (undecorated) which just prints the\n>> > register number and changed %C to also accept a single constant instead of\n>> only a uniform vector.\n>> \n>> Not saying no to %u in future, but %Z seems more consistent with the current\n>> approach. And yeah, I'd also wondered about extending %C.\n>> The problem is guessing whether to print a 32-bit, 64-bit or 128-bit constant\n>> for negative immediates.\n>> \n>\n> Rebased patch,\n>\n> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n>\n> Ok for master?\n>\n> Thanks,\n> Tamar\n>\n> gcc/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* config/aarch64/aarch64.md (3): Add SVE case.\n> \t* config/aarch64/aarch64-simd.md (ior3): Likewise.\n> \t* config/aarch64/iterators.md (VCONV, vconv): New.\n> \t* config/aarch64/predicates.md(aarch64_orr_imm_sve_advsimd): New.\n>\n> gcc/testsuite/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* gcc.target/aarch64/sve/fneg-abs_1.c: Updated.\n> \t* gcc.target/aarch64/sve/fneg-abs_2.c: Updated.\n> \t* gcc.target/aarch64/sve/fneg-abs_4.c: Updated.\n>\n> --- inline copy of patch --\n>\n> diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\n> index 33eceb436584ff73c7271f93639f2246d1af19e0..98c418c54a82a348c597310caa23916f9c16f9b6 100644\n> --- a/gcc/config/aarch64/aarch64-simd.md\n> +++ b/gcc/config/aarch64/aarch64-simd.md\n> @@ -1219,11 +1219,14 @@ (define_insn \"and3\"\n> (define_insn \"ior3\"\n> [(set (match_operand:VDQ_I 0 \"register_operand\")\n> \t(ior:VDQ_I (match_operand:VDQ_I 1 \"register_operand\")\n> -\t\t (match_operand:VDQ_I 2 \"aarch64_reg_or_orr_imm\")))]\n> - \"TARGET_SIMD\"\n> - {@ [ cons: =0 , 1 , 2 ]\n> - [ w , w , w ] orr\\t%0., %1., %2.\n> - [ w , 0 , Do ] << aarch64_output_simd_mov_immediate (operands[2], , AARCH64_CHECK_ORR);\n> +\t\t (match_operand:VDQ_I 2 \"aarch64_orr_imm_sve_advsimd\")))]\n> + \"TARGET_SIMD\"\n> + {@ [ cons: =0 , 1 , 2; attrs: arch ]\n> + [ w , w , w ; simd ] orr\\t%0., %1., %2.\n> + [ w , 0 , vsl; sve ] orr\\t%Z0., %Z0., #%2\n> + [ w , 0 , Do ; simd ] \\\n> + << aarch64_output_simd_mov_immediate (operands[2], , \\\n> +\t\t\t\t\t AARCH64_CHECK_ORR);\n> }\n> [(set_attr \"type\" \"neon_logic\")]\n> )\n> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\n> index 4fcd71a2e9d1e8c35f35593255c4f66a68856a79..c6b1506fe7b47dd40741f26ef0cc92692008a631 100644\n> --- a/gcc/config/aarch64/aarch64.md\n> +++ b/gcc/config/aarch64/aarch64.md\n> @@ -4599,7 +4599,8 @@ (define_insn \"3\"\n> \"\"\n> {@ [ cons: =0 , 1 , 2 ; attrs: type , arch ]\n> [ r , %r , r ; logic_reg , * ] \\t%0, %1, %2\n> - [ rk , r , ; logic_imm , * ] \\t%0, %1, %2\n> + [ rk , ^r , ; logic_imm , * ] \\t%0, %1, %2\n> + [ w , 0 , ; * , sve ] \\t%Z0., %Z0., #%2\n> [ w , w , w ; neon_logic , simd ] \\t%0., %1., %2.\n> }\n> )\n> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\n> index 1593a8fd04f91259295d0e393cbc7973daf7bf73..d24109b4fe6a867125b9474d34d616155bc36b3f 100644\n> --- a/gcc/config/aarch64/iterators.md\n> +++ b/gcc/config/aarch64/iterators.md\n> @@ -1435,6 +1435,19 @@ (define_mode_attr VCONQ [(V8QI \"V16QI\") (V16QI \"V16QI\")\n> \t\t\t (HI \"V8HI\") (QI \"V16QI\")\n> \t\t\t (SF \"V4SF\") (DF \"V2DF\")])\n> \n> +;; 128-bit container modes for the lower part of an SVE vector to the inner or\n> +;; neon source mode.\n> +(define_mode_attr VCONV [(SI \"VNx4SI\") (DI \"VNx2DI\")\n> +\t\t\t (V8QI \"VNx16QI\") (V16QI \"VNx16QI\")\n> +\t\t\t (V4HI \"VNx8HI\") (V8HI \"VNx8HI\")\n> +\t\t\t (V2SI \"VNx4SI\") (V4SI \"VNx4SI\")\n> +\t\t\t (V2DI \"VNx2DI\")])\n> +(define_mode_attr vconv [(SI \"vnx4si\") (DI \"vnx2di\")\n> +\t\t\t (V8QI \"vnx16qi\") (V16QI \"vnx16qi\")\n> +\t\t\t (V4HI \"vnx8hi\") (V8HI \"vnx8hi\")\n> +\t\t\t (V2SI \"vnx4si\") (V4SI \"vnx4si\")\n> +\t\t\t (V2DI \"vnx2di\")])\n> +\n> ;; Half modes of all vector modes.\n> (define_mode_attr VHALF [(V8QI \"V4QI\") (V16QI \"V8QI\")\n> \t\t\t (V4HI \"V2HI\") (V8HI \"V4HI\")\n\nThese attributes arne't needed any more (at least, not by this patch).\nOK for trunk with those removed.\n\nThanks,\nRichard\n\n> diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md\n> index 01de47439744acb3708c645b98eaa607294a1f1f..a73724a7fc05636d4c0643a291f40f2609564778 100644\n> --- a/gcc/config/aarch64/predicates.md\n> +++ b/gcc/config/aarch64/predicates.md\n> @@ -871,6 +871,11 @@ (define_predicate \"aarch64_sve_logical_operand\"\n> (ior (match_operand 0 \"register_operand\")\n> (match_operand 0 \"aarch64_sve_logical_immediate\")))\n> \n> +(define_predicate \"aarch64_orr_imm_sve_advsimd\"\n> + (ior (match_operand 0 \"aarch64_reg_or_orr_imm\")\n> + (and (match_test \"TARGET_SVE\")\n> +\t (match_operand 0 \"aarch64_sve_logical_operand\"))))\n> +\n> (define_predicate \"aarch64_sve_gather_offset_b\"\n> (ior (match_operand 0 \"register_operand\")\n> (match_operand 0 \"aarch64_sve_gather_immediate_b\")))\n> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\n> index 0c7664e6de77a497682952653ffd417453854d52..a8b27199ff83d0eebadfc7dcf03f94e1229d76b8 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_1.c\n> @@ -6,7 +6,7 @@\n> \n> /*\n> ** t1:\n> -**\torr\tv[0-9]+.2s, #128, lsl #24\n> +**\torr\tz[0-9]+.s, z[0-9]+.s, #-2147483648\n> **\tret\n> */\n> float32x2_t t1 (float32x2_t a)\n> @@ -16,7 +16,7 @@ float32x2_t t1 (float32x2_t a)\n> \n> /*\n> ** t2:\n> -**\torr\tv[0-9]+.4s, #128, lsl #24\n> +**\torr\tz[0-9]+.s, z[0-9]+.s, #-2147483648\n> **\tret\n> */\n> float32x4_t t2 (float32x4_t a)\n> @@ -26,9 +26,7 @@ float32x4_t t2 (float32x4_t a)\n> \n> /*\n> ** t3:\n> -**\tadrp\tx0, .LC[0-9]+\n> -**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n> -**\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n> +**\torr\tz[0-9]+.d, z[0-9]+.d, #-9223372036854775808\n> **\tret\n> */\n> float64x2_t t3 (float64x2_t a)\n> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> index a60cd31b9294af2dac69eed1c93f899bd5c78fca..19a7695e605bc8aced486a9c450d1cdc6be4691a 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n> @@ -7,8 +7,7 @@\n> \n> /*\n> ** f1:\n> -**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n> -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> +**\torr\tz0.s, z0.s, #-2147483648\n> **\tret\n> */\n> float32_t f1 (float32_t a)\n> @@ -18,9 +17,7 @@ float32_t f1 (float32_t a)\n> \n> /*\n> ** f2:\n> -**\tmov\tx0, -9223372036854775808\n> -**\tfmov\td[0-9]+, x0\n> -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> +**\torr\tz0.d, z0.d, #-9223372036854775808\n> **\tret\n> */\n> float64_t f2 (float64_t a)\n> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> index 21f2a8da2a5d44e3d01f6604ca7be87e3744d494..663d5fe17e091d128313b6b8b8dc918a01a96c4f 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n> @@ -6,9 +6,7 @@\n> \n> /*\n> ** negabs:\n> -**\tmov\tx0, -9223372036854775808\n> -**\tfmov\td[0-9]+, x0\n> -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> +**\torr\tz0.d, z0.d, #-9223372036854775808\n> **\tret\n> */\n> double negabs (double x)\n> @@ -22,8 +20,7 @@ double negabs (double x)\n> \n> /*\n> ** negabsf:\n> -**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n> -**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> +**\torr\tz0.s, z0.s, #-2147483648\n> **\tret\n> */\n> float negabsf (float x)","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=8.43.85.97; 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