[{"id":3188270,"web_url":"http://patchwork.ozlabs.org/comment/3188270/","msgid":"","list_archive_url":null,"date":"2023-09-27T01:35:05","subject":"Re: [PATCH]AArch64 Add movi for 0 moves for scalar types [PR109154]","submitter":{"id":4605,"url":"http://patchwork.ozlabs.org/api/people/4605/","name":"Ramana Radhakrishnan","email":"ramana.gcc@googlemail.com"},"content":"On Wed, Sep 27, 2023 at 1:51 AM Tamar Christina wrote:\n>\n> Hi All,\n>\n> Following the Neoverse N/V and Cortex-A optimization guides SIMD 0 immediates\n> should be created with a movi of 0.\n>\n> At the moment we generate an `fmov .., xzr` which is slower and requires a\n> GP -> FP transfer.\n>\n> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n>\n> Ok for master?\n>\n> Thanks,\n> Tamar\n>\n> gcc/ChangeLog:\n>\n> PR tree-optimization/109154\n> * config/aarch64/aarch64.md (*mov_aarch64, *movsi_aarch64,\n> *movdi_aarch64): Add new w -> Z case.\n> * config/aarch64/iterators.md (Vbtype): Add QI and HI.\n>\n> gcc/testsuite/ChangeLog:\n>\n> PR tree-optimization/109154\n> * gcc.target/aarch64/fneg-abs_2.c: Updated.\n> * gcc.target/aarch64/fneg-abs_4.c: Updated.\n>\n> --- inline copy of patch --\n> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\n> index b51f979dba12b726bff0c1109b75c6d2c7ae41ab..60c92213c75a2a4c18a6b59ae52fe45d1e872718 100644\n> --- a/gcc/config/aarch64/aarch64.md\n> +++ b/gcc/config/aarch64/aarch64.md\n> @@ -1232,6 +1232,7 @@ (define_insn \"*mov_aarch64\"\n> \"(register_operand (operands[0], mode)\n> || aarch64_reg_or_zero (operands[1], mode))\"\n> {@ [cons: =0, 1; attrs: type, arch]\n> + [w, Z ; neon_move , simd ] movi\\t%0., #0\n> [r, r ; mov_reg , * ] mov\\t%w0, %w1\n> [r, M ; mov_imm , * ] mov\\t%w0, %1\n> [w, D; neon_move , simd ] << aarch64_output_scalar_simd_mov_immediate (operands[1], mode);\n> @@ -1289,6 +1290,7 @@ (define_insn_and_split \"*movsi_aarch64\"\n> \"(register_operand (operands[0], SImode)\n> || aarch64_reg_or_zero (operands[1], SImode))\"\n> {@ [cons: =0, 1; attrs: type, arch, length]\n> + [w , Z ; neon_move, simd, 4] movi\\t%0.2d, #0\n> [r k, r ; mov_reg , * , 4] mov\\t%w0, %w1\n> [r , k ; mov_reg , * , 4] ^\n> [r , M ; mov_imm , * , 4] mov\\t%w0, %1\n> @@ -1322,6 +1324,7 @@ (define_insn_and_split \"*movdi_aarch64\"\n> \"(register_operand (operands[0], DImode)\n> || aarch64_reg_or_zero (operands[1], DImode))\"\n> {@ [cons: =0, 1; attrs: type, arch, length]\n> + [w, Z ; neon_move, simd, 4] movi\\t%0.2d, #0\n> [r, r ; mov_reg , * , 4] mov\\t%x0, %x1\n> [k, r ; mov_reg , * , 4] mov\\t%0, %x1\n> [r, k ; mov_reg , * , 4] mov\\t%x0, %1\n> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\n> index 2451d8c2cd8e2da6ac8339eed9bc975cf203fa4c..d17becc37e230684beaee3c69e2a0f0ce612eda5 100644\n> --- a/gcc/config/aarch64/iterators.md\n> +++ b/gcc/config/aarch64/iterators.md\n> @@ -1297,6 +1297,7 @@ (define_mode_attr Vbtype [(V8QI \"8b\") (V16QI \"16b\")\n> (V4SF \"16b\") (V2DF \"16b\")\n> (DI \"8b\") (DF \"8b\")\n> (SI \"8b\") (SF \"8b\")\n> + (QI \"8b\") (HI \"8b\")\n> (V4BF \"8b\") (V8BF \"16b\")])\n>\n> ;; Advanced SIMD vector structure to element modes.\n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> index fb14ec3e2210e0feeff80f2410d777d3046a9f78..5e253d3059cfc9b93bd0865e6eaed1231eba19bd 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> @@ -20,7 +20,7 @@ float32_t f1 (float32_t a)\n>\n> /*\n> ** f2:\n> -** fmov d[0-9]+, xzr\n> +** movi v[0-9]+.2d, #0\n> ** fneg v[0-9]+.2d, v[0-9]+.2d\n> ** orr v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> ** ret\n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> index 4ea0105f6c0a9756070bcc60d34f142f53d8242c..c86fe3e032c9e5176467841ce1a679ea47bbd531 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> @@ -8,7 +8,7 @@\n>\n> /*\n> ** negabs:\n> -** fmov d[0-9]+, xzr\n> +** movi v31.2d, #0\n> ** fneg v[0-9]+.2d, v[0-9]+.2d\n> ** orr v[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> ** ret\n>\n>\n>\n>\n\n\nLGTM. I just clocked that the simd attribute is disabled with\n-mgeneral-regs-only which allows for this to work .. Neat.\n\n\n I cannot approve.\n\nRamana\n> --","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=googlemail.com header.i=@googlemail.com\n header.a=rsa-sha256 header.s=20230601 header.b=eUpGjQhT;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org;\n envelope-from=gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)","sourceware.org; dmarc=pass (p=quarantine dis=none)\n header.from=googlemail.com","sourceware.org; spf=pass smtp.mailfrom=googlemail.com"],"Received":["from server2.sourceware.org (server2.sourceware.org\n [IPv6:2620:52:3:1:0:246e:9693:128c])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4RwK1c07WPz1ypJ\n\tfor ; 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Tue, 26 Sep\n 2023 18:35:16 -0700 (PDT)","MIME-Version":"1.0","References":"","In-Reply-To":"","From":"Ramana Radhakrishnan ","Date":"Wed, 27 Sep 2023 02:35:05 +0100","Message-ID":"\n ","Subject":"Re: [PATCH]AArch64 Add movi for 0 moves for scalar types [PR109154]","To":"Tamar Christina ","Cc":"gcc-patches@gcc.gnu.org, nd@arm.com, Richard.Earnshaw@arm.com,\n Marcus.Shawcroft@arm.com, Kyrylo.Tkachov@arm.com, richard.sandiford@arm.com","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-Spam-Status":"No, score=-9.0 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0,\n KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org"}},{"id":3188405,"web_url":"http://patchwork.ozlabs.org/comment/3188405/","msgid":"","list_archive_url":null,"date":"2023-09-27T06:41:15","subject":"Re: [PATCH]AArch64 Add movi for 0 moves for scalar types [PR109154]","submitter":{"id":64746,"url":"http://patchwork.ozlabs.org/api/people/64746/","name":"Richard Sandiford","email":"richard.sandiford@arm.com"},"content":"Tamar Christina writes:\n> Hi All,\n>\n> Following the Neoverse N/V and Cortex-A optimization guides SIMD 0 immediates\n> should be created with a movi of 0.\n>\n> At the moment we generate an `fmov .., xzr` which is slower and requires a\n> GP -> FP transfer.\n>\n> Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n>\n> Ok for master?\n>\n> Thanks,\n> Tamar\n>\n> gcc/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* config/aarch64/aarch64.md (*mov_aarch64, *movsi_aarch64,\n> \t*movdi_aarch64): Add new w -> Z case.\n> \t* config/aarch64/iterators.md (Vbtype): Add QI and HI.\n>\n> gcc/testsuite/ChangeLog:\n>\n> \tPR tree-optimization/109154\n> \t* gcc.target/aarch64/fneg-abs_2.c: Updated.\n> \t* gcc.target/aarch64/fneg-abs_4.c: Updated.\n\nOK, thanks.\n\nRichard\n\n> --- inline copy of patch -- \n> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\n> index b51f979dba12b726bff0c1109b75c6d2c7ae41ab..60c92213c75a2a4c18a6b59ae52fe45d1e872718 100644\n> --- a/gcc/config/aarch64/aarch64.md\n> +++ b/gcc/config/aarch64/aarch64.md\n> @@ -1232,6 +1232,7 @@ (define_insn \"*mov_aarch64\"\n> \"(register_operand (operands[0], mode)\n> || aarch64_reg_or_zero (operands[1], mode))\"\n> {@ [cons: =0, 1; attrs: type, arch]\n> + [w, Z ; neon_move , simd ] movi\\t%0., #0\n> [r, r ; mov_reg , * ] mov\\t%w0, %w1\n> [r, M ; mov_imm , * ] mov\\t%w0, %1\n> [w, D; neon_move , simd ] << aarch64_output_scalar_simd_mov_immediate (operands[1], mode);\n> @@ -1289,6 +1290,7 @@ (define_insn_and_split \"*movsi_aarch64\"\n> \"(register_operand (operands[0], SImode)\n> || aarch64_reg_or_zero (operands[1], SImode))\"\n> {@ [cons: =0, 1; attrs: type, arch, length]\n> + [w , Z ; neon_move, simd, 4] movi\\t%0.2d, #0\n> [r k, r ; mov_reg , * , 4] mov\\t%w0, %w1\n> [r , k ; mov_reg , * , 4] ^\n> [r , M ; mov_imm , * , 4] mov\\t%w0, %1\n> @@ -1322,6 +1324,7 @@ (define_insn_and_split \"*movdi_aarch64\"\n> \"(register_operand (operands[0], DImode)\n> || aarch64_reg_or_zero (operands[1], DImode))\"\n> {@ [cons: =0, 1; attrs: type, arch, length]\n> + [w, Z ; neon_move, simd, 4] movi\\t%0.2d, #0\n> [r, r ; mov_reg , * , 4] mov\\t%x0, %x1\n> [k, r ; mov_reg , * , 4] mov\\t%0, %x1\n> [r, k ; mov_reg , * , 4] mov\\t%x0, %1\n> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\n> index 2451d8c2cd8e2da6ac8339eed9bc975cf203fa4c..d17becc37e230684beaee3c69e2a0f0ce612eda5 100644\n> --- a/gcc/config/aarch64/iterators.md\n> +++ b/gcc/config/aarch64/iterators.md\n> @@ -1297,6 +1297,7 @@ (define_mode_attr Vbtype [(V8QI \"8b\") (V16QI \"16b\")\n> \t\t\t (V4SF \"16b\") (V2DF \"16b\")\n> \t\t\t (DI \"8b\") (DF \"8b\")\n> \t\t\t (SI \"8b\") (SF \"8b\")\n> +\t\t\t (QI \"8b\") (HI \"8b\")\n> \t\t\t (V4BF \"8b\") (V8BF \"16b\")])\n> \n> ;; Advanced SIMD vector structure to element modes.\n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> index fb14ec3e2210e0feeff80f2410d777d3046a9f78..5e253d3059cfc9b93bd0865e6eaed1231eba19bd 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n> @@ -20,7 +20,7 @@ float32_t f1 (float32_t a)\n> \n> /*\n> ** f2:\n> -**\tfmov\td[0-9]+, xzr\n> +**\tmovi\tv[0-9]+.2d, #0\n> **\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n> **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> **\tret\n> diff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> index 4ea0105f6c0a9756070bcc60d34f142f53d8242c..c86fe3e032c9e5176467841ce1a679ea47bbd531 100644\n> --- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> +++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n> @@ -8,7 +8,7 @@\n> \n> /*\n> ** negabs:\n> -**\tfmov\td[0-9]+, xzr\n> +**\tmovi\tv31.2d, #0\n> **\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n> **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n> **\tret","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","gcc-patches@gcc.gnu.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","gcc-patches@gcc.gnu.org"],"Authentication-Results":["legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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