[{"id":3188954,"web_url":"http://patchwork.ozlabs.org/comment/3188954/","msgid":"<97eb2099-23c2-4921-89ac-9523226ad221@linaro.org>","list_archive_url":null,"date":"2023-09-27T16:03:02","subject":"Re: [PATCH] uapi/auxvec: Define AT_HWCAP3 and AT_HWCAP4 aux vector,\n entries","submitter":{"id":66065,"url":"http://patchwork.ozlabs.org/api/people/66065/","name":"Adhemerval Zanella Netto","email":"adhemerval.zanella@linaro.org"},"content":"On 26/09/23 19:02, Peter Bergner wrote:\n> The powerpc toolchain keeps a copy of the HWCAP bit masks in our TCB for fast\n> access by our __builtin_cpu_supports built-in function. The TCB space for\n> the HWCAP entries - which are created in pairs - is an ABI extension, so\n> waiting to create the space for HWCAP3 and HWCAP4 until we need them is\n> problematical, given distro unwillingness to apply ABI modifying patches\n> to distro point releases. Define AT_HWCAP3 and AT_HWCAP4 in the generic\n> uapi header so they can be used in GLIBC to reserve space in the powerpc\n> TCB for their future use.\n\nThis is different than previously exported auxv, where each AT_* constant\nwould have a auxv entry. On glibc it would require changing _dl_parse_auxv\nto iterate over the auxv_values to find AT_HWCAP3/AT_HWCAP4 (not ideal, \nbut doable).\n\nWouldn't be better to always export it on fs/binfmt_elf.c, along with all \nthe machinery to setup it (ELF_HWCAP3, etc), along with proper documentation?\n\n> \n> I scanned both the Linux and GLIBC source codes looking for unused AT_*\n> values and 29 and 30 did not seem to be used, so they are what I went\n> with. If anyone sees a problem with using those specific values, I'm\n> amenable to using other values, just let me know what would be better.\n> \n> Peter\n> \n> \n> Signed-off-by: Peter Bergner \n> ---\n> include/uapi/linux/auxvec.h | 2 ++\n> 1 file changed, 2 insertions(+)\n> \n> diff --git a/include/uapi/linux/auxvec.h b/include/uapi/linux/auxvec.h\n> index 6991c4b8ab18..cc61cb9b3e9a 100644\n> --- a/include/uapi/linux/auxvec.h\n> +++ b/include/uapi/linux/auxvec.h\n> @@ -32,6 +32,8 @@\n> #define AT_HWCAP2 26\t/* extension of AT_HWCAP */\n> #define AT_RSEQ_FEATURE_SIZE\t27\t/* rseq supported feature size */\n> #define AT_RSEQ_ALIGN\t\t28\t/* rseq allocation alignment */\n> +#define AT_HWCAP3 29\t/* extension of AT_HWCAP */\n> +#define AT_HWCAP4 30\t/* extension of AT_HWCAP */\n> \n> #define AT_EXECFN 31\t/* filename of program */\n>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=TwHaln8g;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE,\n SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org"}},{"id":3191482,"web_url":"http://patchwork.ozlabs.org/comment/3191482/","msgid":"<891957ad-453e-4c68-9c5a-7a979667543d@linux.ibm.com>","list_archive_url":null,"date":"2023-10-02T21:19:10","subject":"Re: [PATCH] uapi/auxvec: Define AT_HWCAP3 and AT_HWCAP4 aux vector,\n entries","submitter":{"id":74386,"url":"http://patchwork.ozlabs.org/api/people/74386/","name":"Peter Bergner","email":"bergner@linux.ibm.com"},"content":"Hi Adhemerval, sorry for the delay in replying, I was a little under the\nweather last week.\n\n\nOn 9/27/23 11:03 AM, Adhemerval Zanella Netto wrote:\n> On 26/09/23 19:02, Peter Bergner wrote:\n>> The powerpc toolchain keeps a copy of the HWCAP bit masks in our TCB for fast\n>> access by our __builtin_cpu_supports built-in function. The TCB space for\n>> the HWCAP entries - which are created in pairs - is an ABI extension, so\n>> waiting to create the space for HWCAP3 and HWCAP4 until we need them is\n>> problematical, given distro unwillingness to apply ABI modifying patches\n>> to distro point releases. Define AT_HWCAP3 and AT_HWCAP4 in the generic\n>> uapi header so they can be used in GLIBC to reserve space in the powerpc\n>> TCB for their future use.\n> \n> This is different than previously exported auxv, where each AT_* constant\n> would have a auxv entry. On glibc it would require changing _dl_parse_auxv\n> to iterate over the auxv_values to find AT_HWCAP3/AT_HWCAP4 (not ideal, \n> but doable).\n\nWhen you say different, do you mean because all AUXVs exported by the kernel\n*will* have an AT_HWCAP and AT_HWCAP2 entry and AT_HWCAP3/AT_HWCAP4 won't?\nI don't think that's a problem for either kernel or glibc side of things.\nI'm not even sure there is a guarantee that every AT_* value *must* be\npresent in the exported AUXV.\n\nThe new AT_HWCAP3/AT_HWCAP4 defines are less than AT_MINSIGSTKSZ, so they\ndon't affect the size of _dl_parse_auxv's auxv_values array size and the\nAT_HWCAP3 and AT_HWCAP4 entries in auxv_values[] are already initialized\nto zero today. Additionally, the loop in _dl_parse_auxv already parses\nthe entire AUXV, so there is no extra work for it to do, unless and until\nAT_HWCAP3 and AT_HWCAP4 start being exported by the kernel. Really, the\nonly extra work _dl_parse_auxv would need to do, is add two new stores:\n\n GLRO(dl_hwcap3) = auxv_values[AT_HWCAP3];\n GLRO(dl_hwcap4) = auxv_values[AT_HWCAP4];\n\n\n\n> Wouldn't be better to always export it on fs/binfmt_elf.c, along with all \n> the machinery to setup it (ELF_HWCAP3, etc), along with proper documentation?\n\nYou mean modify the kernel now to export AT_HWCAP3 and AT_HWCAP4 as zero\nmasks? Is that really necessary since we don't need or have any features\ndefined in them yet? GLIBC's _dl_parse_auxv doesn't really need them to\nbe exported either, since in the absence of the entries, it will just end\nup using zero masks for dl_hwcap3 and dl_hwcap4, so everything is copacetic\neven without any kernel changes.\n\nAs I mentioned, our real problem is the lead time for getting changes that\naffect the user ABI into a distro release, and ppc's copy/cache of the HWCAP\nmasks is an ABI change. If we wait to add this support until when we\nactually have a need for HWCAP3, then we won't have any support until\nthe next major distro release. However, if we can add this support now,\nwhich I don't think is an onerous change on glibc's part, then we can\nstart using it immediately when Linux starts exporting them.\n\n\nPeter","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=GlQP1vi4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=8.43.85.97; helo=server2.sourceware.org;\n envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n dmarc=none (p=none dis=none) header.from=linux.ibm.com","sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com"],"Received":["from server2.sourceware.org (ip-8-43-85-97.sourceware.org\n [8.43.85.97])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Rzv3n0DTFz1ypx\n\tfor ; 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charset=UTF-8","Content-Transfer-Encoding":"7bit","X-TM-AS-GCONF":"00","X-Proofpoint-ORIG-GUID":"iwOxse1LKTd-mzgBl_gDQrG6AZJZ2pID","X-Proofpoint-GUID":"oXttozJ5pEGhCYcwaRXxZAKaOtCxpjge","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-02_15,2023-10-02_01,2023-05-22_02","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n mlxscore=0 spamscore=0\n phishscore=0 mlxlogscore=716 malwarescore=0 clxscore=1011 suspectscore=0\n priorityscore=1501 impostorscore=0 adultscore=0 lowpriorityscore=0\n bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2309180000 definitions=main-2310020163","X-Spam-Status":"No, score=-3.1 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_EF, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,\n SPF_HELO_NONE,\n SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org"}},{"id":3191983,"web_url":"http://patchwork.ozlabs.org/comment/3191983/","msgid":"<057366c2-ee65-441d-b2ac-f40e1d94b44e@linaro.org>","list_archive_url":null,"date":"2023-10-03T14:08:11","subject":"Re: [PATCH] uapi/auxvec: Define AT_HWCAP3 and AT_HWCAP4 aux vector,\n entries","submitter":{"id":66065,"url":"http://patchwork.ozlabs.org/api/people/66065/","name":"Adhemerval Zanella Netto","email":"adhemerval.zanella@linaro.org"},"content":"On 02/10/23 18:19, Peter Bergner wrote:\n> Hi Adhemerval, sorry for the delay in replying, I was a little under the\n> weather last week.\n> \n> \n> On 9/27/23 11:03 AM, Adhemerval Zanella Netto wrote:\n>> On 26/09/23 19:02, Peter Bergner wrote:\n>>> The powerpc toolchain keeps a copy of the HWCAP bit masks in our TCB for fast\n>>> access by our __builtin_cpu_supports built-in function. The TCB space for\n>>> the HWCAP entries - which are created in pairs - is an ABI extension, so\n>>> waiting to create the space for HWCAP3 and HWCAP4 until we need them is\n>>> problematical, given distro unwillingness to apply ABI modifying patches\n>>> to distro point releases. Define AT_HWCAP3 and AT_HWCAP4 in the generic\n>>> uapi header so they can be used in GLIBC to reserve space in the powerpc\n>>> TCB for their future use.\n>>\n>> This is different than previously exported auxv, where each AT_* constant\n>> would have a auxv entry. On glibc it would require changing _dl_parse_auxv\n>> to iterate over the auxv_values to find AT_HWCAP3/AT_HWCAP4 (not ideal, \n>> but doable).\n> \n> When you say different, do you mean because all AUXVs exported by the kernel\n> *will* have an AT_HWCAP and AT_HWCAP2 entry and AT_HWCAP3/AT_HWCAP4 won't?\n> I don't think that's a problem for either kernel or glibc side of things.\n> I'm not even sure there is a guarantee that every AT_* value *must* be\n> present in the exported AUXV.\n> \n> The new AT_HWCAP3/AT_HWCAP4 defines are less than AT_MINSIGSTKSZ, so they\n> don't affect the size of _dl_parse_auxv's auxv_values array size and the\n> AT_HWCAP3 and AT_HWCAP4 entries in auxv_values[] are already initialized\n> to zero today. Additionally, the loop in _dl_parse_auxv already parses\n> the entire AUXV, so there is no extra work for it to do, unless and until\n> AT_HWCAP3 and AT_HWCAP4 start being exported by the kernel. Really, the\n> only extra work _dl_parse_auxv would need to do, is add two new stores:\n> \n> GLRO(dl_hwcap3) = auxv_values[AT_HWCAP3];\n> GLRO(dl_hwcap4) = auxv_values[AT_HWCAP4];\n> \n\nIndeed you are right, I wrong assumed that the AT_HWCAP3/AT_HWCAP4 would\nbe higher than AT_MINSIGSTKSZ. \n\n> \n> \n>> Wouldn't be better to always export it on fs/binfmt_elf.c, along with all \n>> the machinery to setup it (ELF_HWCAP3, etc), along with proper documentation?\n> \n> You mean modify the kernel now to export AT_HWCAP3 and AT_HWCAP4 as zero\n> masks? Is that really necessary since we don't need or have any features\n> defined in them yet? GLIBC's _dl_parse_auxv doesn't really need them to\n> be exported either, since in the absence of the entries, it will just end\n> up using zero masks for dl_hwcap3 and dl_hwcap4, so everything is copacetic\n> even without any kernel changes.\n> \n> As I mentioned, our real problem is the lead time for getting changes that\n> affect the user ABI into a distro release, and ppc's copy/cache of the HWCAP\n> masks is an ABI change. If we wait to add this support until when we\n> actually have a need for HWCAP3, then we won't have any support until\n> the next major distro release. However, if we can add this support now,\n> which I don't think is an onerous change on glibc's part, then we can\n> start using it immediately when Linux starts exporting them.\n\nWhat it is not clear to me is what kind of ABI boundary you are trying to\npreemptively add support here. The TCB ABI for __builtin_cpu_supports is\nuserland only, so if your intention is just to allow gcc to work on older\nglibcs, it should be a matter to just reserve the space on tcbhead_t. Once\nkernel actually provides AT_HWCAP3/AT_HWCAP4, backporting should be\nstraightforward.\n\nIf your intention is to also add support on glibc, it makes more sense to\nalready reserve it. For __builtin_cpu_supports it should work, although\nfor glibc itself some backporting would be required (to correctly showing\nthe bits with LD_SHOW_AUXV).","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ZSW3VKyf;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=8.43.85.97; helo=server2.sourceware.org;\n envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=linaro.org","sourceware.org; spf=pass smtp.mailfrom=linaro.org"],"Received":["from server2.sourceware.org (server2.sourceware.org [8.43.85.97])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4S0KRc3w6Wz1yng\n\tfor ; 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charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-5.2 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,\n SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org"}},{"id":3192280,"web_url":"http://patchwork.ozlabs.org/comment/3192280/","msgid":"","list_archive_url":null,"date":"2023-10-03T22:12:40","subject":"Re: [PATCH] uapi/auxvec: Define AT_HWCAP3 and AT_HWCAP4 aux vector,\n entries","submitter":{"id":74386,"url":"http://patchwork.ozlabs.org/api/people/74386/","name":"Peter Bergner","email":"bergner@linux.ibm.com"},"content":"On 10/3/23 9:08 AM, Adhemerval Zanella Netto wrote:\n> What it is not clear to me is what kind of ABI boundary you are trying to\n> preemptively add support here. The TCB ABI for __builtin_cpu_supports is\n> userland only, so if your intention is just to allow gcc to work on older\n> glibcs, it should be a matter to just reserve the space on tcbhead_t.\n\nYes, extending tcbhead_t to contain the slots for hwcap3 and hwcap4 are the\nABI extensions we are interested in, and not something that can be backported\ninto a distro point release. Yes, we don't strictly need the AT_HWCAP3 and\nAT_HWCAP4 kernel defines to reserve (and clear) that space in glibc, but....\n\n\n\n> If your intention is to also add support on glibc, it makes more sense to\n> already reserve it. For __builtin_cpu_supports it should work, although\n> for glibc itself some backporting would be required (to correctly showing\n> the bits with LD_SHOW_AUXV).\n\nOur intention is to also add the glibc support too once we have the\nAT_HWCAP3 and AT_HWCAP4 kernel macros defined. 1) Once the defines are\nthere, adding the support should be pretty straight forward, so why wait?\nAnd 2) part of the glibc and compiler support introduces a new symbol\nthat is exported by glibc and referenced by the compilers to ensure the\ncompilers *never* access the hwcap* fields in the TCB unless the glibc\nsupports them. See the symbol __parse_hwcap_and_convert_at_platform used\nfor HWCAP/HWCAP2. We'll need a similar one for HWCAP3/HWCAP4 and I'm\ndoubtful whether the distros will allow the backport of a patch that\nintroduces a new exported symbol from glibc in a distro point release.\n\n\nPeter","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=HCirntTj;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org;\n envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n dmarc=none (p=none dis=none) header.from=linux.ibm.com","sourceware.org; spf=pass smtp.mailfrom=linux.ibm.com"],"Received":["from server2.sourceware.org (server2.sourceware.org\n [IPv6:2620:52:3:1:0:246e:9693:128c])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4S0XBw0286z1yng\n\tfor ; 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charset=UTF-8","Content-Transfer-Encoding":"7bit","X-TM-AS-GCONF":"00","X-Proofpoint-ORIG-GUID":"QBv_-BKDIIjD6Ym1H1PQ2Xb6PFMUBl_I","X-Proofpoint-GUID":"Tb47txw3PRJ5F1pBchWwQ_ZiRAOEEZ1e","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-03_18,2023-10-02_01,2023-05-22_02","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n bulkscore=0\n priorityscore=1501 lowpriorityscore=0 phishscore=0 clxscore=1015\n malwarescore=0 mlxscore=0 adultscore=0 suspectscore=0 mlxlogscore=598\n spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx\n scancount=1 engine=8.12.0-2309180000 definitions=main-2310030167","X-Spam-Status":"No, score=-3.1 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_EF, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL,\n SPF_HELO_NONE,\n SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org"}},{"id":3192630,"web_url":"http://patchwork.ozlabs.org/comment/3192630/","msgid":"","list_archive_url":null,"date":"2023-10-04T11:02:28","subject":"Re: [PATCH] uapi/auxvec: Define AT_HWCAP3 and AT_HWCAP4 aux vector,\n entries","submitter":{"id":66065,"url":"http://patchwork.ozlabs.org/api/people/66065/","name":"Adhemerval Zanella Netto","email":"adhemerval.zanella@linaro.org"},"content":"On 03/10/23 19:12, Peter Bergner wrote:\n> On 10/3/23 9:08 AM, Adhemerval Zanella Netto wrote:\n>> What it is not clear to me is what kind of ABI boundary you are trying to\n>> preemptively add support here. The TCB ABI for __builtin_cpu_supports is\n>> userland only, so if your intention is just to allow gcc to work on older\n>> glibcs, it should be a matter to just reserve the space on tcbhead_t.\n> \n> Yes, extending tcbhead_t to contain the slots for hwcap3 and hwcap4 are the\n> ABI extensions we are interested in, and not something that can be backported\n> into a distro point release. Yes, we don't strictly need the AT_HWCAP3 and\n> AT_HWCAP4 kernel defines to reserve (and clear) that space in glibc, but....\n> \n> \n> \n>> If your intention is to also add support on glibc, it makes more sense to\n>> already reserve it. For __builtin_cpu_supports it should work, although\n>> for glibc itself some backporting would be required (to correctly showing\n>> the bits with LD_SHOW_AUXV).\n> \n> Our intention is to also add the glibc support too once we have the\n> AT_HWCAP3 and AT_HWCAP4 kernel macros defined. 1) Once the defines are\n> there, adding the support should be pretty straight forward, so why wait?\n> And 2) part of the glibc and compiler support introduces a new symbol\n> that is exported by glibc and referenced by the compilers to ensure the\n> compilers *never* access the hwcap* fields in the TCB unless the glibc\n> supports them. See the symbol __parse_hwcap_and_convert_at_platform used\n> for HWCAP/HWCAP2. We'll need a similar one for HWCAP3/HWCAP4 and I'm\n> doubtful whether the distros will allow the backport of a patch that\n> introduces a new exported symbol from glibc in a distro point release.\n\nAlright, I makes more sense it now. And indeed backporting a __parse_hwcap\nfor HWCAP3/HWCAP4 will be frown upon.","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=yAtHmAo4;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; helo=server2.sourceware.org;\n envelope-from=libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)","sourceware.org;\n dmarc=pass (p=none dis=none) header.from=linaro.org","sourceware.org; spf=pass smtp.mailfrom=linaro.org"],"Received":["from server2.sourceware.org (server2.sourceware.org\n [IPv6:2620:52:3:1:0:246e:9693:128c])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4S0sHM0DRzz1yph\n\tfor ; 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charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-5.2 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,\n SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"libc-alpha@sourceware.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Libc-alpha mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"libc-alpha-bounces+incoming=patchwork.ozlabs.org@sourceware.org"}},{"id":3201089,"web_url":"http://patchwork.ozlabs.org/comment/3201089/","msgid":"<4294d9ae-3f5e-4f81-b586-2c134d21896a@linux.ibm.com>","list_archive_url":null,"date":"2023-10-17T23:14:53","subject":"[PING][PATCH] uapi/auxvec: Define AT_HWCAP3 and AT_HWCAP4 aux vector,\n entries","submitter":{"id":74386,"url":"http://patchwork.ozlabs.org/api/people/74386/","name":"Peter Bergner","email":"bergner@linux.ibm.com"},"content":"CCing linux-kernel for more exposure.\n\nPING. I'm waiting on a reply from anyone on the kernel side of things\nto see whether they have an issue with reserving values for AT_HWCAP3\nand AT_HWCAP4. \n\nI'll note reviews from the GLIBC camp did not have an issue with the below patch.\n\nThanks.\n\nPeter\n\n\nOn 9/26/23 5:02 PM, Peter Bergner wrote:\n> The powerpc toolchain keeps a copy of the HWCAP bit masks in our TCB for fast\n> access by our __builtin_cpu_supports built-in function. The TCB space for\n> the HWCAP entries - which are created in pairs - is an ABI extension, so\n> waiting to create the space for HWCAP3 and HWCAP4 until we need them is\n> problematical, given distro unwillingness to apply ABI modifying patches\n> to distro point releases. Define AT_HWCAP3 and AT_HWCAP4 in the generic\n> uapi header so they can be used in GLIBC to reserve space in the powerpc\n> TCB for their future use.\n> \n> I scanned both the Linux and GLIBC source codes looking for unused AT_*\n> values and 29 and 30 did not seem to be used, so they are what I went\n> with. If anyone sees a problem with using those specific values, I'm\n> amenable to using other values, just let me know what would be better.\n> \n> Peter\n> \n> \n> Signed-off-by: Peter Bergner \n> ---\n> include/uapi/linux/auxvec.h | 2 ++\n> 1 file changed, 2 insertions(+)\n> \n> diff --git a/include/uapi/linux/auxvec.h b/include/uapi/linux/auxvec.h\n> index 6991c4b8ab18..cc61cb9b3e9a 100644\n> --- a/include/uapi/linux/auxvec.h\n> +++ b/include/uapi/linux/auxvec.h\n> @@ -32,6 +32,8 @@\n> #define AT_HWCAP2 26\t/* extension of AT_HWCAP */\n> #define AT_RSEQ_FEATURE_SIZE\t27\t/* rseq supported feature size */\n> #define AT_RSEQ_ALIGN\t\t28\t/* rseq allocation alignment */\n> +#define AT_HWCAP3 29\t/* extension of AT_HWCAP */\n> +#define AT_HWCAP4 30\t/* extension of AT_HWCAP */\n> \n> #define AT_EXECFN 31\t/* filename of program */\n>","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=NxGosvxC;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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I'm waiting on a reply from anyone on the kernel side of things\n> to see whether they have an issue with reserving values for AT_HWCAP3\n> and AT_HWCAP4. \n> \n> I'll note reviews from the GLIBC camp did not have an issue with the below patch.\n\nfwiw, aarch64 is quickly filling up AT_HWCAP2 so this will be\nuseful for arm64 too eventually, but we are not in a hurry.\n\n> > +#define AT_HWCAP3 29\t/* extension of AT_HWCAP */\n> > +#define AT_HWCAP4 30\t/* extension of AT_HWCAP */","headers":{"Return-Path":"","X-Original-To":["incoming@patchwork.ozlabs.org","libc-alpha@sourceware.org"],"Delivered-To":["patchwork-incoming@legolas.ozlabs.org","libc-alpha@sourceware.org"],"Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com\n header.b=jVWTV1dg;\n\tdkim=pass (1024-bit key) header.d=armh.onmicrosoft.com\n header.i=@armh.onmicrosoft.com header.a=rsa-sha256\n header.s=selector2-armh-onmicrosoft-com header.b=jVWTV1dg;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=8.43.85.97; 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