[{"id":2911009,"web_url":"http://patchwork.ozlabs.org/comment/2911009/","msgid":"<6c02f8ef-8aea-8f80-590d-343f67a96f8d@infradead.org>","list_archive_url":null,"date":"2022-06-10T16:34:46","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":18663,"url":"http://patchwork.ozlabs.org/api/people/18663/","name":"Randy Dunlap","email":"rdunlap@infradead.org"},"content":"Hi--\n\nOn 6/10/22 01:17, Serge Semin wrote:\n> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\n> index bb45a9c00514..95e0e022b5bb 100644\n> --- a/drivers/ata/Kconfig\n> +++ b/drivers/ata/Kconfig\n> @@ -176,6 +176,16 @@ config AHCI_DM816\n> \n> \t If unsure, say N.\n> \n> +config AHCI_DWC\n> +\ttristate \"Synopsys DWC AHCI SATA support\"\n> +\tselect SATA_HOST\n> +\tdefault SATA_AHCI_PLATFORM\n\nI don't think this needs to default to SATA_AHCI_PLATFORM.\nIt might build a driver that isn't needed.\nAnd it's incompatible with \"If unsure, say N.\"\n\n> +\thelp\n> +\t This option enables support for the Synopsys DWC AHCI SATA\n> +\t controller implementation.\n> +\n> +\t If unsure, say N.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=infradead.org header.i=@infradead.org header.a=rsa-sha256\n header.s=casper.20170209 header.b=XZqQoZt7;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; 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charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-5.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED,\n SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED\n autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2911120,"web_url":"http://patchwork.ozlabs.org/comment/2911120/","msgid":"<20220610215850.ju76kxjquwef6kd3@mobilestation>","list_archive_url":null,"date":"2022-06-10T21:58:50","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":70038,"url":"http://patchwork.ozlabs.org/api/people/70038/","name":"Serge Semin","email":"fancer.lancer@gmail.com"},"content":"On Fri, Jun 10, 2022 at 09:34:46AM -0700, Randy Dunlap wrote:\n> Hi--\n\nHi Randy\n\n> \n> On 6/10/22 01:17, Serge Semin wrote:\n> > diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\n> > index bb45a9c00514..95e0e022b5bb 100644\n> > --- a/drivers/ata/Kconfig\n> > +++ b/drivers/ata/Kconfig\n> > @@ -176,6 +176,16 @@ config AHCI_DM816\n> > \n> > \t If unsure, say N.\n> > \n> > +config AHCI_DWC\n> > +\ttristate \"Synopsys DWC AHCI SATA support\"\n> > +\tselect SATA_HOST\n> > +\tdefault SATA_AHCI_PLATFORM\n> \n\n> I don't think this needs to default to SATA_AHCI_PLATFORM.\n> It might build a driver that isn't needed.\n> And it's incompatible with \"If unsure, say N.\"\n\nBasically you are right, but this particular setting is connected with\nthe modification I've done in the drivers/ata/ahci_platform.c driver\nin the framework of this commit. I've moved the \"snps,spear-ahci\" and\n\"snps,dwc-ahci\" compatible devices support to the new driver. Thus\nshould I omit the SATA_AHCI_PLATFORM dependency their default kernel\nconfigs will lack the corresponding controllers support. If it's not a\nproblem and we can rely on the kernel build system ability to ask\nwhether the new config needs to be set/cleared, then I would be very\nhappy to drop the default setting. What do you think?\n\n-Sergey\n\n> \n> > +\thelp\n> > +\t This option enables support for the Synopsys DWC AHCI SATA\n> > +\t controller implementation.\n> > +\n> > +\t If unsure, say N.\n> \n> -- \n> ~Randy","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20210112 header.b=iC/k1aIY;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-ide-owner@vger.kernel.org; receiver=)"],"Received":["from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 4LKZc919dBz9s1l\n\tfor ; Sat, 11 Jun 2022 07:59:04 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S241580AbiFJV7B (ORCPT );\n Fri, 10 Jun 2022 17:59:01 -0400","from lindbergh.monkeyblade.net ([23.128.96.19]:59992 \"EHLO\n lindbergh.monkeyblade.net\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n with ESMTP id S243046AbiFJV7A (ORCPT\n ); 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<6c02f8ef-8aea-8f80-590d-343f67a96f8d@infradead.org>","X-Spam-Status":"No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,\n RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE\n autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2911135,"web_url":"http://patchwork.ozlabs.org/comment/2911135/","msgid":"<73716f9f-892c-41c5-89f0-64a1985438aa@infradead.org>","list_archive_url":null,"date":"2022-06-10T23:34:13","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":18663,"url":"http://patchwork.ozlabs.org/api/people/18663/","name":"Randy Dunlap","email":"rdunlap@infradead.org"},"content":"Hi Serge,\n\nOn 6/10/22 14:58, Serge Semin wrote:\n> On Fri, Jun 10, 2022 at 09:34:46AM -0700, Randy Dunlap wrote:\n>> Hi--\n> \n> Hi Randy\n> \n>>\n>> On 6/10/22 01:17, Serge Semin wrote:\n>>> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\n>>> index bb45a9c00514..95e0e022b5bb 100644\n>>> --- a/drivers/ata/Kconfig\n>>> +++ b/drivers/ata/Kconfig\n>>> @@ -176,6 +176,16 @@ config AHCI_DM816\n>>> \n>>> \t If unsure, say N.\n>>> \n>>> +config AHCI_DWC\n>>> +\ttristate \"Synopsys DWC AHCI SATA support\"\n>>> +\tselect SATA_HOST\n>>> +\tdefault SATA_AHCI_PLATFORM\n>>\n> \n>> I don't think this needs to default to SATA_AHCI_PLATFORM.\n>> It might build a driver that isn't needed.\n>> And it's incompatible with \"If unsure, say N.\"\n> \n> Basically you are right, but this particular setting is connected with\n> the modification I've done in the drivers/ata/ahci_platform.c driver\n> in the framework of this commit. I've moved the \"snps,spear-ahci\" and\n> \"snps,dwc-ahci\" compatible devices support to the new driver. Thus\n> should I omit the SATA_AHCI_PLATFORM dependency their default kernel\n> configs will lack the corresponding controllers support. If it's not a\n> problem and we can rely on the kernel build system ability to ask\n> whether the new config needs to be set/cleared, then I would be very\n> happy to drop the default setting. What do you think?\n\nI'd prefer to try it like that.\nIf it becomes a problem, we can go back to this v4 patch.\n\n>>> +\thelp\n>>> +\t This option enables support for the Synopsys DWC AHCI SATA\n>>> +\t controller implementation.\n>>> +\n>>> +\t If unsure, say N.\n>>\n>> -- \n>> ~Randy\n\nThanks.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=infradead.org header.i=@infradead.org header.a=rsa-sha256\n header.s=desiato.20200630 header.b=nuJn2mIT;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-ide-owner@vger.kernel.org; receiver=)"],"Received":["from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 4LKckl3jJGz9s09\n\tfor ; Sat, 11 Jun 2022 09:34:55 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S1348949AbiFJXew (ORCPT );\n Fri, 10 Jun 2022 19:34:52 -0400","from lindbergh.monkeyblade.net ([23.128.96.19]:53020 \"EHLO\n lindbergh.monkeyblade.net\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n with ESMTP id S1348626AbiFJXev (ORCPT\n ); Fri, 10 Jun 2022 19:34:51 -0400","from desiato.infradead.org (desiato.infradead.org\n [IPv6:2001:8b0:10b:1:d65d:64ff:fe57:4e05])\n by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49A3B289A0F;\n Fri, 10 Jun 2022 16:34:49 -0700 (PDT)","from [2601:1c0:6280:3f0::aa0b]\n by desiato.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux))\n id 1nzo8z-006o8u-Ah; Fri, 10 Jun 2022 23:34:22 +0000"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n d=infradead.org; s=desiato.20200630;\n h=Content-Transfer-Encoding:Content-Type\n :In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date:Message-ID:\n Sender:Reply-To:Content-ID:Content-Description;\n bh=wwxScsKhI2Gxa0NDbcdKj4SXbyaU0oPRufyab5cqNns=;\n b=nuJn2mITolgztxc1OtuuW5b9bc\n r5eVsM0cGFiQ7FM5BTPwGzLl9Pp3DFHI58cH8UxPCGTndt6CshU5UHisXKsaVEngEOaPVpo7h+BxS\n UJmrxs1R+8E6yrjHWWrTVVXDJKtQQ0m2TEbV1iDc+odJpRwEEhpxjHEXYDqOyUJ6nFcx7CLs0BrB9\n 7AaDgHFro5h92kf5lJWVgeC6HRdUTMygXdIiJkfP7lGpGjM87xpZCPdHBY11BKx14Z5yJ4LdSESpe\n Qcb5YPUfSBK8Q62VLQcLXtM8OuWbasTBO6ICOEu0qFRq9zKd89Y3IwR0PMSjB+md5tJFGzVyFrtp2\n eDRuT8OA==;","Message-ID":"<73716f9f-892c-41c5-89f0-64a1985438aa@infradead.org>","Date":"Fri, 10 Jun 2022 16:34:13 -0700","MIME-Version":"1.0","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101\n Thunderbird/91.9.1","Subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","Content-Language":"en-US","To":"Serge Semin ","Cc":"Serge Semin ,\n Damien Le Moal ,\n Hans de Goede ,\n Jens Axboe , Hannes Reinecke ,\n Alexey Malahov ,\n Pavel Parkhomenko ,\n Rob Herring , linux-ide@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org","References":"<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>\n <20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru>\n <6c02f8ef-8aea-8f80-590d-343f67a96f8d@infradead.org>\n <20220610215850.ju76kxjquwef6kd3@mobilestation>","From":"Randy Dunlap ","In-Reply-To":"<20220610215850.ju76kxjquwef6kd3@mobilestation>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-5.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED,\n SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED\n autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2912318,"web_url":"http://patchwork.ozlabs.org/comment/2912318/","msgid":"<52c9ca79-769f-4426-db94-7aad05a68258@opensource.wdc.com>","list_archive_url":null,"date":"2022-06-14T08:53:39","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":82259,"url":"http://patchwork.ozlabs.org/api/people/82259/","name":"Damien Le Moal","email":"damien.lemoal@opensource.wdc.com"},"content":"On 6/10/22 17:17, Serge Semin wrote:\n> Synopsys AHCI SATA controller can work pretty under with the generic\n> AHCI-platform driver control. But there are vendor-specific peculiarities\n> which can tune the device performance up and which may need to be fixed up\n> for proper device functioning. In addition some DWC AHCI-based controllers\n> may require small platform-specific fixups, so adding them in the generic\n> AHCI driver would have ruined the code simplicity. Shortly speaking in\n> order to keep the generic AHCI-platform code clean and have DWC AHCI\n> SATA-specific features supported we suggest to add a dedicated DWC AHCI\n> SATA device driver. Aside with the standard AHCI-platform resources\n> getting, enabling/disabling and the controller registration the new driver\n> performs the next actions.\n> \n> First of all there is a way to verify whether the HBA/ports capabilities\n> activated in OF are correct. Almost all features availability is reflected\n> in the vendor-specific parameters registers. So the DWC AHCI driver does\n> the capabilities sanity check based on the corresponding fields state.\n> \n> Secondly if either the Command Completion Coalescing or the Device Sleep\n> feature is enabled the DWC AHCI-specific internal 1ms timer must be fixed\n> in accordance with the application clock signal frequency. In particular\n> the timer value must be set to be Fapp * 1000. Normally the SoC designers\n> pre-configure the TIMER1MS register to contain a correct value by default.\n> But the platforms can support the application clock rate change. If that\n> happens the 1ms timer value must be accordingly updated otherwise the\n> dependent features won't work as expected. In the DWC AHCI driver we\n> suggest to rely on the \"aclk\" reference clock rate to set the timer\n> interval up. That clock source is supposed to be the AHCI SATA application\n> clock in accordance with the DT bindings.\n> \n> Finally DWC AHCI SATA controller AXI/AHB bus DMA-engine can be tuned up to\n> transfer up to 1024 * FIFO words at a time by setting the Tx/Rx\n> transaction size in the DMA control register. The maximum value depends on\n> the DMA data bus and AXI/AHB bus maximum burst length. In most of the\n> cases it's better to set the maximum possible value to reach the best AHCI\n> SATA controller performance. But sometimes in order to improve the system\n> interconnect responsiveness, transferring in smaller data chunks may be\n> more preferable. For such cases and for the case when the default value\n> doesn't provide the best DMA bus performance we suggest to use the new\n> HBA-port specific DT-properties \"snps,{tx,rx}-ts-max\" to tune the DMA\n> transactions size up.\n> \n> After all the settings denoted above are handled the DWC AHCI SATA driver\n> proceeds further with the standard AHCI-platform host initializations.\n> \n> Note since DWC AHCI controller is now have a dedicated driver we can\n> discard the corresponding compatible string from the ahci-platform.c\n> module. The same concerns \"snps,spear-ahci\" compatible string, which is\n> also based on the DWC AHCI IP-core.\n> \n> Signed-off-by: Serge Semin \n> Reviewed-by: Hannes Reinecke \n> \n> ---\n> \n> Note there are three more AHCI SATA drivers which have been created for\n> the devices based on the DWC AHCI SATA IP-core. It's AHCI SunXi, St and\n> iMX drivers. Mostly they don't support the features implemented in this\n> driver. So hopefully sometime in future they can be converted to be based\n> on the generic DWC AHCI SATA driver and just perform some\n> subvendor-specific setups in their own LLDD (glue) driver code. But for\n> now let's leave the generic DWC AHCI SATA code as is. Hopefully the new\n> DWC AHCI-based device drivers will try at least to re-use a part of the\n> DWC AHCI driver methods if not being able to be integrated in the generic\n> DWC driver code.\n> \n> Changelog v2:\n> - Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_'.\n> (@Damien)\n> \n> Changelog v4:\n> - Replace GPLv2 with just GPL license which are the same in the framework\n> of the MODULE_LICENSE() macro.\n> ---\n> drivers/ata/Kconfig | 10 +\n> drivers/ata/Makefile | 1 +\n> drivers/ata/ahci_dwc.c | 395 ++++++++++++++++++++++++++++++++++++\n> drivers/ata/ahci_platform.c | 2 -\n> 4 files changed, 406 insertions(+), 2 deletions(-)\n> create mode 100644 drivers/ata/ahci_dwc.c\n> \n> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\n> index bb45a9c00514..95e0e022b5bb 100644\n> --- a/drivers/ata/Kconfig\n> +++ b/drivers/ata/Kconfig\n> @@ -176,6 +176,16 @@ config AHCI_DM816\n> \n> \t If unsure, say N.\n> \n> +config AHCI_DWC\n> +\ttristate \"Synopsys DWC AHCI SATA support\"\n> +\tselect SATA_HOST\n> +\tdefault SATA_AHCI_PLATFORM\n> +\thelp\n> +\t This option enables support for the Synopsys DWC AHCI SATA\n> +\t controller implementation.\n> +\n> +\t If unsure, say N.\n> +\n> config AHCI_ST\n> \ttristate \"ST AHCI SATA support\"\n> \tdepends on ARCH_STI\n> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile\n> index b8aebfb14e82..34623365d9a6 100644\n> --- a/drivers/ata/Makefile\n> +++ b/drivers/ata/Makefile\n> @@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_BRCM)\t\t+= ahci_brcm.o libahci.o libahci_platform.o\n> obj-$(CONFIG_AHCI_CEVA)\t\t+= ahci_ceva.o libahci.o libahci_platform.o\n> obj-$(CONFIG_AHCI_DA850)\t+= ahci_da850.o libahci.o libahci_platform.o\n> obj-$(CONFIG_AHCI_DM816)\t+= ahci_dm816.o libahci.o libahci_platform.o\n> +obj-$(CONFIG_AHCI_DWC)\t\t+= ahci_dwc.o libahci.o libahci_platform.o\n> obj-$(CONFIG_AHCI_IMX)\t\t+= ahci_imx.o libahci.o libahci_platform.o\n> obj-$(CONFIG_AHCI_MTK)\t\t+= ahci_mtk.o libahci.o libahci_platform.o\n> obj-$(CONFIG_AHCI_MVEBU)\t+= ahci_mvebu.o libahci.o libahci_platform.o\n> diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c\n> new file mode 100644\n> index 000000000000..8c2510933a31\n> --- /dev/null\n> +++ b/drivers/ata/ahci_dwc.c\n> @@ -0,0 +1,395 @@\n> +// SPDX-License-Identifier: GPL-2.0-or-later\n> +/*\n> + * DWC AHCI SATA Platform driver\n> + *\n> + * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#include \"ahci.h\"\n> +\n> +#define DRV_NAME \"ahci-dwc\"\n> +\n> +#define AHCI_DWC_FBS_PMPN_MAX\t\t15\n> +\n> +/* DWC AHCI SATA controller specific registers */\n> +#define AHCI_DWC_HOST_OOBR\t\t0xbc\n> +#define AHCI_DWC_HOST_OOB_WE\t\tBIT(31)\n> +#define AHCI_DWC_HOST_CWMIN_MASK\tGENMASK(30, 24)\n> +#define AHCI_DWC_HOST_CWMAX_MASK\tGENMASK(23, 16)\n> +#define AHCI_DWC_HOST_CIMIN_MASK\tGENMASK(15, 8)\n> +#define AHCI_DWC_HOST_CIMAX_MASK\tGENMASK(7, 0)\n> +\n> +#define AHCI_DWC_HOST_GPCR\t\t0xd0\n> +#define AHCI_DWC_HOST_GPSR\t\t0xd4\n> +\n> +#define AHCI_DWC_HOST_TIMER1MS\t\t0xe0\n> +#define AHCI_DWC_HOST_TIMV_MASK\t\tGENMASK(19, 0)\n> +\n> +#define AHCI_DWC_HOST_GPARAM1R\t\t0xe8\n> +#define AHCI_DWC_HOST_ALIGN_M\t\tBIT(31)\n> +#define AHCI_DWC_HOST_RX_BUFFER\t\tBIT(30)\n> +#define AHCI_DWC_HOST_PHY_DATA_MASK\tGENMASK(29, 28)\n> +#define AHCI_DWC_HOST_PHY_RST\t\tBIT(27)\n> +#define AHCI_DWC_HOST_PHY_CTRL_MASK\tGENMASK(26, 21)\n> +#define AHCI_DWC_HOST_PHY_STAT_MASK\tGENMASK(20, 15)\n> +#define AHCI_DWC_HOST_LATCH_M\t\tBIT(14)\n> +#define AHCI_DWC_HOST_PHY_TYPE_MASK\tGENMASK(13, 11)\n> +#define AHCI_DWC_HOST_RET_ERR\t\tBIT(10)\n> +#define AHCI_DWC_HOST_AHB_ENDIAN_MASK\tGENMASK(9, 8)\n> +#define AHCI_DWC_HOST_S_HADDR\t\tBIT(7)\n> +#define AHCI_DWC_HOST_M_HADDR\t\tBIT(6)\n> +#define AHCI_DWC_HOST_S_HDATA_MASK\tGENMASK(5, 3)\n> +#define AHCI_DWC_HOST_M_HDATA_MASK\tGENMASK(2, 0)\n> +\n> +#define AHCI_DWC_HOST_GPARAM2R\t\t0xec\n> +#define AHCI_DWC_HOST_FBS_MEM_S\t\tBIT(19)\n> +#define AHCI_DWC_HOST_FBS_PMPN_MASK\tGENMASK(17, 16)\n> +#define AHCI_DWC_HOST_FBS_SUP\t\tBIT(15)\n> +#define AHCI_DWC_HOST_DEV_CP\t\tBIT(14)\n> +#define AHCI_DWC_HOST_DEV_MP\t\tBIT(13)\n> +#define AHCI_DWC_HOST_ENCODE_M\t\tBIT(12)\n> +#define AHCI_DWC_HOST_RXOOB_CLK_M\tBIT(11)\n> +#define AHCI_DWC_HOST_RXOOB_M\t\tBIT(10)\n> +#define AHCI_DWC_HOST_TXOOB_M\t\tBIT(9)\n> +#define AHCI_DWC_HOST_RXOOB_M\t\tBIT(10)\n> +#define AHCI_DWC_HOST_RXOOB_CLK_MASK\tGENMASK(8, 0)\n> +\n> +#define AHCI_DWC_HOST_PPARAMR\t\t0xf0\n> +#define AHCI_DWC_HOST_TX_MEM_M\t\tBIT(11)\n> +#define AHCI_DWC_HOST_TX_MEM_S\t\tBIT(10)\n> +#define AHCI_DWC_HOST_RX_MEM_M\t\tBIT(9)\n> +#define AHCI_DWC_HOST_RX_MEM_S\t\tBIT(8)\n> +#define AHCI_DWC_HOST_TXFIFO_DEPTH\tGENMASK(7, 4)\n> +#define AHCI_DWC_HOST_RXFIFO_DEPTH\tGENMASK(3, 0)\n> +\n> +#define AHCI_DWC_HOST_TESTR\t\t0xf4\n> +#define AHCI_DWC_HOST_PSEL_MASK\t\tGENMASK(18, 16)\n> +#define AHCI_DWC_HOST_TEST_IF\t\tBIT(0)\n> +\n> +#define AHCI_DWC_HOST_VERSIONR\t\t0xf8\n> +#define AHCI_DWC_HOST_IDR\t\t0xfc\n> +\n> +#define AHCI_DWC_PORT_DMACR\t\t0x70\n> +#define AHCI_DWC_PORT_RXABL_MASK\tGENMASK(15, 12)\n> +#define AHCI_DWC_PORT_TXABL_MASK\tGENMASK(11, 8)\n> +#define AHCI_DWC_PORT_RXTS_MASK\t\tGENMASK(7, 4)\n> +#define AHCI_DWC_PORT_TXTS_MASK\t\tGENMASK(3, 0)\n> +#define AHCI_DWC_PORT_PHYCR\t\t0x74\n> +#define AHCI_DWC_PORT_PHYSR\t\t0x78\n> +\n> +struct ahci_dwc_host_priv {\n> +\tstruct platform_device *pdev;\n> +\n> +\tu32 timv;\n> +\tu32 dmacr[AHCI_MAX_PORTS];\n> +};\n> +\n> +static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev)\n> +{\n> +\tstruct ahci_dwc_host_priv *dpriv;\n> +\tstruct ahci_host_priv *hpriv;\n> +\n> +\tdpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL);\n> +\tif (!dpriv)\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\n> +\tdpriv->pdev = pdev;\n> +\n> +\thpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);\n> +\tif (IS_ERR(hpriv))\n> +\t\treturn hpriv;\n> +\n> +\thpriv->plat_data = (void *)dpriv;\n> +\n> +\treturn hpriv;\n> +}\n> +\n> +static void ahci_dwc_check_cap(struct ahci_host_priv *hpriv)\n> +{\n> +\tunsigned long port_map = hpriv->saved_port_map | hpriv->mask_port_map;\n> +\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n> +\tbool dev_mp, dev_cp, fbs_sup;\n> +\tunsigned int fbs_pmp;\n> +\tu32 param;\n> +\tint i;\n> +\n> +\tparam = readl(hpriv->mmio + AHCI_DWC_HOST_GPARAM2R);\n> +\tdev_mp = !!(param & AHCI_DWC_HOST_DEV_MP);\n> +\tdev_cp = !!(param & AHCI_DWC_HOST_DEV_CP);\n> +\tfbs_sup = !!(param & AHCI_DWC_HOST_FBS_SUP);\n> +\tfbs_pmp = 5 * FIELD_GET(AHCI_DWC_HOST_FBS_PMPN_MASK, param);\n> +\n> +\tif (!dev_mp && hpriv->saved_cap & HOST_CAP_MPS) {\n> +\t\tdev_warn(&dpriv->pdev->dev, \"MPS is unsupported\\n\");\n> +\t\thpriv->saved_cap &= ~HOST_CAP_MPS;\n> +\t}\n> +\n> +\n> +\tif (fbs_sup && fbs_pmp < AHCI_DWC_FBS_PMPN_MAX) {\n> +\t\tdev_warn(&dpriv->pdev->dev, \"PMPn is limited up to %u ports\\n\",\n> +\t\t\t fbs_pmp);\n> +\t}\n> +\n> +\tfor_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {\n> +\t\tif (!dev_mp && hpriv->saved_port_cap[i] & PORT_CMD_MPSP) {\n> +\t\t\tdev_warn(&dpriv->pdev->dev, \"MPS incapable port %d\\n\", i);\n> +\t\t\thpriv->saved_port_cap[i] &= ~PORT_CMD_MPSP;\n> +\t\t}\n> +\n> +\t\tif (!dev_cp && hpriv->saved_port_cap[i] & PORT_CMD_CPD) {\n> +\t\t\tdev_warn(&dpriv->pdev->dev, \"CPD incapable port %d\\n\", i);\n> +\t\t\thpriv->saved_port_cap[i] &= ~PORT_CMD_CPD;\n> +\t\t}\n> +\n> +\t\tif (!fbs_sup && hpriv->saved_port_cap[i] & PORT_CMD_FBSCP) {\n> +\t\t\tdev_warn(&dpriv->pdev->dev, \"FBS incapable port %d\\n\", i);\n> +\t\t\thpriv->saved_port_cap[i] &= ~PORT_CMD_FBSCP;\n> +\t\t}\n> +\t}\n> +}\n> +\n> +static void ahci_dwc_init_timer(struct ahci_host_priv *hpriv)\n> +{\n> +\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n> +\tunsigned long rate;\n> +\tstruct clk *aclk;\n> +\tu32 cap, cap2;\n> +\n> +\t/* 1ms tick is generated only for the CCC or DevSleep features */\n> +\tcap = readl(hpriv->mmio + HOST_CAP);\n> +\tcap2 = readl(hpriv->mmio + HOST_CAP2);\n> +\tif (!(cap & HOST_CAP_CCC) && !(cap2 & HOST_CAP2_SDS))\n> +\t\treturn;\n> +\n> +\t/*\n> +\t * Tick is generated based on the AXI/AHB application clocks signal\n> +\t * so we need to be sure in the clock we are going to use.\n> +\t */\n> +\taclk = ahci_platform_find_clk(hpriv, \"aclk\");\n> +\tif (!aclk)\n> +\t\treturn;\n> +\n> +\t/* 1ms timer interval is set as TIMV = AMBA_FREQ[MHZ] * 1000 */\n> +\tdpriv->timv = readl(hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);\n> +\tdpriv->timv = FIELD_GET(AHCI_DWC_HOST_TIMV_MASK, dpriv->timv);\n> +\trate = clk_get_rate(aclk) / 1000UL;\n> +\tif (rate == dpriv->timv)\n> +\t\treturn;\n> +\n> +\tdev_info(&dpriv->pdev->dev, \"Update CCC/DevSlp timer for Fapp %lu MHz\\n\",\n> +\t\t rate / 1000UL);\n> +\tdpriv->timv = FIELD_PREP(AHCI_DWC_HOST_TIMV_MASK, rate);\n> +\twritel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);\n> +}\n> +\n> +static int ahci_dwc_init_dmacr(struct ahci_host_priv *hpriv)\n> +{\n> +\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n> +\tstruct device_node *child;\n> +\tvoid __iomem *port_mmio;\n> +\tu32 port, dmacr, ts;\n> +\n> +\t/*\n> +\t * Update the DMA Tx/Rx transaction sizes in accordance with the\n> +\t * platform setup. Note values exceeding maximal or minimal limits will\n> +\t * be automatically clamped. Also note the register isn't affected by\n> +\t * the HBA global reset so we can freely initialize it once until the\n> +\t * next system reset.\n> +\t */\n> +\tfor_each_child_of_node(dpriv->pdev->dev.of_node, child) {\n> +\t\tif (!of_device_is_available(child))\n> +\t\t\tcontinue;\n> +\n> +\t\tif (of_property_read_u32(child, \"reg\", &port)) {\n> +\t\t\tof_node_put(child);\n> +\t\t\treturn -EINVAL;\n> +\t\t}\n> +\n> +\t\tport_mmio = __ahci_port_base(hpriv, port);\n> +\t\tdmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR);\n> +\n> +\t\tif (!of_property_read_u32(child, \"snps,tx-ts-max\", &ts)) {\n> +\t\t\tts = ilog2(ts);\n> +\t\t\tdmacr &= ~AHCI_DWC_PORT_TXTS_MASK;\n> +\t\t\tdmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts);\n> +\t\t}\n> +\n> +\t\tif (!of_property_read_u32(child, \"snps,rx-ts-max\", &ts)) {\n> +\t\t\tts = ilog2(ts);\n> +\t\t\tdmacr &= ~AHCI_DWC_PORT_RXTS_MASK;\n> +\t\t\tdmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts);\n> +\t\t}\n> +\n> +\t\twritel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR);\n> +\t\tdpriv->dmacr[port] = dmacr;\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int ahci_dwc_init_host(struct ahci_host_priv *hpriv)\n> +{\n> +\tint rc;\n> +\n> +\trc = ahci_platform_enable_resources(hpriv);\n> +\tif (rc)\n> +\t\treturn rc;\n> +\n> +\tahci_dwc_check_cap(hpriv);\n> +\n> +\tahci_dwc_init_timer(hpriv);\n> +\n> +\trc = ahci_dwc_init_dmacr(hpriv);\n> +\tif (rc)\n> +\t\tgoto err_disable_resources;\n> +\n> +\treturn 0;\n> +\n> +err_disable_resources:\n> +\tahci_platform_disable_resources(hpriv);\n> +\n> +\treturn rc;\n> +}\n> +\n> +static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv)\n> +{\n> +\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n> +\tunsigned long port_map = hpriv->port_map;\n> +\tvoid __iomem *port_mmio;\n> +\tint i, rc;\n> +\n> +\trc = ahci_platform_enable_resources(hpriv);\n> +\tif (rc)\n> +\t\treturn rc;\n> +\n> +\twritel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);\n> +\n> +\tfor_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {\n> +\t\tport_mmio = __ahci_port_base(hpriv, i);\n> +\t\twritel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR);\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> +static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv)\n> +{\n> +\tahci_platform_disable_resources(hpriv);\n> +}\n> +\n> +static void ahci_dwc_stop_host(struct ata_host *host)\n> +{\n> +\tstruct ahci_host_priv *hpriv = host->private_data;\n> +\n> +\tahci_dwc_clear_host(hpriv);\n> +}\n> +\n> +static struct ata_port_operations ahci_dwc_port_ops = {\n> +\t.inherits\t= &ahci_platform_ops,\n> +\t.host_stop\t= ahci_dwc_stop_host,\n> +};\n> +\n> +static const struct ata_port_info ahci_dwc_port_info = {\n> +\t.flags\t\t= AHCI_FLAG_COMMON,\n> +\t.pio_mask\t= ATA_PIO4,\n> +\t.udma_mask\t= ATA_UDMA6,\n> +\t.port_ops\t= &ahci_dwc_port_ops,\n> +};\n> +\n> +static struct scsi_host_template ahci_dwc_scsi_info = {\n> +\tAHCI_SHT(DRV_NAME),\n> +};\n> +\n> +static int ahci_dwc_probe(struct platform_device *pdev)\n> +{\n> +\tstruct ahci_host_priv *hpriv;\n> +\tint rc;\n> +\n> +\thpriv = ahci_dwc_get_resources(pdev);\n> +\tif (IS_ERR(hpriv))\n> +\t\treturn PTR_ERR(hpriv);\n> +\n> +\trc = ahci_dwc_init_host(hpriv);\n> +\tif (rc)\n> +\t\treturn rc;\n> +\n> +\trc = ahci_platform_init_host(pdev, hpriv, &ahci_dwc_port_info,\n> +\t\t\t\t &ahci_dwc_scsi_info);\n> +\tif (rc)\n> +\t\tgoto err_clear_host;\n> +\n> +\treturn 0;\n> +\n> +err_clear_host:\n> +\tahci_dwc_clear_host(hpriv);\n> +\n> +\treturn rc;\n> +}\n> +\n> +#ifdef CONFIG_PM_SLEEP\n> +static int ahci_dwc_suspend(struct device *dev)\n> +{\n> +\tstruct ata_host *host = dev_get_drvdata(dev);\n> +\tstruct ahci_host_priv *hpriv = host->private_data;\n> +\tint rc;\n> +\n> +\trc = ahci_platform_suspend_host(dev);\n> +\tif (rc)\n> +\t\treturn rc;\n> +\n> +\tahci_dwc_clear_host(hpriv);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int ahci_dwc_resume(struct device *dev)\n> +{\n> +\tstruct ata_host *host = dev_get_drvdata(dev);\n> +\tstruct ahci_host_priv *hpriv = host->private_data;\n> +\tint rc;\n> +\n> +\trc = ahci_dwc_reinit_host(hpriv);\n> +\tif (rc)\n> +\t\treturn rc;\n> +\n> +\treturn ahci_platform_resume_host(dev);\n> +}\n> +#endif\n> +\n> +static SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend, ahci_dwc_resume);\n\ninclude/linux/pm.h says:\n/* Deprecated. Use DEFINE_SIMPLE_DEV_PM_OPS() instead. */\n\n> +\n> +static const struct of_device_id ahci_dwc_of_match[] = {\n> +\t{ .compatible = \"snps,dwc-ahci\", },\n> +\t{ .compatible = \"snps,spear-ahci\", },\n> +\t{},\n> +};\n> +MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);\n> +\n> +static struct platform_driver ahci_dwc_driver = {\n> +\t.probe = ahci_dwc_probe,\n> +\t.remove = ata_platform_remove_one,\n> +\t.shutdown = ahci_platform_shutdown,\n> +\t.driver = {\n> +\t\t.name = DRV_NAME,\n> +\t\t.of_match_table = ahci_dwc_of_match,\n> +\t\t.pm = &ahci_dwc_pm_ops,\n> +\t},\n> +};\n> +module_platform_driver(ahci_dwc_driver);\n> +\n> +MODULE_DESCRIPTION(\"DWC AHCI SATA platform driver\");\n> +MODULE_AUTHOR(\"Serge Semin \");\n> +MODULE_LICENSE(\"GPL\");\n\nMODULE_LICENSE(\"GPL v2\");\n\nTo match the file header SPDX.\n\n> diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c\n> index 9b56490ecbc3..8f5572a9f8f1 100644\n> --- a/drivers/ata/ahci_platform.c\n> +++ b/drivers/ata/ahci_platform.c\n> @@ -80,9 +80,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,\n> static const struct of_device_id ahci_of_match[] = {\n> \t{ .compatible = \"generic-ahci\", },\n> \t/* Keep the following compatibles for device tree compatibility */\n> -\t{ .compatible = \"snps,spear-ahci\", },\n> \t{ .compatible = \"ibm,476gtr-ahci\", },\n> -\t{ .compatible = \"snps,dwc-ahci\", },\n> \t{ .compatible = \"hisilicon,hisi-ahci\", },\n> \t{ .compatible = \"cavium,octeon-7130-ahci\", },\n> \t{ /* sentinel */ }","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256\n header.s=dkim.wdc.com header.b=lJ5lo5CW;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=opensource.wdc.com header.i=@opensource.wdc.com\n header.a=rsa-sha256 header.s=dkim header.b=diin7gxN;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; 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Linux x86_64; rv:91.0) Gecko/20100101\n Thunderbird/91.10.0","Subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","Content-Language":"en-US","To":"Serge Semin ,\n Hans de Goede ,\n Jens Axboe , Hannes Reinecke ,\n Serge Semin ","Cc":"Alexey Malahov ,\n Pavel Parkhomenko ,\n Rob Herring , linux-ide@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org","References":"<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>\n <20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru>","From":"Damien Le Moal ","Organization":"Western Digital Research","In-Reply-To":"<20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-5.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED,\n SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable\n autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2913753,"web_url":"http://patchwork.ozlabs.org/comment/2913753/","msgid":"<20220615213029.3upsmasnnhigqozm@mobilestation>","list_archive_url":null,"date":"2022-06-15T21:30:29","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":70038,"url":"http://patchwork.ozlabs.org/api/people/70038/","name":"Serge Semin","email":"fancer.lancer@gmail.com"},"content":"On Fri, Jun 10, 2022 at 04:34:13PM -0700, Randy Dunlap wrote:\n> Hi Serge,\n> \n> On 6/10/22 14:58, Serge Semin wrote:\n> > On Fri, Jun 10, 2022 at 09:34:46AM -0700, Randy Dunlap wrote:\n> >> Hi--\n> > \n> > Hi Randy\n> > \n> >>\n> >> On 6/10/22 01:17, Serge Semin wrote:\n> >>> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\n> >>> index bb45a9c00514..95e0e022b5bb 100644\n> >>> --- a/drivers/ata/Kconfig\n> >>> +++ b/drivers/ata/Kconfig\n> >>> @@ -176,6 +176,16 @@ config AHCI_DM816\n> >>> \n> >>> \t If unsure, say N.\n> >>> \n> >>> +config AHCI_DWC\n> >>> +\ttristate \"Synopsys DWC AHCI SATA support\"\n> >>> +\tselect SATA_HOST\n> >>> +\tdefault SATA_AHCI_PLATFORM\n> >>\n> > \n> >> I don't think this needs to default to SATA_AHCI_PLATFORM.\n> >> It might build a driver that isn't needed.\n> >> And it's incompatible with \"If unsure, say N.\"\n> > \n> > Basically you are right, but this particular setting is connected with\n> > the modification I've done in the drivers/ata/ahci_platform.c driver\n> > in the framework of this commit. I've moved the \"snps,spear-ahci\" and\n> > \"snps,dwc-ahci\" compatible devices support to the new driver. Thus\n> > should I omit the SATA_AHCI_PLATFORM dependency their default kernel\n> > configs will lack the corresponding controllers support. If it's not a\n> > problem and we can rely on the kernel build system ability to ask\n> > whether the new config needs to be set/cleared, then I would be very\n> > happy to drop the default setting. What do you think?\n> \n\n> I'd prefer to try it like that.\n> If it becomes a problem, we can go back to this v4 patch.\n\nAgreed then (seeing Damien is silent about your comment).\n\n-Sergey\n\n> \n> >>> +\thelp\n> >>> +\t This option enables support for the Synopsys DWC AHCI SATA\n> >>> +\t controller implementation.\n> >>> +\n> >>> +\t If unsure, say N.\n> >>\n> >> -- \n> >> ~Randy\n> \n> Thanks.\n> -- \n> ~Randy","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20210112 header.b=B0emyKDi;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-ide-owner@vger.kernel.org; receiver=)"],"Received":["from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 4LNdl50MDLz9sG0\n\tfor ; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<73716f9f-892c-41c5-89f0-64a1985438aa@infradead.org>","X-Spam-Status":"No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,\n RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE\n autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2913769,"web_url":"http://patchwork.ozlabs.org/comment/2913769/","msgid":"<20220615214802.ke6owp5cuv5l77hu@mobilestation>","list_archive_url":null,"date":"2022-06-15T21:48:02","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":70038,"url":"http://patchwork.ozlabs.org/api/people/70038/","name":"Serge Semin","email":"fancer.lancer@gmail.com"},"content":"On Tue, Jun 14, 2022 at 05:53:39PM +0900, Damien Le Moal wrote:\n> On 6/10/22 17:17, Serge Semin wrote:\n> > Synopsys AHCI SATA controller can work pretty under with the generic\n> > AHCI-platform driver control. But there are vendor-specific peculiarities\n> > which can tune the device performance up and which may need to be fixed up\n> > for proper device functioning. In addition some DWC AHCI-based controllers\n> > may require small platform-specific fixups, so adding them in the generic\n> > AHCI driver would have ruined the code simplicity. Shortly speaking in\n> > order to keep the generic AHCI-platform code clean and have DWC AHCI\n> > SATA-specific features supported we suggest to add a dedicated DWC AHCI\n> > SATA device driver. Aside with the standard AHCI-platform resources\n> > getting, enabling/disabling and the controller registration the new driver\n> > performs the next actions.\n> > \n> > First of all there is a way to verify whether the HBA/ports capabilities\n> > activated in OF are correct. Almost all features availability is reflected\n> > in the vendor-specific parameters registers. So the DWC AHCI driver does\n> > the capabilities sanity check based on the corresponding fields state.\n> > \n> > Secondly if either the Command Completion Coalescing or the Device Sleep\n> > feature is enabled the DWC AHCI-specific internal 1ms timer must be fixed\n> > in accordance with the application clock signal frequency. In particular\n> > the timer value must be set to be Fapp * 1000. Normally the SoC designers\n> > pre-configure the TIMER1MS register to contain a correct value by default.\n> > But the platforms can support the application clock rate change. If that\n> > happens the 1ms timer value must be accordingly updated otherwise the\n> > dependent features won't work as expected. In the DWC AHCI driver we\n> > suggest to rely on the \"aclk\" reference clock rate to set the timer\n> > interval up. That clock source is supposed to be the AHCI SATA application\n> > clock in accordance with the DT bindings.\n> > \n> > Finally DWC AHCI SATA controller AXI/AHB bus DMA-engine can be tuned up to\n> > transfer up to 1024 * FIFO words at a time by setting the Tx/Rx\n> > transaction size in the DMA control register. The maximum value depends on\n> > the DMA data bus and AXI/AHB bus maximum burst length. In most of the\n> > cases it's better to set the maximum possible value to reach the best AHCI\n> > SATA controller performance. But sometimes in order to improve the system\n> > interconnect responsiveness, transferring in smaller data chunks may be\n> > more preferable. For such cases and for the case when the default value\n> > doesn't provide the best DMA bus performance we suggest to use the new\n> > HBA-port specific DT-properties \"snps,{tx,rx}-ts-max\" to tune the DMA\n> > transactions size up.\n> > \n> > After all the settings denoted above are handled the DWC AHCI SATA driver\n> > proceeds further with the standard AHCI-platform host initializations.\n> > \n> > Note since DWC AHCI controller is now have a dedicated driver we can\n> > discard the corresponding compatible string from the ahci-platform.c\n> > module. The same concerns \"snps,spear-ahci\" compatible string, which is\n> > also based on the DWC AHCI IP-core.\n> > \n> > Signed-off-by: Serge Semin \n> > Reviewed-by: Hannes Reinecke \n> > \n> > ---\n> > \n> > Note there are three more AHCI SATA drivers which have been created for\n> > the devices based on the DWC AHCI SATA IP-core. It's AHCI SunXi, St and\n> > iMX drivers. Mostly they don't support the features implemented in this\n> > driver. So hopefully sometime in future they can be converted to be based\n> > on the generic DWC AHCI SATA driver and just perform some\n> > subvendor-specific setups in their own LLDD (glue) driver code. But for\n> > now let's leave the generic DWC AHCI SATA code as is. Hopefully the new\n> > DWC AHCI-based device drivers will try at least to re-use a part of the\n> > DWC AHCI driver methods if not being able to be integrated in the generic\n> > DWC driver code.\n> > \n> > Changelog v2:\n> > - Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_'.\n> > (@Damien)\n> > \n> > Changelog v4:\n> > - Replace GPLv2 with just GPL license which are the same in the framework\n> > of the MODULE_LICENSE() macro.\n> > ---\n> > drivers/ata/Kconfig | 10 +\n> > drivers/ata/Makefile | 1 +\n> > drivers/ata/ahci_dwc.c | 395 ++++++++++++++++++++++++++++++++++++\n> > drivers/ata/ahci_platform.c | 2 -\n> > 4 files changed, 406 insertions(+), 2 deletions(-)\n> > create mode 100644 drivers/ata/ahci_dwc.c\n> > \n> > diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\n> > index bb45a9c00514..95e0e022b5bb 100644\n> > --- a/drivers/ata/Kconfig\n> > +++ b/drivers/ata/Kconfig\n> > @@ -176,6 +176,16 @@ config AHCI_DM816\n> > \n> > \t If unsure, say N.\n> > \n> > +config AHCI_DWC\n> > +\ttristate \"Synopsys DWC AHCI SATA support\"\n> > +\tselect SATA_HOST\n> > +\tdefault SATA_AHCI_PLATFORM\n> > +\thelp\n> > +\t This option enables support for the Synopsys DWC AHCI SATA\n> > +\t controller implementation.\n> > +\n> > +\t If unsure, say N.\n> > +\n> > config AHCI_ST\n> > \ttristate \"ST AHCI SATA support\"\n> > \tdepends on ARCH_STI\n> > diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile\n> > index b8aebfb14e82..34623365d9a6 100644\n> > --- a/drivers/ata/Makefile\n> > +++ b/drivers/ata/Makefile\n> > @@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_BRCM)\t\t+= ahci_brcm.o libahci.o libahci_platform.o\n> > obj-$(CONFIG_AHCI_CEVA)\t\t+= ahci_ceva.o libahci.o libahci_platform.o\n> > obj-$(CONFIG_AHCI_DA850)\t+= ahci_da850.o libahci.o libahci_platform.o\n> > obj-$(CONFIG_AHCI_DM816)\t+= ahci_dm816.o libahci.o libahci_platform.o\n> > +obj-$(CONFIG_AHCI_DWC)\t\t+= ahci_dwc.o libahci.o libahci_platform.o\n> > obj-$(CONFIG_AHCI_IMX)\t\t+= ahci_imx.o libahci.o libahci_platform.o\n> > obj-$(CONFIG_AHCI_MTK)\t\t+= ahci_mtk.o libahci.o libahci_platform.o\n> > obj-$(CONFIG_AHCI_MVEBU)\t+= ahci_mvebu.o libahci.o libahci_platform.o\n> > diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c\n> > new file mode 100644\n> > index 000000000000..8c2510933a31\n> > --- /dev/null\n> > +++ b/drivers/ata/ahci_dwc.c\n> > @@ -0,0 +1,395 @@\n> > +// SPDX-License-Identifier: GPL-2.0-or-later\n> > +/*\n> > + * DWC AHCI SATA Platform driver\n> > + *\n> > + * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC\n> > + */\n> > +\n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +#include \n> > +\n> > +#include \"ahci.h\"\n> > +\n> > +#define DRV_NAME \"ahci-dwc\"\n> > +\n> > +#define AHCI_DWC_FBS_PMPN_MAX\t\t15\n> > +\n> > +/* DWC AHCI SATA controller specific registers */\n> > +#define AHCI_DWC_HOST_OOBR\t\t0xbc\n> > +#define AHCI_DWC_HOST_OOB_WE\t\tBIT(31)\n> > +#define AHCI_DWC_HOST_CWMIN_MASK\tGENMASK(30, 24)\n> > +#define AHCI_DWC_HOST_CWMAX_MASK\tGENMASK(23, 16)\n> > +#define AHCI_DWC_HOST_CIMIN_MASK\tGENMASK(15, 8)\n> > +#define AHCI_DWC_HOST_CIMAX_MASK\tGENMASK(7, 0)\n> > +\n> > +#define AHCI_DWC_HOST_GPCR\t\t0xd0\n> > +#define AHCI_DWC_HOST_GPSR\t\t0xd4\n> > +\n> > +#define AHCI_DWC_HOST_TIMER1MS\t\t0xe0\n> > +#define AHCI_DWC_HOST_TIMV_MASK\t\tGENMASK(19, 0)\n> > +\n> > +#define AHCI_DWC_HOST_GPARAM1R\t\t0xe8\n> > +#define AHCI_DWC_HOST_ALIGN_M\t\tBIT(31)\n> > +#define AHCI_DWC_HOST_RX_BUFFER\t\tBIT(30)\n> > +#define AHCI_DWC_HOST_PHY_DATA_MASK\tGENMASK(29, 28)\n> > +#define AHCI_DWC_HOST_PHY_RST\t\tBIT(27)\n> > +#define AHCI_DWC_HOST_PHY_CTRL_MASK\tGENMASK(26, 21)\n> > +#define AHCI_DWC_HOST_PHY_STAT_MASK\tGENMASK(20, 15)\n> > +#define AHCI_DWC_HOST_LATCH_M\t\tBIT(14)\n> > +#define AHCI_DWC_HOST_PHY_TYPE_MASK\tGENMASK(13, 11)\n> > +#define AHCI_DWC_HOST_RET_ERR\t\tBIT(10)\n> > +#define AHCI_DWC_HOST_AHB_ENDIAN_MASK\tGENMASK(9, 8)\n> > +#define AHCI_DWC_HOST_S_HADDR\t\tBIT(7)\n> > +#define AHCI_DWC_HOST_M_HADDR\t\tBIT(6)\n> > +#define AHCI_DWC_HOST_S_HDATA_MASK\tGENMASK(5, 3)\n> > +#define AHCI_DWC_HOST_M_HDATA_MASK\tGENMASK(2, 0)\n> > +\n> > +#define AHCI_DWC_HOST_GPARAM2R\t\t0xec\n> > +#define AHCI_DWC_HOST_FBS_MEM_S\t\tBIT(19)\n> > +#define AHCI_DWC_HOST_FBS_PMPN_MASK\tGENMASK(17, 16)\n> > +#define AHCI_DWC_HOST_FBS_SUP\t\tBIT(15)\n> > +#define AHCI_DWC_HOST_DEV_CP\t\tBIT(14)\n> > +#define AHCI_DWC_HOST_DEV_MP\t\tBIT(13)\n> > +#define AHCI_DWC_HOST_ENCODE_M\t\tBIT(12)\n> > +#define AHCI_DWC_HOST_RXOOB_CLK_M\tBIT(11)\n> > +#define AHCI_DWC_HOST_RXOOB_M\t\tBIT(10)\n> > +#define AHCI_DWC_HOST_TXOOB_M\t\tBIT(9)\n> > +#define AHCI_DWC_HOST_RXOOB_M\t\tBIT(10)\n> > +#define AHCI_DWC_HOST_RXOOB_CLK_MASK\tGENMASK(8, 0)\n> > +\n> > +#define AHCI_DWC_HOST_PPARAMR\t\t0xf0\n> > +#define AHCI_DWC_HOST_TX_MEM_M\t\tBIT(11)\n> > +#define AHCI_DWC_HOST_TX_MEM_S\t\tBIT(10)\n> > +#define AHCI_DWC_HOST_RX_MEM_M\t\tBIT(9)\n> > +#define AHCI_DWC_HOST_RX_MEM_S\t\tBIT(8)\n> > +#define AHCI_DWC_HOST_TXFIFO_DEPTH\tGENMASK(7, 4)\n> > +#define AHCI_DWC_HOST_RXFIFO_DEPTH\tGENMASK(3, 0)\n> > +\n> > +#define AHCI_DWC_HOST_TESTR\t\t0xf4\n> > +#define AHCI_DWC_HOST_PSEL_MASK\t\tGENMASK(18, 16)\n> > +#define AHCI_DWC_HOST_TEST_IF\t\tBIT(0)\n> > +\n> > +#define AHCI_DWC_HOST_VERSIONR\t\t0xf8\n> > +#define AHCI_DWC_HOST_IDR\t\t0xfc\n> > +\n> > +#define AHCI_DWC_PORT_DMACR\t\t0x70\n> > +#define AHCI_DWC_PORT_RXABL_MASK\tGENMASK(15, 12)\n> > +#define AHCI_DWC_PORT_TXABL_MASK\tGENMASK(11, 8)\n> > +#define AHCI_DWC_PORT_RXTS_MASK\t\tGENMASK(7, 4)\n> > +#define AHCI_DWC_PORT_TXTS_MASK\t\tGENMASK(3, 0)\n> > +#define AHCI_DWC_PORT_PHYCR\t\t0x74\n> > +#define AHCI_DWC_PORT_PHYSR\t\t0x78\n> > +\n> > +struct ahci_dwc_host_priv {\n> > +\tstruct platform_device *pdev;\n> > +\n> > +\tu32 timv;\n> > +\tu32 dmacr[AHCI_MAX_PORTS];\n> > +};\n> > +\n> > +static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev)\n> > +{\n> > +\tstruct ahci_dwc_host_priv *dpriv;\n> > +\tstruct ahci_host_priv *hpriv;\n> > +\n> > +\tdpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL);\n> > +\tif (!dpriv)\n> > +\t\treturn ERR_PTR(-ENOMEM);\n> > +\n> > +\tdpriv->pdev = pdev;\n> > +\n> > +\thpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);\n> > +\tif (IS_ERR(hpriv))\n> > +\t\treturn hpriv;\n> > +\n> > +\thpriv->plat_data = (void *)dpriv;\n> > +\n> > +\treturn hpriv;\n> > +}\n> > +\n> > +static void ahci_dwc_check_cap(struct ahci_host_priv *hpriv)\n> > +{\n> > +\tunsigned long port_map = hpriv->saved_port_map | hpriv->mask_port_map;\n> > +\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n> > +\tbool dev_mp, dev_cp, fbs_sup;\n> > +\tunsigned int fbs_pmp;\n> > +\tu32 param;\n> > +\tint i;\n> > +\n> > +\tparam = readl(hpriv->mmio + AHCI_DWC_HOST_GPARAM2R);\n> > +\tdev_mp = !!(param & AHCI_DWC_HOST_DEV_MP);\n> > +\tdev_cp = !!(param & AHCI_DWC_HOST_DEV_CP);\n> > +\tfbs_sup = !!(param & AHCI_DWC_HOST_FBS_SUP);\n> > +\tfbs_pmp = 5 * FIELD_GET(AHCI_DWC_HOST_FBS_PMPN_MASK, param);\n> > +\n> > +\tif (!dev_mp && hpriv->saved_cap & HOST_CAP_MPS) {\n> > +\t\tdev_warn(&dpriv->pdev->dev, \"MPS is unsupported\\n\");\n> > +\t\thpriv->saved_cap &= ~HOST_CAP_MPS;\n> > +\t}\n> > +\n> > +\n> > +\tif (fbs_sup && fbs_pmp < AHCI_DWC_FBS_PMPN_MAX) {\n> > +\t\tdev_warn(&dpriv->pdev->dev, \"PMPn is limited up to %u ports\\n\",\n> > +\t\t\t fbs_pmp);\n> > +\t}\n> > +\n> > +\tfor_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {\n> > +\t\tif (!dev_mp && hpriv->saved_port_cap[i] & PORT_CMD_MPSP) {\n> > +\t\t\tdev_warn(&dpriv->pdev->dev, \"MPS incapable port %d\\n\", i);\n> > +\t\t\thpriv->saved_port_cap[i] &= ~PORT_CMD_MPSP;\n> > +\t\t}\n> > +\n> > +\t\tif (!dev_cp && hpriv->saved_port_cap[i] & PORT_CMD_CPD) {\n> > +\t\t\tdev_warn(&dpriv->pdev->dev, \"CPD incapable port %d\\n\", i);\n> > +\t\t\thpriv->saved_port_cap[i] &= ~PORT_CMD_CPD;\n> > +\t\t}\n> > +\n> > +\t\tif (!fbs_sup && hpriv->saved_port_cap[i] & PORT_CMD_FBSCP) {\n> > +\t\t\tdev_warn(&dpriv->pdev->dev, \"FBS incapable port %d\\n\", i);\n> > +\t\t\thpriv->saved_port_cap[i] &= ~PORT_CMD_FBSCP;\n> > +\t\t}\n> > +\t}\n> > +}\n> > +\n> > +static void ahci_dwc_init_timer(struct ahci_host_priv *hpriv)\n> > +{\n> > +\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n> > +\tunsigned long rate;\n> > +\tstruct clk *aclk;\n> > +\tu32 cap, cap2;\n> > +\n> > +\t/* 1ms tick is generated only for the CCC or DevSleep features */\n> > +\tcap = readl(hpriv->mmio + HOST_CAP);\n> > +\tcap2 = readl(hpriv->mmio + HOST_CAP2);\n> > +\tif (!(cap & HOST_CAP_CCC) && !(cap2 & HOST_CAP2_SDS))\n> > +\t\treturn;\n> > +\n> > +\t/*\n> > +\t * Tick is generated based on the AXI/AHB application clocks signal\n> > +\t * so we need to be sure in the clock we are going to use.\n> > +\t */\n> > +\taclk = ahci_platform_find_clk(hpriv, \"aclk\");\n> > +\tif (!aclk)\n> > +\t\treturn;\n> > +\n> > +\t/* 1ms timer interval is set as TIMV = AMBA_FREQ[MHZ] * 1000 */\n> > +\tdpriv->timv = readl(hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);\n> > +\tdpriv->timv = FIELD_GET(AHCI_DWC_HOST_TIMV_MASK, dpriv->timv);\n> > +\trate = clk_get_rate(aclk) / 1000UL;\n> > +\tif (rate == dpriv->timv)\n> > +\t\treturn;\n> > +\n> > +\tdev_info(&dpriv->pdev->dev, \"Update CCC/DevSlp timer for Fapp %lu MHz\\n\",\n> > +\t\t rate / 1000UL);\n> > +\tdpriv->timv = FIELD_PREP(AHCI_DWC_HOST_TIMV_MASK, rate);\n> > +\twritel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);\n> > +}\n> > +\n> > +static int ahci_dwc_init_dmacr(struct ahci_host_priv *hpriv)\n> > +{\n> > +\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n> > +\tstruct device_node *child;\n> > +\tvoid __iomem *port_mmio;\n> > +\tu32 port, dmacr, ts;\n> > +\n> > +\t/*\n> > +\t * Update the DMA Tx/Rx transaction sizes in accordance with the\n> > +\t * platform setup. Note values exceeding maximal or minimal limits will\n> > +\t * be automatically clamped. Also note the register isn't affected by\n> > +\t * the HBA global reset so we can freely initialize it once until the\n> > +\t * next system reset.\n> > +\t */\n> > +\tfor_each_child_of_node(dpriv->pdev->dev.of_node, child) {\n> > +\t\tif (!of_device_is_available(child))\n> > +\t\t\tcontinue;\n> > +\n> > +\t\tif (of_property_read_u32(child, \"reg\", &port)) {\n> > +\t\t\tof_node_put(child);\n> > +\t\t\treturn -EINVAL;\n> > +\t\t}\n> > +\n> > +\t\tport_mmio = __ahci_port_base(hpriv, port);\n> > +\t\tdmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR);\n> > +\n> > +\t\tif (!of_property_read_u32(child, \"snps,tx-ts-max\", &ts)) {\n> > +\t\t\tts = ilog2(ts);\n> > +\t\t\tdmacr &= ~AHCI_DWC_PORT_TXTS_MASK;\n> > +\t\t\tdmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts);\n> > +\t\t}\n> > +\n> > +\t\tif (!of_property_read_u32(child, \"snps,rx-ts-max\", &ts)) {\n> > +\t\t\tts = ilog2(ts);\n> > +\t\t\tdmacr &= ~AHCI_DWC_PORT_RXTS_MASK;\n> > +\t\t\tdmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts);\n> > +\t\t}\n> > +\n> > +\t\twritel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR);\n> > +\t\tdpriv->dmacr[port] = dmacr;\n> > +\t}\n> > +\n> > +\treturn 0;\n> > +}\n> > +\n> > +static int ahci_dwc_init_host(struct ahci_host_priv *hpriv)\n> > +{\n> > +\tint rc;\n> > +\n> > +\trc = ahci_platform_enable_resources(hpriv);\n> > +\tif (rc)\n> > +\t\treturn rc;\n> > +\n> > +\tahci_dwc_check_cap(hpriv);\n> > +\n> > +\tahci_dwc_init_timer(hpriv);\n> > +\n> > +\trc = ahci_dwc_init_dmacr(hpriv);\n> > +\tif (rc)\n> > +\t\tgoto err_disable_resources;\n> > +\n> > +\treturn 0;\n> > +\n> > +err_disable_resources:\n> > +\tahci_platform_disable_resources(hpriv);\n> > +\n> > +\treturn rc;\n> > +}\n> > +\n> > +static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv)\n> > +{\n> > +\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n> > +\tunsigned long port_map = hpriv->port_map;\n> > +\tvoid __iomem *port_mmio;\n> > +\tint i, rc;\n> > +\n> > +\trc = ahci_platform_enable_resources(hpriv);\n> > +\tif (rc)\n> > +\t\treturn rc;\n> > +\n> > +\twritel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);\n> > +\n> > +\tfor_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {\n> > +\t\tport_mmio = __ahci_port_base(hpriv, i);\n> > +\t\twritel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR);\n> > +\t}\n> > +\n> > +\treturn 0;\n> > +}\n> > +\n> > +static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv)\n> > +{\n> > +\tahci_platform_disable_resources(hpriv);\n> > +}\n> > +\n> > +static void ahci_dwc_stop_host(struct ata_host *host)\n> > +{\n> > +\tstruct ahci_host_priv *hpriv = host->private_data;\n> > +\n> > +\tahci_dwc_clear_host(hpriv);\n> > +}\n> > +\n> > +static struct ata_port_operations ahci_dwc_port_ops = {\n> > +\t.inherits\t= &ahci_platform_ops,\n> > +\t.host_stop\t= ahci_dwc_stop_host,\n> > +};\n> > +\n> > +static const struct ata_port_info ahci_dwc_port_info = {\n> > +\t.flags\t\t= AHCI_FLAG_COMMON,\n> > +\t.pio_mask\t= ATA_PIO4,\n> > +\t.udma_mask\t= ATA_UDMA6,\n> > +\t.port_ops\t= &ahci_dwc_port_ops,\n> > +};\n> > +\n> > +static struct scsi_host_template ahci_dwc_scsi_info = {\n> > +\tAHCI_SHT(DRV_NAME),\n> > +};\n> > +\n> > +static int ahci_dwc_probe(struct platform_device *pdev)\n> > +{\n> > +\tstruct ahci_host_priv *hpriv;\n> > +\tint rc;\n> > +\n> > +\thpriv = ahci_dwc_get_resources(pdev);\n> > +\tif (IS_ERR(hpriv))\n> > +\t\treturn PTR_ERR(hpriv);\n> > +\n> > +\trc = ahci_dwc_init_host(hpriv);\n> > +\tif (rc)\n> > +\t\treturn rc;\n> > +\n> > +\trc = ahci_platform_init_host(pdev, hpriv, &ahci_dwc_port_info,\n> > +\t\t\t\t &ahci_dwc_scsi_info);\n> > +\tif (rc)\n> > +\t\tgoto err_clear_host;\n> > +\n> > +\treturn 0;\n> > +\n> > +err_clear_host:\n> > +\tahci_dwc_clear_host(hpriv);\n> > +\n> > +\treturn rc;\n> > +}\n> > +\n> > +#ifdef CONFIG_PM_SLEEP\n> > +static int ahci_dwc_suspend(struct device *dev)\n> > +{\n> > +\tstruct ata_host *host = dev_get_drvdata(dev);\n> > +\tstruct ahci_host_priv *hpriv = host->private_data;\n> > +\tint rc;\n> > +\n> > +\trc = ahci_platform_suspend_host(dev);\n> > +\tif (rc)\n> > +\t\treturn rc;\n> > +\n> > +\tahci_dwc_clear_host(hpriv);\n> > +\n> > +\treturn 0;\n> > +}\n> > +\n> > +static int ahci_dwc_resume(struct device *dev)\n> > +{\n> > +\tstruct ata_host *host = dev_get_drvdata(dev);\n> > +\tstruct ahci_host_priv *hpriv = host->private_data;\n> > +\tint rc;\n> > +\n> > +\trc = ahci_dwc_reinit_host(hpriv);\n> > +\tif (rc)\n> > +\t\treturn rc;\n> > +\n> > +\treturn ahci_platform_resume_host(dev);\n> > +}\n> > +#endif\n> > +\n> > +static SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend, ahci_dwc_resume);\n> \n\n> include/linux/pm.h says:\n> /* Deprecated. Use DEFINE_SIMPLE_DEV_PM_OPS() instead. */\n\nOk.\n\n> \n> > +\n> > +static const struct of_device_id ahci_dwc_of_match[] = {\n> > +\t{ .compatible = \"snps,dwc-ahci\", },\n> > +\t{ .compatible = \"snps,spear-ahci\", },\n> > +\t{},\n> > +};\n> > +MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);\n> > +\n> > +static struct platform_driver ahci_dwc_driver = {\n> > +\t.probe = ahci_dwc_probe,\n> > +\t.remove = ata_platform_remove_one,\n> > +\t.shutdown = ahci_platform_shutdown,\n> > +\t.driver = {\n> > +\t\t.name = DRV_NAME,\n> > +\t\t.of_match_table = ahci_dwc_of_match,\n> > +\t\t.pm = &ahci_dwc_pm_ops,\n> > +\t},\n> > +};\n> > +module_platform_driver(ahci_dwc_driver);\n> > +\n> > +MODULE_DESCRIPTION(\"DWC AHCI SATA platform driver\");\n> > +MODULE_AUTHOR(\"Serge Semin \");\n> > +MODULE_LICENSE(\"GPL\");\n> \n\n> MODULE_LICENSE(\"GPL v2\");\n> \n> To match the file header SPDX.\n\nNo. Please see the commit bf7fbeeae6db (\"module: Cure the\nMODULE_LICENSE \"GPL\" vs. \"GPL v2\" bogosity\") and what checkpatch.pl\nsays should the \"GPL v2\" string is used in the module license block.\nMore info regarding this macro and the possible license values are\ndescribed here:\nDocumentation/process/license-rules.rst\n\n-Sergey\n\n> \n> > diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c\n> > index 9b56490ecbc3..8f5572a9f8f1 100644\n> > --- a/drivers/ata/ahci_platform.c\n> > +++ b/drivers/ata/ahci_platform.c\n> > @@ -80,9 +80,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,\n> > static const struct of_device_id ahci_of_match[] = {\n> > \t{ .compatible = \"generic-ahci\", },\n> > \t/* Keep the following compatibles for device tree compatibility */\n> > -\t{ .compatible = \"snps,spear-ahci\", },\n> > \t{ .compatible = \"ibm,476gtr-ahci\", },\n> > -\t{ .compatible = \"snps,dwc-ahci\", },\n> > \t{ .compatible = \"hisilicon,hisi-ahci\", },\n> > \t{ .compatible = \"cavium,octeon-7130-ahci\", },\n> > \t{ /* sentinel */ }\n> \n> \n> -- \n> Damien Le Moal\n> Western Digital Research","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20210112 header.b=pONlZCHv;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<52c9ca79-769f-4426-db94-7aad05a68258@opensource.wdc.com>","X-Spam-Status":"No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,\n RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE\n autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2913857,"web_url":"http://patchwork.ozlabs.org/comment/2913857/","msgid":"","list_archive_url":null,"date":"2022-06-16T00:31:30","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":82259,"url":"http://patchwork.ozlabs.org/api/people/82259/","name":"Damien Le Moal","email":"damien.lemoal@opensource.wdc.com"},"content":"On 2022/06/16 6:30, Serge Semin wrote:\n> On Fri, Jun 10, 2022 at 04:34:13PM -0700, Randy Dunlap wrote:\n>> Hi Serge,\n>>\n>> On 6/10/22 14:58, Serge Semin wrote:\n>>> On Fri, Jun 10, 2022 at 09:34:46AM -0700, Randy Dunlap wrote:\n>>>> Hi--\n>>>\n>>> Hi Randy\n>>>\n>>>>\n>>>> On 6/10/22 01:17, Serge Semin wrote:\n>>>>> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\n>>>>> index bb45a9c00514..95e0e022b5bb 100644\n>>>>> --- a/drivers/ata/Kconfig\n>>>>> +++ b/drivers/ata/Kconfig\n>>>>> @@ -176,6 +176,16 @@ config AHCI_DM816\n>>>>> \n>>>>> \t If unsure, say N.\n>>>>> \n>>>>> +config AHCI_DWC\n>>>>> +\ttristate \"Synopsys DWC AHCI SATA support\"\n>>>>> +\tselect SATA_HOST\n>>>>> +\tdefault SATA_AHCI_PLATFORM\n>>>>\n>>>\n>>>> I don't think this needs to default to SATA_AHCI_PLATFORM.\n>>>> It might build a driver that isn't needed.\n>>>> And it's incompatible with \"If unsure, say N.\"\n>>>\n>>> Basically you are right, but this particular setting is connected with\n>>> the modification I've done in the drivers/ata/ahci_platform.c driver\n>>> in the framework of this commit. I've moved the \"snps,spear-ahci\" and\n>>> \"snps,dwc-ahci\" compatible devices support to the new driver. Thus\n>>> should I omit the SATA_AHCI_PLATFORM dependency their default kernel\n>>> configs will lack the corresponding controllers support. If it's not a\n>>> problem and we can rely on the kernel build system ability to ask\n>>> whether the new config needs to be set/cleared, then I would be very\n>>> happy to drop the default setting. What do you think?\n>>\n> \n>> I'd prefer to try it like that.\n>> If it becomes a problem, we can go back to this v4 patch.\n> \n> Agreed then (seeing Damien is silent about your comment).\n\nI have not thought about it :)\nI do not use SATA PLATFORM at all, so I am not familiar with its dependencies.\nWill have a look and do my usual build tests anyway.\n\n> \n> -Sergey\n> \n>>\n>>>>> +\thelp\n>>>>> +\t This option enables support for the Synopsys DWC AHCI SATA\n>>>>> +\t controller implementation.\n>>>>> +\n>>>>> +\t If unsure, say N.\n>>>>\n>>>> -- \n>>>> ~Randy\n>>\n>> Thanks.\n>> -- \n>> ~Randy","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256\n header.s=dkim.wdc.com header.b=mFinrey1;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=opensource.wdc.com header.i=@opensource.wdc.com\n header.a=rsa-sha256 header.s=dkim header.b=PP8LAnE1;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; 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Intel Mac OS X 10.15; rv:91.0)\n Gecko/20100101 Thunderbird/91.10.0","Subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","Content-Language":"en-US","To":"Serge Semin ,\n Randy Dunlap ","Cc":"Serge Semin ,\n Hans de Goede ,\n Jens Axboe , Hannes Reinecke ,\n Alexey Malahov ,\n Pavel Parkhomenko ,\n Rob Herring , linux-ide@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org","References":"<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>\n <20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru>\n <6c02f8ef-8aea-8f80-590d-343f67a96f8d@infradead.org>\n <20220610215850.ju76kxjquwef6kd3@mobilestation>\n <73716f9f-892c-41c5-89f0-64a1985438aa@infradead.org>\n <20220615213029.3upsmasnnhigqozm@mobilestation>","From":"Damien Le Moal ","Organization":"Western Digital Research","In-Reply-To":"<20220615213029.3upsmasnnhigqozm@mobilestation>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-5.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED,\n SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable\n autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2913860,"web_url":"http://patchwork.ozlabs.org/comment/2913860/","msgid":"<5f1edbd8-018a-bcd0-10f2-94767f341b45@opensource.wdc.com>","list_archive_url":null,"date":"2022-06-16T00:33:22","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":82259,"url":"http://patchwork.ozlabs.org/api/people/82259/","name":"Damien Le Moal","email":"damien.lemoal@opensource.wdc.com"},"content":"On 2022/06/16 6:48, Serge Semin wrote:\n[...]\n>> MODULE_LICENSE(\"GPL v2\");\n>>\n>> To match the file header SPDX.\n> \n> No. Please see the commit bf7fbeeae6db (\"module: Cure the\n> MODULE_LICENSE \"GPL\" vs. \"GPL v2\" bogosity\") and what checkpatch.pl\n> says should the \"GPL v2\" string is used in the module license block.\n> More info regarding this macro and the possible license values are\n> described here:\n> Documentation/process/license-rules.rst\n\nah ! OK. I was not 100% sure. Doing a quick grep, there is still a lot of (half\n?) of \"GPL v2\" vs \"GPL\".\n\nIgnore this then.\n\n> \n> -Sergey\n> \n>>\n>>> diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c\n>>> index 9b56490ecbc3..8f5572a9f8f1 100644\n>>> --- a/drivers/ata/ahci_platform.c\n>>> +++ b/drivers/ata/ahci_platform.c\n>>> @@ -80,9 +80,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,\n>>> static const struct of_device_id ahci_of_match[] = {\n>>> \t{ .compatible = \"generic-ahci\", },\n>>> \t/* Keep the following compatibles for device tree compatibility */\n>>> -\t{ .compatible = \"snps,spear-ahci\", },\n>>> \t{ .compatible = \"ibm,476gtr-ahci\", },\n>>> -\t{ .compatible = \"snps,dwc-ahci\", },\n>>> \t{ .compatible = \"hisilicon,hisi-ahci\", },\n>>> \t{ .compatible = \"cavium,octeon-7130-ahci\", },\n>>> \t{ /* sentinel */ }\n>>\n>>\n>> -- \n>> Damien Le Moal\n>> Western Digital Research\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256\n header.s=dkim.wdc.com header.b=VcGosERU;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=opensource.wdc.com header.i=@opensource.wdc.com\n header.a=rsa-sha256 header.s=dkim header.b=NQ4xGNcQ;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; 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Intel Mac OS X 10.15; rv:91.0)\n Gecko/20100101 Thunderbird/91.10.0","Subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","Content-Language":"en-US","To":"Serge Semin ","Cc":"Serge Semin ,\n Hans de Goede ,\n Jens Axboe , Hannes Reinecke ,\n Alexey Malahov ,\n Pavel Parkhomenko ,\n Rob Herring , linux-ide@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org","References":"<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>\n <20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru>\n <52c9ca79-769f-4426-db94-7aad05a68258@opensource.wdc.com>\n <20220615214802.ke6owp5cuv5l77hu@mobilestation>","From":"Damien Le Moal ","Organization":"Western Digital Research","In-Reply-To":"<20220615214802.ke6owp5cuv5l77hu@mobilestation>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-5.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED,\n SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham\n autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2915227,"web_url":"http://patchwork.ozlabs.org/comment/2915227/","msgid":"<20220617203419.ksoald7am3677csh@mobilestation>","list_archive_url":null,"date":"2022-06-17T20:34:19","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":70038,"url":"http://patchwork.ozlabs.org/api/people/70038/","name":"Serge Semin","email":"fancer.lancer@gmail.com"},"content":"On Thu, Jun 16, 2022 at 09:33:22AM +0900, Damien Le Moal wrote:\n> On 2022/06/16 6:48, Serge Semin wrote:\n> [...]\n> >> MODULE_LICENSE(\"GPL v2\");\n> >>\n> >> To match the file header SPDX.\n> > \n> > No. Please see the commit bf7fbeeae6db (\"module: Cure the\n> > MODULE_LICENSE \"GPL\" vs. \"GPL v2\" bogosity\") and what checkpatch.pl\n> > says should the \"GPL v2\" string is used in the module license block.\n> > More info regarding this macro and the possible license values are\n> > described here:\n> > Documentation/process/license-rules.rst\n> \n\n> ah ! OK. I was not 100% sure. Doing a quick grep, there is still a lot of (half\n> ?) of \"GPL v2\" vs \"GPL\".\n> \n> Ignore this then.\n\nOk.\n\n-Sergey\n\n> \n> > \n> > -Sergey\n> > \n> >>\n> >>> diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c\n> >>> index 9b56490ecbc3..8f5572a9f8f1 100644\n> >>> --- a/drivers/ata/ahci_platform.c\n> >>> +++ b/drivers/ata/ahci_platform.c\n> >>> @@ -80,9 +80,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,\n> >>> static const struct of_device_id ahci_of_match[] = {\n> >>> \t{ .compatible = \"generic-ahci\", },\n> >>> \t/* Keep the following compatibles for device tree compatibility */\n> >>> -\t{ .compatible = \"snps,spear-ahci\", },\n> >>> \t{ .compatible = \"ibm,476gtr-ahci\", },\n> >>> -\t{ .compatible = \"snps,dwc-ahci\", },\n> >>> \t{ .compatible = \"hisilicon,hisi-ahci\", },\n> >>> \t{ .compatible = \"cavium,octeon-7130-ahci\", },\n> >>> \t{ /* sentinel */ }\n> >>\n> >>\n> >> -- \n> >> Damien Le Moal\n> >> Western Digital Research\n> > \n> \n> \n> -- \n> Damien Le Moal\n> Western Digital Research","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20210112 header.b=lw8A+ey8;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<5f1edbd8-018a-bcd0-10f2-94767f341b45@opensource.wdc.com>","X-Spam-Status":"No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,\n RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE\n autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2915231,"web_url":"http://patchwork.ozlabs.org/comment/2915231/","msgid":"<20220617203649.wa2b3etx6gpm3s5g@mobilestation>","list_archive_url":null,"date":"2022-06-17T20:36:49","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":70038,"url":"http://patchwork.ozlabs.org/api/people/70038/","name":"Serge Semin","email":"fancer.lancer@gmail.com"},"content":"On Thu, Jun 16, 2022 at 09:31:30AM +0900, Damien Le Moal wrote:\n> On 2022/06/16 6:30, Serge Semin wrote:\n> > On Fri, Jun 10, 2022 at 04:34:13PM -0700, Randy Dunlap wrote:\n> >> Hi Serge,\n> >>\n> >> On 6/10/22 14:58, Serge Semin wrote:\n> >>> On Fri, Jun 10, 2022 at 09:34:46AM -0700, Randy Dunlap wrote:\n> >>>> Hi--\n> >>>\n> >>> Hi Randy\n> >>>\n> >>>>\n> >>>> On 6/10/22 01:17, Serge Semin wrote:\n> >>>>> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\n> >>>>> index bb45a9c00514..95e0e022b5bb 100644\n> >>>>> --- a/drivers/ata/Kconfig\n> >>>>> +++ b/drivers/ata/Kconfig\n> >>>>> @@ -176,6 +176,16 @@ config AHCI_DM816\n> >>>>> \n> >>>>> \t If unsure, say N.\n> >>>>> \n> >>>>> +config AHCI_DWC\n> >>>>> +\ttristate \"Synopsys DWC AHCI SATA support\"\n> >>>>> +\tselect SATA_HOST\n> >>>>> +\tdefault SATA_AHCI_PLATFORM\n> >>>>\n> >>>\n> >>>> I don't think this needs to default to SATA_AHCI_PLATFORM.\n> >>>> It might build a driver that isn't needed.\n> >>>> And it's incompatible with \"If unsure, say N.\"\n> >>>\n> >>> Basically you are right, but this particular setting is connected with\n> >>> the modification I've done in the drivers/ata/ahci_platform.c driver\n> >>> in the framework of this commit. I've moved the \"snps,spear-ahci\" and\n> >>> \"snps,dwc-ahci\" compatible devices support to the new driver. Thus\n> >>> should I omit the SATA_AHCI_PLATFORM dependency their default kernel\n> >>> configs will lack the corresponding controllers support. If it's not a\n> >>> problem and we can rely on the kernel build system ability to ask\n> >>> whether the new config needs to be set/cleared, then I would be very\n> >>> happy to drop the default setting. What do you think?\n> >>\n> > \n> >> I'd prefer to try it like that.\n> >> If it becomes a problem, we can go back to this v4 patch.\n> > \n> > Agreed then (seeing Damien is silent about your comment).\n> \n\n> I have not thought about it :)\n> I do not use SATA PLATFORM at all, so I am not familiar with its dependencies.\n> Will have a look and do my usual build tests anyway.\n\nOk. I'll be waiting for you reply in this regard the before\nre-submitting the next series version.\n\n-Sergey\n\n> \n> > \n> > -Sergey\n> > \n> >>\n> >>>>> +\thelp\n> >>>>> +\t This option enables support for the Synopsys DWC AHCI SATA\n> >>>>> +\t controller implementation.\n> >>>>> +\n> >>>>> +\t If unsure, say N.\n> >>>>\n> >>>> -- \n> >>>> ~Randy\n> >>\n> >> Thanks.\n> >> -- \n> >> ~Randy\n> \n> \n> -- \n> Damien Le Moal\n> Western Digital Research","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20210112 header.b=cPydoDo5;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-ide-owner@vger.kernel.org; receiver=)"],"Received":["from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 4LPrWw22ZBz9sG2\n\tfor ; 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charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","X-Spam-Status":"No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM,\n RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE\n autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}},{"id":2915385,"web_url":"http://patchwork.ozlabs.org/comment/2915385/","msgid":"","list_archive_url":null,"date":"2022-06-18T06:54:30","subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","submitter":{"id":82259,"url":"http://patchwork.ozlabs.org/api/people/82259/","name":"Damien Le Moal","email":"damien.lemoal@opensource.wdc.com"},"content":"On 6/18/22 05:36, Serge Semin wrote:\n> On Thu, Jun 16, 2022 at 09:31:30AM +0900, Damien Le Moal wrote:\n>> On 2022/06/16 6:30, Serge Semin wrote:\n>>> On Fri, Jun 10, 2022 at 04:34:13PM -0700, Randy Dunlap wrote:\n>>>> Hi Serge,\n>>>>\n>>>> On 6/10/22 14:58, Serge Semin wrote:\n>>>>> On Fri, Jun 10, 2022 at 09:34:46AM -0700, Randy Dunlap wrote:\n>>>>>> Hi--\n>>>>>\n>>>>> Hi Randy\n>>>>>\n>>>>>>\n>>>>>> On 6/10/22 01:17, Serge Semin wrote:\n>>>>>>> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\n>>>>>>> index bb45a9c00514..95e0e022b5bb 100644\n>>>>>>> --- a/drivers/ata/Kconfig\n>>>>>>> +++ b/drivers/ata/Kconfig\n>>>>>>> @@ -176,6 +176,16 @@ config AHCI_DM816\n>>>>>>> \n>>>>>>> \t If unsure, say N.\n>>>>>>> \n>>>>>>> +config AHCI_DWC\n>>>>>>> +\ttristate \"Synopsys DWC AHCI SATA support\"\n>>>>>>> +\tselect SATA_HOST\n>>>>>>> +\tdefault SATA_AHCI_PLATFORM\n>>>>>>\n>>>>>\n>>>>>> I don't think this needs to default to SATA_AHCI_PLATFORM.\n>>>>>> It might build a driver that isn't needed.\n>>>>>> And it's incompatible with \"If unsure, say N.\"\n>>>>>\n>>>>> Basically you are right, but this particular setting is connected with\n>>>>> the modification I've done in the drivers/ata/ahci_platform.c driver\n>>>>> in the framework of this commit. I've moved the \"snps,spear-ahci\" and\n>>>>> \"snps,dwc-ahci\" compatible devices support to the new driver. Thus\n>>>>> should I omit the SATA_AHCI_PLATFORM dependency their default kernel\n>>>>> configs will lack the corresponding controllers support. If it's not a\n>>>>> problem and we can rely on the kernel build system ability to ask\n>>>>> whether the new config needs to be set/cleared, then I would be very\n>>>>> happy to drop the default setting. What do you think?\n>>>>\n>>>\n>>>> I'd prefer to try it like that.\n>>>> If it becomes a problem, we can go back to this v4 patch.\n>>>\n>>> Agreed then (seeing Damien is silent about your comment).\n>>\n> \n>> I have not thought about it :)\n>> I do not use SATA PLATFORM at all, so I am not familiar with its dependencies.\n>> Will have a look and do my usual build tests anyway.\n> \n> Ok. I'll be waiting for you reply in this regard the before\n> re-submitting the next series version.\n\nPlease send a fixed-up new version. I will use that to look at builds and\nconfig dependencies.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=wdc.com header.i=@wdc.com header.a=rsa-sha256\n header.s=dkim.wdc.com header.b=p6VpgH8y;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=opensource.wdc.com header.i=@opensource.wdc.com\n header.a=rsa-sha256 header.s=dkim header.b=pKJhH2iF;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-ide-owner@vger.kernel.org; receiver=)","usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass\n reason=\"pass (just generated, assumed good)\"\n header.d=opensource.wdc.com"],"Received":["from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 4LQ68w0g6Qz9s75\n\tfor ; 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Linux x86_64; rv:91.0) Gecko/20100101\n Thunderbird/91.10.0","Subject":"Re: [PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support","Content-Language":"en-US","To":"Serge Semin ","Cc":"Randy Dunlap ,\n Serge Semin ,\n Hans de Goede ,\n Jens Axboe , Hannes Reinecke ,\n Alexey Malahov ,\n Pavel Parkhomenko ,\n Rob Herring , linux-ide@vger.kernel.org,\n linux-kernel@vger.kernel.org, devicetree@vger.kernel.org","References":"<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>\n <20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru>\n <6c02f8ef-8aea-8f80-590d-343f67a96f8d@infradead.org>\n <20220610215850.ju76kxjquwef6kd3@mobilestation>\n <73716f9f-892c-41c5-89f0-64a1985438aa@infradead.org>\n <20220615213029.3upsmasnnhigqozm@mobilestation>\n \n <20220617203649.wa2b3etx6gpm3s5g@mobilestation>","From":"Damien Le Moal ","Organization":"Western Digital Research","In-Reply-To":"<20220617203649.wa2b3etx6gpm3s5g@mobilestation>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-6.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_MED,\n SPF_HELO_PASS,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable\n autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-ide@vger.kernel.org"}}]