[{"id":2899691,"web_url":"http://patchwork.ozlabs.org/comment/2899691/","msgid":"<3ca91605-546d-8a6f-e8fd-57fdbc0b8e4c@foss.st.com>","list_archive_url":null,"date":"2022-05-20T06:27:49","subject":"Re: [PATCH v2 1/3] clk: Add directory for STM32 clock drivers","submitter":{"id":80709,"url":"http://patchwork.ozlabs.org/api/people/80709/","name":"Patrice Chotard","email":"patrice.chotard@foss.st.com"},"content":"Hi Patrick\n\nOn 5/19/22 17:56, Patrick Delaunay wrote:\n> Add a directory in drivers/clk to regroup the clock drivers for all\n> STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or\n> CONFIG_ARCH_STM32MP (MPUs with cortex A).\n> \n> Signed-off-by: Patrick Delaunay \n> ---\n> \n> Changes in v2:\n> - replace '_' by '-' in file names to be consistant with other clk drivers\n> and prepare introduction of new files for stm32mp13\n> \n> MAINTAINERS | 2 +-\n> drivers/clk/Kconfig | 17 +-------------\n> drivers/clk/Makefile | 5 ++--\n> drivers/clk/stm32/Kconfig | 23 +++++++++++++++++++\n> drivers/clk/stm32/Makefile | 7 ++++++\n> .../clk/{clk_stm32f.c => stm32/clk-stm32f.c} | 0\n> .../{clk_stm32h7.c => stm32/clk-stm32h7.c} | 0\n> .../{clk_stm32mp1.c => stm32/clk-stm32mp1.c} | 0\n> 8 files changed, 34 insertions(+), 20 deletions(-)\n> create mode 100644 drivers/clk/stm32/Kconfig\n> create mode 100644 drivers/clk/stm32/Makefile\n> rename drivers/clk/{clk_stm32f.c => stm32/clk-stm32f.c} (100%)\n> rename drivers/clk/{clk_stm32h7.c => stm32/clk-stm32h7.c} (100%)\n> rename drivers/clk/{clk_stm32mp1.c => stm32/clk-stm32mp1.c} (100%)\n> \n> diff --git a/MAINTAINERS b/MAINTAINERS\n> index 56be0bfad0..3f37edd716 100644\n> --- a/MAINTAINERS\n> +++ b/MAINTAINERS\n> @@ -469,7 +469,7 @@ S:\tMaintained\n> F:\tarch/arm/mach-stm32mp/\n> F:\tdoc/board/st/\n> F:\tdrivers/adc/stm32-adc*\n> -F:\tdrivers/clk/clk_stm32mp1.c\n> +F:\tdrivers/clk/stm32/\n> F:\tdrivers/gpio/stm32_gpio.c\n> F:\tdrivers/hwspinlock/stm32_hwspinlock.c\n> F:\tdrivers/i2c/stm32f7_i2c.c\n> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig\n> index a62b81a123..fd9e1a80c6 100644\n> --- a/drivers/clk/Kconfig\n> +++ b/drivers/clk/Kconfig\n> @@ -166,22 +166,6 @@ config CLK_SCMI\n> \t by a SCMI agent based on SCMI clock protocol communication\n> \t with a SCMI server.\n> \n> -config CLK_STM32F\n> -\tbool \"Enable clock driver support for STM32F family\"\n> -\tdepends on CLK && (STM32F7 || STM32F4)\n> -\tdefault y\n> -\thelp\n> -\t This clock driver adds support for RCC clock management\n> -\t for STM32F4 and STM32F7 SoCs.\n> -\n> -config CLK_STM32MP1\n> -\tbool \"Enable RCC clock driver for STM32MP1\"\n> -\tdepends on ARCH_STM32MP && CLK\n> -\tdefault y\n> -\thelp\n> -\t Enable the STM32 clock (RCC) driver. Enable support for\n> -\t manipulating STM32MP1's on-SoC clocks.\n> -\n> config CLK_HSDK\n> \tbool \"Enable cgu clock driver for HSDK boards\"\n> \tdepends on CLK && TARGET_HSDK\n> @@ -251,6 +235,7 @@ source \"drivers/clk/owl/Kconfig\"\n> source \"drivers/clk/renesas/Kconfig\"\n> source \"drivers/clk/sunxi/Kconfig\"\n> source \"drivers/clk/sifive/Kconfig\"\n> +source \"drivers/clk/stm32/Kconfig\"\n> source \"drivers/clk/tegra/Kconfig\"\n> source \"drivers/clk/ti/Kconfig\"\n> source \"drivers/clk/uniphier/Kconfig\"\n> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\n> index f5b553172c..c274cda77c 100644\n> --- a/drivers/clk/Makefile\n> +++ b/drivers/clk/Makefile\n> @@ -23,6 +23,8 @@ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/\n> obj-$(CONFIG_ARCH_NPCM) += nuvoton/\n> obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/\n> obj-$(CONFIG_ARCH_SOCFPGA) += altera/\n> +obj-$(CONFIG_ARCH_STM32) += stm32/\n> +obj-$(CONFIG_ARCH_STM32MP) += stm32/\n> obj-$(CONFIG_ARCH_SUNXI) += sunxi/\n> obj-$(CONFIG_CLK_AT91) += at91/\n> obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o\n> @@ -39,8 +41,6 @@ obj-$(CONFIG_CLK_OWL) += owl/\n> obj-$(CONFIG_CLK_RENESAS) += renesas/\n> obj-$(CONFIG_CLK_SCMI) += clk_scmi.o\n> obj-$(CONFIG_CLK_SIFIVE) += sifive/\n> -obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o\n> -obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o\n> obj-$(CONFIG_CLK_UNIPHIER) += uniphier/\n> obj-$(CONFIG_CLK_VERSACLOCK) += clk_versaclock.o\n> obj-$(CONFIG_CLK_VERSAL) += clk_versal.o\n> @@ -53,4 +53,3 @@ obj-$(CONFIG_MACH_PIC32) += clk_pic32.o\n> obj-$(CONFIG_SANDBOX_CLK_CCF) += clk_sandbox_ccf.o\n> obj-$(CONFIG_SANDBOX) += clk_sandbox.o\n> obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o\n> -obj-$(CONFIG_STM32H7) += clk_stm32h7.o\n> diff --git a/drivers/clk/stm32/Kconfig b/drivers/clk/stm32/Kconfig\n> new file mode 100644\n> index 0000000000..eac3fc1e9d\n> --- /dev/null\n> +++ b/drivers/clk/stm32/Kconfig\n> @@ -0,0 +1,23 @@\n> +config CLK_STM32F\n> +\tbool \"Enable clock driver support for STM32F family\"\n> +\tdepends on CLK && (STM32F7 || STM32F4)\n> +\tdefault y\n> +\thelp\n> +\t This clock driver adds support for RCC clock management\n> +\t for STM32F4 and STM32F7 SoCs.\n> +\n> +config CLK_STM32H7\n> +\tbool \"Enable clock driver support for STM32H7 family\"\n> +\tdepends on CLK && STM32H7\n> +\tdefault y\n> +\thelp\n> +\t This clock driver adds support for RCC clock management\n> +\t for STM32H7 SoCs.\n> +\n> +config CLK_STM32MP1\n> +\tbool \"Enable RCC clock driver for STM32MP15\"\n> +\tdepends on ARCH_STM32MP && CLK\n> +\tdefault y if STM32MP15x\n> +\thelp\n> +\t Enable the STM32 clock (RCC) driver. Enable support for\n> +\t manipulating STM32MP15's on-SoC clocks.\n> diff --git a/drivers/clk/stm32/Makefile b/drivers/clk/stm32/Makefile\n> new file mode 100644\n> index 0000000000..f66f295403\n> --- /dev/null\n> +++ b/drivers/clk/stm32/Makefile\n> @@ -0,0 +1,7 @@\n> +# SPDX-License-Identifier: GPL-2.0-or-later\n> +#\n> +# Copyright (C) 2022, STMicroelectronics - All Rights Reserved\n> +\n> +obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o\n> +obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o\n> +obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o\n> diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/stm32/clk-stm32f.c\n> similarity index 100%\n> rename from drivers/clk/clk_stm32f.c\n> rename to drivers/clk/stm32/clk-stm32f.c\n> diff --git a/drivers/clk/clk_stm32h7.c b/drivers/clk/stm32/clk-stm32h7.c\n> similarity index 100%\n> rename from drivers/clk/clk_stm32h7.c\n> rename to drivers/clk/stm32/clk-stm32h7.c\n> diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/stm32/clk-stm32mp1.c\n> similarity index 100%\n> rename from drivers/clk/clk_stm32mp1.c\n> rename to drivers/clk/stm32/clk-stm32mp1.c\n\n\nReviewed-by: Patrice Chotard \n\nThanks\nPatrice","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=foss.st.com header.i=@foss.st.com header.a=rsa-sha256\n header.s=selector1 header.b=T0bD4sjK;\n\tdkim-atps=neutral","ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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Linux x86_64; rv:91.0) Gecko/20100101\n Thunderbird/91.8.1","Subject":"Re: [PATCH v2 1/3] clk: Add directory for STM32 clock drivers","Content-Language":"en-US","To":"Patrick Delaunay , ","CC":"Gabriel FERNANDEZ , Lukasz Majewski\n , Sean Anderson ,\n ","References":"<20220519155647.1433652-1-patrick.delaunay@foss.st.com>\n <20220519175614.v2.1.Ieec76f320c9cc6885d7b519dffddff9ad4c97b59@changeid>","From":"Patrice CHOTARD ","In-Reply-To":"\n <20220519175614.v2.1.Ieec76f320c9cc6885d7b519dffddff9ad4c97b59@changeid>","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.75.127.50]","X-ClientProxiedBy":"SFHDAG2NODE3.st.com (10.75.127.6) To SHFDAG1NODE1.st.com\n (10.75.129.69)","X-Proofpoint-Virus-Version":"vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-05-20_02,2022-05-19_03,2022-02-23_01","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.39","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" ","X-Virus-Scanned":"clamav-milter 0.103.5 at phobos.denx.de","X-Virus-Status":"Clean"}},{"id":2900481,"web_url":"http://patchwork.ozlabs.org/comment/2900481/","msgid":"","list_archive_url":null,"date":"2022-05-21T07:19:37","subject":"Re: [PATCH v2 1/3] clk: Add directory for STM32 clock drivers","submitter":{"id":81591,"url":"http://patchwork.ozlabs.org/api/people/81591/","name":"Grzegorz Szymaszek","email":"gszymaszek@short.pl"},"content":"On Thu, May 19, 2022 at 05:56:45PM +0200, Patrick Delaunay wrote:\n> Add a directory in drivers/clk to regroup the clock drivers for all\n> STM32 Soc with CONFIG_ARCH_STM32 (MCUs with cortex M) or\n> CONFIG_ARCH_STM32MP (MPUs with cortex A).\n\nSome nits:\n- s/Soc/SoCs/\n- s/cortex /Cortex-/\n\nEven if you will not include these two changes, feel free to add:\nReviewed-by: Grzegorz Szymaszek ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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Sat, 21 May 2022 09:19:42 +0200 (CEST)","from [192.168.192.146] (port=38330 helo=nx64de-df6d00)\n by mx01.ayax.eu with esmtpsa (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.92) (envelope-from )\n id 1nsJOk-0003GX-F7; Sat, 21 May 2022 09:19:38 +0200"],"X-Spam-Checker-Version":"SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS,\n SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no\n version=3.4.2","Date":"Sat, 21 May 2022 09:19:37 +0200","From":"Grzegorz Szymaszek ","To":"Patrick Delaunay ","Cc":"u-boot@lists.denx.de, Gabriel Fernandez ,\n Sean Anderson ,\n uboot-stm32@st-md-mailman.stormreply.com, Lukasz Majewski ,\n Grzegorz Szymaszek ","Subject":"Re: [PATCH v2 1/3] clk: Add directory for STM32 clock drivers","Message-ID":"","Mail-Followup-To":"Patrick Delaunay ,\n u-boot@lists.denx.de,\n Gabriel Fernandez ,\n Sean Anderson ,\n uboot-stm32@st-md-mailman.stormreply.com,\n Lukasz Majewski ","References":"<20220519155647.1433652-1-patrick.delaunay@foss.st.com>\n <20220519175614.v2.1.Ieec76f320c9cc6885d7b519dffddff9ad4c97b59@changeid>","MIME-Version":"1.0","Content-Type":"multipart/signed; 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