[{"id":2196427,"web_url":"http://patchwork.ozlabs.org/comment/2196427/","msgid":"<dc4b60ae-8716-0e7e-4e41-431c0ef9f50f@arm.com>","list_archive_url":null,"date":"2019-06-18T09:19:31","subject":"Re: [PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during\n\tsuspend","submitter":{"id":7353,"url":"http://patchwork.ozlabs.org/api/people/7353/","name":"Marc Zyngier","email":"marc.zyngier@arm.com"},"content":"On 18/06/2019 08:46, Sowjanya Komatineni wrote:\n> Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry\n> sequence and sc7 entry firmware is run from COP/BPMP-Lite.\n> \n> So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence\n> for Tegra210.\n> \n> This patch has fix for leaving the COP IRQ enabled for Tegra210 during\n> interrupt controller suspend operation.\n> \n> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n> ---\n>  drivers/irqchip/irq-tegra.c | 21 +++++++++++++++++++--\n>  1 file changed, 19 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/irqchip/irq-tegra.c b/drivers/irqchip/irq-tegra.c\n> index e1f771c72fc4..cf0c07052064 100644\n> --- a/drivers/irqchip/irq-tegra.c\n> +++ b/drivers/irqchip/irq-tegra.c\n> @@ -44,18 +44,22 @@ static unsigned int num_ictlrs;\n>  \n>  struct tegra_ictlr_soc {\n>  \tunsigned int num_ictlrs;\n> +\tbool supports_sc7;\n>  };\n>  \n>  static const struct tegra_ictlr_soc tegra20_ictlr_soc = {\n>  \t.num_ictlrs = 4,\n> +\t.supports_sc7 = false,\n\nnit: that's the default for a statically initialized structure.\n\n>  };\n>  \n>  static const struct tegra_ictlr_soc tegra30_ictlr_soc = {\n>  \t.num_ictlrs = 5,\n> +\t.supports_sc7 = false,\n>  };\n>  \n>  static const struct tegra_ictlr_soc tegra210_ictlr_soc = {\n>  \t.num_ictlrs = 6,\n> +\t.supports_sc7 = true,\n>  };\n>  \n>  static const struct of_device_id ictlr_matches[] = {\n> @@ -67,6 +71,7 @@ static const struct of_device_id ictlr_matches[] = {\n>  \n>  struct tegra_ictlr_info {\n>  \tvoid __iomem *base[TEGRA_MAX_NUM_ICTLRS];\n> +\tconst struct tegra_ictlr_soc *soc;\n>  #ifdef CONFIG_PM_SLEEP\n>  \tu32 cop_ier[TEGRA_MAX_NUM_ICTLRS];\n>  \tu32 cop_iep[TEGRA_MAX_NUM_ICTLRS];\n> @@ -147,8 +152,19 @@ static int tegra_ictlr_suspend(void)\n>  \t\tlic->cop_ier[i] = readl_relaxed(ictlr + ICTLR_COP_IER);\n>  \t\tlic->cop_iep[i] = readl_relaxed(ictlr + ICTLR_COP_IEP_CLASS);\n>  \n> -\t\t/* Disable COP interrupts */\n> -\t\twritel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);\n> +\t\t/*\n> +\t\t * AVP/COP/BPMP-Lite is the Tegra boot processor.\n> +\t\t *\n> +\t\t * Tegra210 system suspend flow uses sc7entry firmware which\n> +\t\t * is executed by COP/BPMP and it includes disabling COP IRQ,\n> +\t\t * clamping CPU rail, turning off VDD_CPU, and preparing the\n> +\t\t * system to go to SC7/LP0.\n> +\t\t *\n> +\t\t * COP/BPMP wakes up when COP IRQ is triggered and runs\n> +\t\t * sc7entry-firmware. So need to keep COP interrupt enabled.\n\nIt is great that you're describing what happens when the system does\nsupport this SC7 thing...\n\n> +\t\t */\n> +\t\tif (!lic->soc->supports_sc7)\n> +\t\t\twritel_relaxed(~0ul, ictlr + ICTLR_COP_IER_CLR);\n\nExcept that the code actually deals with *not* having this SC7, and\nyou've deleted the one line of comment that was explaining it.\n\n>  \n>  \t\t/* Disable CPU interrupts */\n>  \t\twritel_relaxed(~0ul, ictlr + ICTLR_CPU_IER_CLR);\n> @@ -339,6 +355,7 @@ static int __init tegra_ictlr_init(struct device_node *node,\n>  \t\tgoto out_unmap;\n>  \t}\n>  \n> +\tlic->soc = soc;\n>  \ttegra_ictlr_syscore_init();\n>  \n>  \tpr_info(\"%pOF: %d interrupts forwarded to %pOF\\n\",\n> \n\nOtherwise looks OK to me.\n\nThanks,\n\n\tM.","headers":{"Return-Path":"<linux-gpio-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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Tue, 18 Jun 2019 02:19:33 -0700 (PDT)"],"Subject":"Re: [PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during\n\tsuspend","To":"Sowjanya Komatineni <skomatineni@nvidia.com>,\n\tthierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de,\n\tjason@lakedaemon.net, linus.walleij@linaro.org, stefan@agner.ch,\n\tmark.rutland@arm.com","Cc":"pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org,\n\tlinux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,\n\tjckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tmperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org,\n\tdigetx@gmail.com, devicetree@vger.kernel.org","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-2-git-send-email-skomatineni@nvidia.com>","From":"Marc Zyngier <marc.zyngier@arm.com>","Openpgp":"preference=signencrypt","Autocrypt":"addr=marc.zyngier@arm.com; prefer-encrypt=mutual; keydata=\n\tmQINBE6Jf0UBEADLCxpix34Ch3kQKA9SNlVQroj9aHAEzzl0+V8jrvT9a9GkK+FjBOIQz4KE\n\tg+3p+lqgJH4NfwPm9H5I5e3wa+Scz9wAqWLTT772Rqb6hf6kx0kKd0P2jGv79qXSmwru28vJ\n\tt9NNsmIhEYwS5eTfCbsZZDCnR31J6qxozsDHpCGLHlYym/VbC199Uq/pN5gH+5JHZyhyZiNW\n\tozUCjMqC4eNW42nYVKZQfbj/k4W9xFfudFaFEhAf/Vb1r6F05eBP1uopuzNkAN7vqS8XcgQH\n\tqXI357YC4ToCbmqLue4HK9+2mtf7MTdHZYGZ939OfTlOGuxFW+bhtPQzsHiW7eNe0ew0+LaL\n\t3wdNzT5abPBscqXWVGsZWCAzBmrZato+Pd2bSCDPLInZV0j+rjt7MWiSxEAEowue3IcZA++7\n\tifTDIscQdpeKT8hcL+9eHLgoSDH62SlubO/y8bB1hV8JjLW/jQpLnae0oz25h39ij4ijcp8N\n\tt5slf5DNRi1NLz5+iaaLg4gaM3ywVK2VEKdBTg+JTg3dfrb3DH7ctTQquyKun9IVY8AsxMc6\n\tlxl4HxrpLX7HgF10685GG5fFla7R1RUnW5svgQhz6YVU33yJjk5lIIrrxKI/wLlhn066mtu1\n\tDoD9TEAjwOmpa6ofV6rHeBPehUwMZEsLqlKfLsl0PpsJwov8TQARAQABtCNNYXJjIFp5bmdp\n\tZXIgPG1hcmMuenluZ2llckBhcm0uY29tPokCTwQTAQIAOQIbAwYLCQgHAwIGFQgCCQoLBBYC\n\tAwECHgECF4AWIQSf1RxT4LVjGP2VnD0j0NC60T16QwUCXO+WxgAKCRAj0NC60T16QzfuEACd\n\toPsSJdUg3nm61VKq86Pp0mfCC5IVyD/vTDw3jDErsmtT7t8mMVgidSJe9cMEudLO5xske/mY\n\tsC7ZZ4GFNRRsFs3wY5g+kg4yk2UY6q18HXRQJwzWCug2bkJPUxbh71nS3KPsvq4BBOeQiTIX\n\tXr0lTyReFAp+JZ0HpanAU/iD2usEZLDNLXYLRjaHlfkwouxt02XcTKbqRWNtKl3Ybj+mz5IA\n\tqEQnA5Z8Nt9ZQmlZ4ASiXVVCbZKIR3RewBL6BP4OhYrvcPCtkoqlqKWZoHBs3ZicRXvcVUr/\n\tnqUyZpqhmfht2mIE063L3kTfBqxJ1SQqPc0ZIModTh4ATEjC44x8ObQvtnmgL8EKJBhxJfjY\n\tEUYLnwSejH1h+qgj94vn7n1RMVqXpCrWHyF7pCDBqq3gBxtDu6TWgi4iwh4CtdOzXBw2V39D\n\tLlnABnrZl5SdVbRwV+Ek1399s/laceH8e4uNea50ho89WmP9AUCrXlawHohfDE3GMOV4BdQ2\n\tDbJAtZnENQXaRK9gr86jbGQBga9VDvsBbRd+uegEmQ8nPspryWIz/gDRZLXIG8KE9Jj9OhwE\n\toiusVTLsw7KS4xKDK2Ixb/XGtJPLtUXbMM1n9YfLsB5JPZ3B08hhrv+8Vmm734yCXtxI0+7B\n\tF1V4T2njuJKWTsmJWmx+tIY8y9muUK9rabkCDQROiX9FARAAz/al0tgJaZ/eu0iI/xaPk3DK\n\tNIvr9SsKFe2hf3CVjxriHcRfoTfriycglUwtvKvhvB2Y8pQuWfLtP9Hx3H+YI5a78PO2tU1C\n\tJdY5Momd3/aJBuUFP5blbx6n+dLDepQhyQrAp2mVC3NIp4T48n4YxL4Og0MORytWNSeygISv\n\tRordw7qDmEsa7wgFsLUIlhKmmV5VVv+wAOdYXdJ9S8n+XgrxSTgHj5f3QqkDtT0yG8NMLLmY\n\tkZpOwWoMumeqn/KppPY/uTIwbYTD56q1UirDDB5kDRL626qm63nF00ByyPY+6BXH22XD8smj\n\tf2eHw2szECG/lpD4knYjxROIctdC+gLRhz+Nlf8lEHmvjHgiErfgy/lOIf+AV9lvDF3bztjW\n\tM5oP2WGeR7VJfkxcXt4JPdyDIH6GBK7jbD7bFiXf6vMiFCrFeFo/bfa39veKUk7TRlnX13go\n\tgIZxqR6IvpkG0PxOu2RGJ7Aje/SjytQFa2NwNGCDe1bH89wm9mfDW3BuZF1o2+y+eVqkPZj0\n\tmzfChEsiNIAY6KPDMVdInILYdTUAC5H26jj9CR4itBUcjE/tMll0n2wYRZ14Y/PM+UosfAhf\n\tYfN9t2096M9JebksnTbqp20keDMEBvc3KBkboEfoQLU08NDo7ncReitdLW2xICCnlkNIUQGS\n\tWlFVPcTQ2sMAEQEAAYkCHwQYAQIACQUCTol/RQIbDAAKCRAj0NC60T16QwsFD/9T4y30O0Wn\n\tMwIgcU8T2c2WwKbvmPbaU2LDqZebHdxQDemX65EZCv/NALmKdA22MVSbAaQeqsDD5KYbmCyC\n\tczilJ1i+tpZoJY5kJALHWWloI6Uyi2s1zAwlMktAZzgGMnI55Ifn0dAOK0p8oy7/KNGHNPwJ\n\teHKzpHSRgysQ3S1t7VwU4mTFJtXQaBFMMXg8rItP5GdygrFB7yUbG6TnrXhpGkFBrQs9p+SK\n\tvCqRS3Gw+dquQ9QR+QGWciEBHwuSad5gu7QC9taN8kJQfup+nJL8VGtAKgGr1AgRx/a/V/QA\n\tikDbt/0oIS/kxlIdcYJ01xuMrDXf1jFhmGZdocUoNJkgLb1iFAl5daV8MQOrqciG+6tnLeZK\n\tHY4xCBoigV7E8KwEE5yUfxBS0yRreNb+pjKtX6pSr1Z/dIo+td/sHfEHffaMUIRNvJlBeqaj\n\tBX7ZveskVFafmErkH7HC+7ErIaqoM4aOh/Z0qXbMEjFsWA5yVXvCoJWSHFImL9Bo6PbMGpI0\n\t9eBrkNa1fd6RGcktrX6KNfGZ2POECmKGLTyDC8/kb180YpDJERN48S0QBa3Rvt06ozNgFgZF\n\tWvu5Li5PpY/t/M7AAkLiVTtlhZnJWyEJrQi9O2nXTzlG1PeqGH2ahuRxn7txA5j5PHZEZdL1\n\tZ46HaNmN2hZS/oJ69c1DI5Rcww==","Organization":"ARM Ltd","Message-ID":"<dc4b60ae-8716-0e7e-4e41-431c0ef9f50f@arm.com>","Date":"Tue, 18 Jun 2019 10:19:31 +0100","User-Agent":"Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.0","MIME-Version":"1.0","In-Reply-To":"<1560843991-24123-2-git-send-email-skomatineni@nvidia.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-gpio.vger.kernel.org>","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2196543,"web_url":"http://patchwork.ozlabs.org/comment/2196543/","msgid":"<20190618105857.GD28892@ulmo>","list_archive_url":null,"date":"2019-06-18T10:58:57","subject":"Re: [PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during\n\tsuspend","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Tue, Jun 18, 2019 at 12:46:15AM -0700, Sowjanya Komatineni wrote:\n> Tegra210 platforms use sc7 entry firmware to program Tegra LP0/SC7 entry\n> sequence and sc7 entry firmware is run from COP/BPMP-Lite.\n> \n> So, COP/BPMP-Lite still need IRQ function to finish SC7 suspend sequence\n> for Tegra210.\n> \n> This patch has fix for leaving the COP IRQ enabled for Tegra210 during\n> interrupt controller suspend operation.\n> \n> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n> ---\n>  drivers/irqchip/irq-tegra.c | 21 +++++++++++++++++++--\n>  1 file changed, 19 insertions(+), 2 deletions(-)\n\nAcked-by: Thierry Reding <treding@nvidia.com>","headers":{"Return-Path":"<linux-gpio-owner@vger.kernel.org>","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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[46.91.239.54])\n\tby smtp.gmail.com with ESMTPSA id\n\tl1sm1930397wmg.13.2019.06.18.03.58.58\n\t(version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256);\n\tTue, 18 Jun 2019 03:58:58 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=erWl2ztGQC1+LMUU2GDgbAUN0dxGbS3XfDl1jE6l2ow=;\n\tb=vEKCtOARKjx5EDFmxAJP5qqdrxjSakRCZS/TgKM4RtapEG3kuF3EcgT+PH7T7Et5xP\n\tYFmWyPUzNyz/Sikfrd2Wvs40djchhc4QsPzZFtFYyvgb6MmHE6gVCk2iSkxw/iFYYAB2\n\tDiqR/87gvY86T+U12boAwdwwjhnXBlsraE2LNmc/5SVXbQ259vZ3kym0MHWOzSsNGg4/\n\trDCrjn4s2Op1omFqMkOwkdQF4QzgQnymUDW9oSFeC3YCHPSwjxmZYUUzDMhSL5kdCIXj\n\ts5YZLLa7iVK+sg56EJFDFhGVN09zKD0Pla3p/go1FbagxfZnqlyQpfcMiPHyUIKYA/bI\n\tG2qw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=erWl2ztGQC1+LMUU2GDgbAUN0dxGbS3XfDl1jE6l2ow=;\n\tb=gmg5204szueOsUlOSb7aV8zd9Z91VtoNjanULaRk0vkOb8vxPrAB5jGgtBn/3m3oaY\n\tgDv5dB71bL2BX3J/NQaPXsWfT1ZkufciIlptT5pEH3yN6xSLDjKrTWf33EV8oIfugTpx\n\tm7p85PT3Q3w/uObDawqkajwCWrLy2BKTWxpebV7UpAeFSa2zowIOlq2iWwZYsSQXq9GZ\n\tTvH4lY1XoU+aUn/wwHVKmWro/ewzrUWSvrweRafqZ7GgazpHVvaK31f8ZhDk/QtpEfZx\n\tOOI5oOokPTza5R/qdR5jI09B4lEc5BaILyW5yuewoPeDe3qP/FFem4S4rVy/t1RLEk+j\n\t6LWw==","X-Gm-Message-State":"APjAAAVifWmQQ4PXz5uBsUXOP1rVFKUkklbi4+XP8p8tk+tPOpnkGsKW\n\tFPA1NVAoimB9lbgFvtPGwws=","X-Google-Smtp-Source":"APXvYqyrCJUtg1gqiMWv2NhNK6EU8WMp4kmrJ0w+oq+L1m8gW/h13kuBpFPjrwh8Cp3+wVCytRNK9g==","X-Received":"by 2002:a5d:4a90:: with SMTP id\n\to16mr22664381wrq.13.1560855539430; \n\tTue, 18 Jun 2019 03:58:59 -0700 (PDT)","Date":"Tue, 18 Jun 2019 12:58:57 +0200","From":"Thierry Reding <thierry.reding@gmail.com>","To":"Sowjanya Komatineni <skomatineni@nvidia.com>","Cc":"jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net,\n\tmarc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch,\n\tmark.rutland@arm.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com,\n\tsboyd@kernel.org, linux-clk@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com,\n\ttalho@nvidia.com, linux-tegra@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, mperttunen@nvidia.com,\n\tspatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com,\n\tdevicetree@vger.kernel.org","Subject":"Re: [PATCH V3 01/17] irqchip: tegra: do not disable COP IRQ during\n\tsuspend","Message-ID":"<20190618105857.GD28892@ulmo>","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-2-git-send-email-skomatineni@nvidia.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"RhUH2Ysw6aD5utA4\"","Content-Disposition":"inline","In-Reply-To":"<1560843991-24123-2-git-send-email-skomatineni@nvidia.com>","User-Agent":"Mutt/1.11.4 (2019-03-13)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<linux-gpio.vger.kernel.org>","X-Mailing-List":"linux-gpio@vger.kernel.org"}}]