[{"id":2196589,"web_url":"http://patchwork.ozlabs.org/comment/2196589/","msgid":"<20190618114554.GI28892@ulmo>","list_archive_url":null,"date":"2019-06-18T11:45:54","subject":"Re: [PATCH V3 06/17] clk: tegra: pll: save and restore pll context","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Tue, Jun 18, 2019 at 12:46:20AM -0700, Sowjanya Komatineni wrote:\n> This patch implements save and restore of pll context.\n> \n> During system suspend, core power goes off and looses the settings\n> of the Tegra CAR controller registers.\n> \n> So during suspend entry pll rate is stored and on resume it is\n> restored back along with its state.\n> \n> Signed-off-by: Sowjanya Komatineni \n> ---\n> drivers/clk/tegra/clk-pll.c | 115 ++++++++++++++++++++++++++++++++------------\n> drivers/clk/tegra/clk.h | 6 ++-\n> 2 files changed, 88 insertions(+), 33 deletions(-)\n\nNit: s/pll/PLL/ in the commit message, but it's up to Stephen and Mike\nhow important they consider this to be, so:\n\nAcked-by: Thierry Reding ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=gmail.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"ZF1zVPeh\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SmVy6WZfz9sBr\n\tfor ;\n\tTue, 18 Jun 2019 21:46:02 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729801AbfFRLp7 (ORCPT );\n\tTue, 18 Jun 2019 07:45:59 -0400","from mail-wm1-f66.google.com ([209.85.128.66]:54349 \"EHLO\n\tmail-wm1-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1729662AbfFRLp7 (ORCPT\n\t); Tue, 18 Jun 2019 07:45:59 -0400","by mail-wm1-f66.google.com with SMTP id g135so2883221wme.4;\n\tTue, 18 Jun 2019 04:45:57 -0700 (PDT)","from localhost (p2E5BEF36.dip0.t-ipconnect.de. [46.91.239.54])\n\tby smtp.gmail.com with ESMTPSA id\n\tr12sm21351821wrt.95.2019.06.18.04.45.55\n\t(version=TLS1_3 cipher=AEAD-AES256-GCM-SHA384 bits=256/256);\n\tTue, 18 Jun 2019 04:45:55 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=Hmk5A34hevTih65ONqJk6gJ3pW2w0gAUTQ6jMje+Uj4=;\n\tb=ZF1zVPehgmfyehYR+cbzThXdlcZDCmrJIyuLRSJ1IrMHRkDsD3ct6BMuzP9MWo6A0j\n\tIR0IvIXMGr5Zpqdnjh9lOKG6sszGMQz1K/AZF3MrCB0GBcI3nVAeFzU9uQimqi8A0OpS\n\tqMEt/pkg0PMyGu6S0lgq1ccT3QtCx043WpEWu6iqevbImPEgfKEi6ADUXjaKx+LAdtXZ\n\tXrUC4sYz5al+ZtiQs28dPeesPssBcQq+3AXN8Rz/jyK5YJ+kMPH3P4VCN2BfNYij8K1N\n\tiutBW8CMsQo/EKS4HXH5Wulm21BzfdDNWnyzkQI3fvqW9a6xbULi4AGiJW7UzDQ5oQ4q\n\tWxtg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=Hmk5A34hevTih65ONqJk6gJ3pW2w0gAUTQ6jMje+Uj4=;\n\tb=raRG74tUZBr8R8dR8YvaTh1c74QmWdj6W92yVQA7Xo9ZtJ2yF0wOCXF8ij/JjsUkUH\n\tEMRORH9e6/1X5FKalO/aPA5n5eVTjtR0K8TOCqCWAL4nq3sem4CW986EWr7BHOZSmRU/\n\t4TzQNUFPT41z8M2+ZtzzG8ptYo322VEc0oxNq4P/MCritjTDDN+hIeaKE/bGA3FrO51D\n\tIyaXCCDuHamyeoDc0ltK2adIAbRY4HycurFqfQUDl5BXYqNthQ1Cx7Q9CJNaP380noXG\n\takHk4aAehBoL5MefKvXORxkKRRIV+eqQkY6Mmk65LGwAsP0HDiETWnUOjqIf1xKRdiMK\n\t4LHA==","X-Gm-Message-State":"APjAAAVtBs/26whddzzImXVUtpc1cqKtVO6gG3H5Yb/quFoPD/j4mLh5\n\tDEW+NDg3qBjntU9hRDNvO8Q=","X-Google-Smtp-Source":"APXvYqz3MAaHI3dRTEdsjIx4qOUPlTViVmJqHguDFGORtVNrPF/Y+Tzi5GZjf/61Y3+7LKPOcdwPOg==","X-Received":"by 2002:a1c:f001:: with SMTP id a1mr3427859wmb.130.1560858356319;\n\tTue, 18 Jun 2019 04:45:56 -0700 (PDT)","Date":"Tue, 18 Jun 2019 13:45:54 +0200","From":"Thierry Reding ","To":"Sowjanya Komatineni ","Cc":"jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net,\n\tmarc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch,\n\tmark.rutland@arm.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com,\n\tsboyd@kernel.org, linux-clk@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com,\n\ttalho@nvidia.com, linux-tegra@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, mperttunen@nvidia.com,\n\tspatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com,\n\tdevicetree@vger.kernel.org","Subject":"Re: [PATCH V3 06/17] clk: tegra: pll: save and restore pll context","Message-ID":"<20190618114554.GI28892@ulmo>","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-7-git-send-email-skomatineni@nvidia.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"wjoFZxbW4tu+iR6v\"","Content-Disposition":"inline","In-Reply-To":"<1560843991-24123-7-git-send-email-skomatineni@nvidia.com>","User-Agent":"Mutt/1.11.4 (2019-03-13)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2202861,"web_url":"http://patchwork.ozlabs.org/comment/2202861/","msgid":"<20190625204640.D640E205ED@mail.kernel.org>","list_archive_url":null,"date":"2019-06-25T20:46:40","subject":"Re: [PATCH V3 06/17] clk: tegra: pll: save and restore pll context","submitter":{"id":73546,"url":"http://patchwork.ozlabs.org/api/people/73546/","name":"Stephen Boyd","email":"sboyd@kernel.org"},"content":"Quoting Sowjanya Komatineni (2019-06-18 00:46:20)\n> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c\n> index 1583f5fc992f..4b0ed8fc6268 100644\n> --- a/drivers/clk/tegra/clk-pll.c\n> +++ b/drivers/clk/tegra/clk-pll.c\n> @@ -1008,6 +1008,54 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,\n> return rate;\n> }\n> \n> +void tegra_clk_sync_state_pll(struct clk_hw *hw)\n> +{\n> + if (!__clk_get_enable_count(hw->clk))\n> + clk_pll_disable(hw);\n> + else\n> + clk_pll_enable(hw);\n> +}\n> +\n> +static int tegra_clk_pll_save_context(struct clk_hw *hw)\n> +{\n> + struct tegra_clk_pll *pll = to_clk_pll(hw);\n> +\n> + pll->rate = clk_hw_get_rate(hw);\n> +\n> + if (!strcmp(__clk_get_name(hw->clk), \"pll_mb\"))\n> + pll->pllbase_ctx = pll_readl_base(pll);\n> + else if (!strcmp(__clk_get_name(hw->clk), \"pll_re_vco\"))\n> + pll->pllbase_ctx = pll_readl_base(pll) & (0xf << 16);\n> +\n> + return 0;\n> +}\n> +\n> +static void tegra_clk_pll_restore_context(struct clk_hw *hw)\n> +{\n> + struct tegra_clk_pll *pll = to_clk_pll(hw);\n> + u32 val;\n> +\n> + if (clk_pll_is_enabled(hw))\n> + return;\n> +\n> + if (!strcmp(__clk_get_name(hw->clk), \"pll_mb\")) {\n\nIs there any way to avoid doing a string comparison here, and instead do\nsomething like a pointer comparison? Or maybe look at some flag in the\ntegra_clk_pll to figure out what to do differently? Using a string\ncomparison is not too nice. Or even have different clk ops for the\ndifferent clks and then do different things in this restore clk_op?\n\n> + pll_writel_base(pll->pllbase_ctx, pll);\n> + } else if (!strcmp(__clk_get_name(hw->clk), \"pll_re_vco\")) {\n> + val = pll_readl_base(pll);\n> + val &= ~(0xf << 16);\n> + pll_writel_base(pll->pllbase_ctx | val, pll);\n> + }\n> +\n> + if (pll->params->set_defaults)\n> + pll->params->set_defaults(pll);\n> +\n> + clk_set_rate(hw->clk, pll->rate);\n\nDo you need to call clk_set_rate() here to change the frequency of the\nclk or just the parents of the clk, or both? I'd think that when we're\nrestoring the clk the cached rate of the clk would match whatever we're\nrestoring to, so this is a NOP. So does this do anything?\n\nI'd prefer that the restore ops just restore the clk hardware state of\nthe clk_hw passed in, and not try to fix up the entire tree around a\ncertain clk, if that's even possible.\n\n> +\n> + /* do not sync pllx state here. pllx is sync'd after dfll resume */\n> + if (strcmp(__clk_get_name(hw->clk), \"pll_x\"))\n> + tegra_clk_sync_state_pll(hw);\n> +}\n> +\n> const struct clk_ops tegra_clk_pll_ops = {\n> .is_enabled = clk_pll_is_enabled,\n> .enable = clk_pll_enable,\n> @@ -1015,6 +1063,8 @@ const struct clk_ops tegra_clk_pll_ops = {\n> .recalc_rate = clk_pll_recalc_rate,\n> .round_rate = clk_pll_round_rate,\n> .set_rate = clk_pll_set_rate,\n> + .save_context = tegra_clk_pll_save_context,\n> + .restore_context = tegra_clk_pll_restore_context,","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=kernel.org","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=kernel.org header.i=@kernel.org\n\theader.b=\"1IBQKZ4Q\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45YJ9b4Vygz9s3l\n\tfor ;\n\tWed, 26 Jun 2019 06:46:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1726761AbfFYUqm (ORCPT );\n\tTue, 25 Jun 2019 16:46:42 -0400","from mail.kernel.org ([198.145.29.99]:43984 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1726053AbfFYUqm (ORCPT );\n\tTue, 25 Jun 2019 16:46:42 -0400","from kernel.org (unknown [104.132.0.74])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id D640E205ED;\n\tTue, 25 Jun 2019 20:46:40 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=default; t=1561495600;\n\tbh=4zflnPJOjSzJah74cHqrZgjnWn4XRJGSe8xqS8yMJt4=;\n\th=In-Reply-To:References:To:From:Subject:Cc:Date:From;\n\tb=1IBQKZ4QdO9mARvZO4fdimMmjFiTYyPvYCcleQH84/+xvmlxpz2ZLt+7vlYvJO/Rd\n\tMetUEuXkt6V+Mf82FiEQb7OL3AjJEWviaNLdmYjswYyq7kIa5yAPxZ9jVKnmPmdfBU\n\t+uvHaijX0g2RMbCAesFySwxy8qll5906VdBCxCO8=","Content-Type":"text/plain; charset=\"utf-8\"","MIME-Version":"1.0","Content-Transfer-Encoding":"quoted-printable","In-Reply-To":"<1560843991-24123-7-git-send-email-skomatineni@nvidia.com>","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-7-git-send-email-skomatineni@nvidia.com>","To":"Sowjanya Komatineni , jason@lakedaemon.net,\n\tjonathanh@nvidia.com, linus.walleij@linaro.org,\n\tmarc.zyngier@arm.com, mark.rutland@arm.com, stefan@agner.ch,\n\ttglx@linutronix.de, thierry.reding@gmail.com","From":"Stephen Boyd ","Subject":"Re: [PATCH V3 06/17] clk: tegra: pll: save and restore pll context","Cc":"pdeschrijver@nvidia.com, pgaikwad@nvidia.com,\n\tlinux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,\n\tjckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,\n\tskomatineni@nvidia.com, linux-tegra@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, mperttunen@nvidia.com,\n\tspatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com,\n\tdevicetree@vger.kernel.org","User-Agent":"alot/0.8.1","Date":"Tue, 25 Jun 2019 13:46:40 -0700","Message-Id":"<20190625204640.D640E205ED@mail.kernel.org>","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2202906,"web_url":"http://patchwork.ozlabs.org/comment/2202906/","msgid":"<1d34f117-9882-7e11-9641-90f3b7ebc273@nvidia.com>","list_archive_url":null,"date":"2019-06-25T21:22:43","subject":"Re: [PATCH V3 06/17] clk: tegra: pll: save and restore pll context","submitter":{"id":75554,"url":"http://patchwork.ozlabs.org/api/people/75554/","name":"Sowjanya Komatineni","email":"skomatineni@nvidia.com"},"content":"On 6/25/19 1:46 PM, Stephen Boyd wrote:\n> Quoting Sowjanya Komatineni (2019-06-18 00:46:20)\n>> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c\n>> index 1583f5fc992f..4b0ed8fc6268 100644\n>> --- a/drivers/clk/tegra/clk-pll.c\n>> +++ b/drivers/clk/tegra/clk-pll.c\n>> @@ -1008,6 +1008,54 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,\n>> return rate;\n>> }\n>> \n>> +void tegra_clk_sync_state_pll(struct clk_hw *hw)\n>> +{\n>> + if (!__clk_get_enable_count(hw->clk))\n>> + clk_pll_disable(hw);\n>> + else\n>> + clk_pll_enable(hw);\n>> +}\n>> +\n>> +static int tegra_clk_pll_save_context(struct clk_hw *hw)\n>> +{\n>> + struct tegra_clk_pll *pll = to_clk_pll(hw);\n>> +\n>> + pll->rate = clk_hw_get_rate(hw);\n>> +\n>> + if (!strcmp(__clk_get_name(hw->clk), \"pll_mb\"))\n>> + pll->pllbase_ctx = pll_readl_base(pll);\n>> + else if (!strcmp(__clk_get_name(hw->clk), \"pll_re_vco\"))\n>> + pll->pllbase_ctx = pll_readl_base(pll) & (0xf << 16);\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +static void tegra_clk_pll_restore_context(struct clk_hw *hw)\n>> +{\n>> + struct tegra_clk_pll *pll = to_clk_pll(hw);\n>> + u32 val;\n>> +\n>> + if (clk_pll_is_enabled(hw))\n>> + return;\n>> +\n>> + if (!strcmp(__clk_get_name(hw->clk), \"pll_mb\")) {\n> Is there any way to avoid doing a string comparison here, and instead do\n> something like a pointer comparison? Or maybe look at some flag in the\n> tegra_clk_pll to figure out what to do differently? Using a string\n> comparison is not too nice. Or even have different clk ops for the\n> different clks and then do different things in this restore clk_op?\nOK, Will update...\n>> + pll_writel_base(pll->pllbase_ctx, pll);\n>> + } else if (!strcmp(__clk_get_name(hw->clk), \"pll_re_vco\")) {\n>> + val = pll_readl_base(pll);\n>> + val &= ~(0xf << 16);\n>> + pll_writel_base(pll->pllbase_ctx | val, pll);\n>> + }\n>> +\n>> + if (pll->params->set_defaults)\n>> + pll->params->set_defaults(pll);\n>> +\n>> + clk_set_rate(hw->clk, pll->rate);\n> Do you need to call clk_set_rate() here to change the frequency of the\n> clk or just the parents of the clk, or both? I'd think that when we're\n> restoring the clk the cached rate of the clk would match whatever we're\n> restoring to, so this is a NOP. So does this do anything?\n>\n> I'd prefer that the restore ops just restore the clk hardware state of\n> the clk_hw passed in, and not try to fix up the entire tree around a\n> certain clk, if that's even possible.\n\nOn restore, need to program tegra plls rate back to the same rate as \nthey were before suspend, so I am calling clk_set_rate to program pll \nm,n,p values in hw registers.\n\n>> +\n>> + /* do not sync pllx state here. pllx is sync'd after dfll resume */\n>> + if (strcmp(__clk_get_name(hw->clk), \"pll_x\"))\n>> + tegra_clk_sync_state_pll(hw);\n>> +}\n>> +\n>> const struct clk_ops tegra_clk_pll_ops = {\n>> .is_enabled = clk_pll_is_enabled,\n>> .enable = clk_pll_enable,\n>> @@ -1015,6 +1063,8 @@ const struct clk_ops tegra_clk_pll_ops = {\n>> .recalc_rate = clk_pll_recalc_rate,\n>> .round_rate = clk_pll_round_rate,\n>> .set_rate = clk_pll_set_rate,\n>> + .save_context = tegra_clk_pll_save_context,\n>> + .restore_context = tegra_clk_pll_restore_context,","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"Y4N840op\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45YJzG5R8bz9s4V\n\tfor ;\n\tWed, 26 Jun 2019 07:22:50 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1726287AbfFYVWp (ORCPT );\n\tTue, 25 Jun 2019 17:22:45 -0400","from hqemgate16.nvidia.com ([216.228.121.65]:8463 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1725290AbfFYVWp (ORCPT\n\t); Tue, 25 Jun 2019 17:22:45 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid ; Tue, 25 Jun 2019 14:22:42 -0700","from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 25 Jun 2019 14:22:43 -0700","from [10.110.103.70] (172.20.13.39) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 25 Jun 2019 21:22:42 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 25 Jun 2019 14:22:43 -0700","Subject":"Re: [PATCH V3 06/17] clk: tegra: pll: save and restore pll context","To":"Stephen Boyd , ,\n\t, ,\n\t, , ,\n\t, ","CC":", ,\n\t, ,\n\t, , ,\n\t, ,\n\t, , ,\n\t, ","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-7-git-send-email-skomatineni@nvidia.com>\n\t<20190625204640.D640E205ED@mail.kernel.org>","From":"Sowjanya Komatineni ","Message-ID":"<1d34f117-9882-7e11-9641-90f3b7ebc273@nvidia.com>","Date":"Tue, 25 Jun 2019 14:22:43 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.1","MIME-Version":"1.0","In-Reply-To":"<20190625204640.D640E205ED@mail.kernel.org>","X-Originating-IP":"[172.20.13.39]","X-ClientProxiedBy":"HQMAIL107.nvidia.com (172.20.187.13) To\n\tHQMAIL107.nvidia.com (172.20.187.13)","Content-Type":"text/plain; charset=\"utf-8\"; format=flowed","Content-Transfer-Encoding":"7bit","Content-Language":"en-US","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1561497762; bh=hQq9zJfXZXl1rOsdFRIeo5nPIVHqhZjlNT3Q2VrPlQk=;\n\th=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date:\n\tUser-Agent:MIME-Version:In-Reply-To:X-Originating-IP:\n\tX-ClientProxiedBy:Content-Type:Content-Transfer-Encoding:\n\tContent-Language;\n\tb=Y4N840opIgVuHmpvaOTFetAl+QpI9mntDy4WT4f5UR/ubLzxtJhZTTQgN5os097Bp\n\tYOkxmqmMAkCJOUEMKC/rRPumaNf9mkF3tDJ6QGGQxFUGj8eO/vZIzFVzsQyQn95P/l\n\t/W/IPMLBEQdM9FsZFgHzPZ/ZfjFU1u/iip5/9bmNKqAM7EDivgyI0VL2EXs7OouQMA\n\tWy+A9tqV8wvHucn6G/aCLIKE6ziAeJlpsa07+DHt01Lb0I/tAjzTTr9vZMsJUKTRz/\n\t9R0tjhcuSXnPgNdV5yScRySul2vMkvKy62Zf4AKLl9GJxK1DjPyIOYWdOuHjPObkn/\n\tNIhrvn25PM/Lg==","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}}]