[{"id":2196602,"web_url":"http://patchwork.ozlabs.org/comment/2196602/","msgid":"<20190618115055.GK28892@ulmo>","list_archive_url":null,"date":"2019-06-18T11:50:55","subject":"Re: [PATCH V3 08/17] clk: tegra: add support for peripheral clock\n\tsuspend and resume","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Tue, Jun 18, 2019 at 12:46:22AM -0700, Sowjanya Komatineni wrote:\n> This patch creates APIs to save and restore the state of all\n> peripheral clocks reset and enables.\n> \n> These APIs are invoked by Tegra210 clock driver during suspend and\n> resume to save the peripheral clocks state before suspend and to\n> restore them on resume.\n> \n> Signed-off-by: Sowjanya Komatineni \n> ---\n> drivers/clk/tegra/clk.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++-\n> drivers/clk/tegra/clk.h | 3 +++\n> 2 files changed, 72 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c\n> index 26690663157a..bd3b46c5f941 100644\n> --- a/drivers/clk/tegra/clk.c\n> +++ b/drivers/clk/tegra/clk.c\n> @@ -70,6 +70,7 @@ static struct clk **clks;\n> static int clk_num;\n> static struct clk_onecell_data clk_data;\n> \n> +static u32 *periph_ctx;\n> static u32 cclkg_burst_policy_ctx[2];\n> static u32 cclklp_burst_policy_ctx[2];\n> static u32 sclk_burst_policy_ctx[2];\n> @@ -279,6 +280,63 @@ void tegra_sclk_cpulp_burst_policy_restore_context(void)\n> \twritel_relaxed(clk_arm_ctx, clk_base + CLK_MASK_ARM);\n> }\n> \n> +void tegra_clk_periph_suspend(void __iomem *clk_base)\n> +{\n> +\tint i, idx;\n\nCan be unsigned int. Same for below.\n\n> +\n> +\tidx = 0;\n> +\tfor (i = 0; i < periph_banks; i++, idx++)\n> +\t\tperiph_ctx[idx] =\n> +\t\t\treadl_relaxed(clk_base + periph_regs[i].rst_reg);\n> +\n> +\tfor (i = 0; i < periph_banks; i++, idx++)\n> +\t\tperiph_ctx[idx] =\n> +\t\t\treadl_relaxed(clk_base + periph_regs[i].enb_reg);\n> +}\n> +\n> +void tegra_clk_periph_force_on(u32 *clks_on, int count, void __iomem *clk_base)\n\ncount can also be unsigned int.\n\n> +{\n> +\tint i;\n> +\n> +\tWARN_ON(count != periph_banks);\n> +\n> +\tfor (i = 0; i < count; i++)\n> +\t\twritel_relaxed(clks_on[i], clk_base + periph_regs[i].enb_reg);\n> +}\n> +\n> +void tegra_clk_periph_resume(void __iomem *clk_base)\n> +{\n> +\tint i, idx;\n> +\n> +\tidx = 0;\n> +\tfor (i = 0; i < periph_banks; i++, idx++)\n> +\t\twritel_relaxed(periph_ctx[idx],\n> +\t\t\t clk_base + periph_regs[i].rst_reg);\n> +\n> +\t/* ensure all resets have propagated */\n> +\tfence_udelay(2, clk_base);\n> +\ttegra_read_chipid();\n> +\n> +\tfor (i = 0; i < periph_banks; i++, idx++)\n> +\t\twritel_relaxed(periph_ctx[idx],\n> +\t\t\t clk_base + periph_regs[i].enb_reg);\n> +\n> +\t/* ensure all enables have propagated */\n> +\tfence_udelay(2, clk_base);\n> +\ttegra_read_chipid();\n> +}\n> +\n> +static int tegra_clk_suspend_ctx_init(int banks)\n> +{\n> +\tint err = 0;\n> +\n> +\tperiph_ctx = kcalloc(2 * banks, sizeof(*periph_ctx), GFP_KERNEL);\n> +\tif (!periph_ctx)\n> +\t\terr = -ENOMEM;\n> +\n> +\treturn err;\n> +}\n> +\n> struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)\n> {\n> \tclk_base = regs;\n> @@ -295,11 +353,21 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)\n> \tperiph_banks = banks;\n> \n> \tclks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL);\n> -\tif (!clks)\n> +\tif (!clks) {\n> \t\tkfree(periph_clk_enb_refcnt);\n> +\t\treturn NULL;\n> +\t}\n> \n> \tclk_num = num;\n> \n> +\tif (IS_ENABLED(CONFIG_PM_SLEEP)) {\n> +\t\tif (tegra_clk_suspend_ctx_init(banks)) {\n> +\t\t\tkfree(periph_clk_enb_refcnt);\n> +\t\t\tkfree(clks);\n> +\t\t\treturn NULL;\n> +\t\t}\n> +\t}\n> +\n> \treturn clks;\n> }\n> \n> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\n> index c8f8a23096e2..a354cacae5a6 100644\n> --- a/drivers/clk/tegra/clk.h\n> +++ b/drivers/clk/tegra/clk.h\n> @@ -853,6 +853,9 @@ void tegra_cclkg_burst_policy_save_context(void);\n> void tegra_cclkg_burst_policy_restore_context(void);\n> void tegra_sclk_cclklp_burst_policy_save_context(void);\n> void tegra_sclk_cpulp_burst_policy_restore_context(void);\n> +void tegra_clk_periph_suspend(void __iomem *clk_base);\n> +void tegra_clk_periph_resume(void __iomem *clk_base);\n> +void tegra_clk_periph_force_on(u32 *clks_on, int count, void __iomem *clk_base);\n> \n> /* Combined read fence with delay */\n> #define fence_udelay(delay, reg)\t\\\n\nOther than the nitpicks, looks good:\n\nAcked-by: Thierry Reding ","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=gmail.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"vcUy7JtA\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45Smcj2wgmz9s3C\n\tfor ;\n\tTue, 18 Jun 2019 21:51:01 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729738AbfFRLvA (ORCPT );\n\tTue, 18 Jun 2019 07:51:00 -0400","from mail-wm1-f66.google.com ([209.85.128.66]:51782 \"EHLO\n\tmail-wm1-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1729662AbfFRLvA (ORCPT\n\t); Tue, 18 Jun 2019 07:51:00 -0400","by mail-wm1-f66.google.com with SMTP id 207so2921367wma.1;\n\tTue, 18 Jun 2019 04:50:58 -0700 (PDT)","from localhost (p2E5BEF36.dip0.t-ipconnect.de. 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