[{"id":2196434,"web_url":"http://patchwork.ozlabs.org/comment/2196434/","msgid":"<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>","list_archive_url":null,"date":"2019-06-18T09:22:50","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"18.06.2019 10:46, Sowjanya Komatineni пишет:\n> This patch adds suspend and resume support for Tegra pinctrl driver\n> and registers them to syscore so the pinmux settings are restored\n> before the devices resume.\n> \n> Signed-off-by: Sowjanya Komatineni \n> ---\n> drivers/pinctrl/tegra/pinctrl-tegra.c | 62 ++++++++++++++++++++++++++++++++\n> drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +++\n> drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 +\n> drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 +\n> drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 +\n> drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n> drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 +\n> 7 files changed, 84 insertions(+)\n> \n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> index 34596b246578..ceced30d8bd1 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> @@ -20,11 +20,16 @@\n> #include \n> #include \n> #include \n> +#include \n> \n> #include \"../core.h\"\n> #include \"../pinctrl-utils.h\"\n> #include \"pinctrl-tegra.h\"\n> \n> +#define EMMC2_PAD_CFGPADCTRL_0\t\t\t0x1c8\n> +#define EMMC4_PAD_CFGPADCTRL_0\t\t\t0x1e0\n> +#define EMMC_DPD_PARKING\t\t\t(0x1fff << 14)\n> +\n> static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n> {\n> \treturn readl(pmx->regs[bank] + reg);\n> @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n> \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n> \t\t}\n> \t}\n> +\n> +\tif (pmx->soc->has_park_padcfg) {\n> +\t\tval = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n> +\t\tval &= ~EMMC_DPD_PARKING;\n> +\t\tpmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n> +\n> +\t\tval = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n> +\t\tval &= ~EMMC_DPD_PARKING;\n> +\t\tpmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n> +\t}\n> +}\n\nIs there any reason why parked_bit can't be changed to parked_bitmask like I was\nasking in a comment to v2?\n\nI suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for\nconsistency when possible, hence adding platform specifics here should be discouraged.\nAnd then the parked_bitmask will also result in a proper hardware description in the code.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tTue, 18 Jun 2019 02:22:52 -0700 (PDT)","Subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","To":"Sowjanya Komatineni ,\n\tthierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de,\n\tjason@lakedaemon.net, marc.zyngier@arm.com,\n\tlinus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com","Cc":"pdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org,\n\tlinux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,\n\tjckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tmperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>","From":"Dmitry Osipenko ","Message-ID":"<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>","Date":"Tue, 18 Jun 2019 12:22:50 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.1","MIME-Version":"1.0","In-Reply-To":"<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2196444,"web_url":"http://patchwork.ozlabs.org/comment/2196444/","msgid":"","list_archive_url":null,"date":"2019-06-18T09:30:39","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"18.06.2019 12:22, Dmitry Osipenko пишет:\n> 18.06.2019 10:46, Sowjanya Komatineni пишет:\n>> This patch adds suspend and resume support for Tegra pinctrl driver\n>> and registers them to syscore so the pinmux settings are restored\n>> before the devices resume.\n>>\n>> Signed-off-by: Sowjanya Komatineni \n>> ---\n>> drivers/pinctrl/tegra/pinctrl-tegra.c | 62 ++++++++++++++++++++++++++++++++\n>> drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +++\n>> drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 +\n>> drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 +\n>> drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 +\n>> drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n>> drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 +\n>> 7 files changed, 84 insertions(+)\n>>\n>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>> index 34596b246578..ceced30d8bd1 100644\n>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>> @@ -20,11 +20,16 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> \n>> #include \"../core.h\"\n>> #include \"../pinctrl-utils.h\"\n>> #include \"pinctrl-tegra.h\"\n>> \n>> +#define EMMC2_PAD_CFGPADCTRL_0\t\t\t0x1c8\n>> +#define EMMC4_PAD_CFGPADCTRL_0\t\t\t0x1e0\n>> +#define EMMC_DPD_PARKING\t\t\t(0x1fff << 14)\n>> +\n>> static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n>> {\n>> \treturn readl(pmx->regs[bank] + reg);\n>> @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n>> \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n>> \t\t}\n>> \t}\n>> +\n>> +\tif (pmx->soc->has_park_padcfg) {\n>> +\t\tval = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n>> +\t\tval &= ~EMMC_DPD_PARKING;\n>> +\t\tpmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n>> +\n>> +\t\tval = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n>> +\t\tval &= ~EMMC_DPD_PARKING;\n>> +\t\tpmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n>> +\t}\n>> +}\n> \n> Is there any reason why parked_bit can't be changed to parked_bitmask like I was\n> asking in a comment to v2?\n> \n> I suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for\n> consistency when possible, hence adding platform specifics here should be discouraged.\n> And then the parked_bitmask will also result in a proper hardware description in the code.\n> \n\nI'm now also vaguely recalling that Stephen Warren had some kind of a \"code generator\"\nfor the pinctrl drivers. So I guess all those tables were auto-generated initially.\n\nStephen, maybe you could adjust the generator to take into account the bitmask (of\ncourse if that's a part of the generated code) and then re-gen it all for Sowjanya?","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=gmail.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"IOehSmar\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SjVy3dVwz9sCJ\n\tfor ;\n\tTue, 18 Jun 2019 19:30:50 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729541AbfFRJap (ORCPT );\n\tTue, 18 Jun 2019 05:30:45 -0400","from mail-lj1-f195.google.com ([209.85.208.195]:35413 \"EHLO\n\tmail-lj1-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1726330AbfFRJao (ORCPT\n\t); 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Linux x86_64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.1","MIME-Version":"1.0","In-Reply-To":"<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2196560,"web_url":"http://patchwork.ozlabs.org/comment/2196560/","msgid":"<20190618113109.GE28892@ulmo>","list_archive_url":null,"date":"2019-06-18T11:31:09","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Tue, Jun 18, 2019 at 12:46:16AM -0700, Sowjanya Komatineni wrote:\n> This patch adds suspend and resume support for Tegra pinctrl driver\n> and registers them to syscore so the pinmux settings are restored\n> before the devices resume.\n\nThis no longer uses syscore ops, so you need to reflect that in the\ncommit message.\n\n> \n> Signed-off-by: Sowjanya Komatineni \n> ---\n> drivers/pinctrl/tegra/pinctrl-tegra.c | 62 ++++++++++++++++++++++++++++++++\n> drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +++\n> drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 +\n> drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 +\n> drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 +\n> drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n> drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 +\n> 7 files changed, 84 insertions(+)\n> \n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> index 34596b246578..ceced30d8bd1 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> @@ -20,11 +20,16 @@\n> #include \n> #include \n> #include \n> +#include \n\nNo longer needed.\n\n> \n> #include \"../core.h\"\n> #include \"../pinctrl-utils.h\"\n> #include \"pinctrl-tegra.h\"\n> \n> +#define EMMC2_PAD_CFGPADCTRL_0\t\t\t0x1c8\n> +#define EMMC4_PAD_CFGPADCTRL_0\t\t\t0x1e0\n> +#define EMMC_DPD_PARKING\t\t\t(0x1fff << 14)\n> +\n> static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n> {\n> \treturn readl(pmx->regs[bank] + reg);\n> @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n> \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n> \t\t}\n> \t}\n> +\n> +\tif (pmx->soc->has_park_padcfg) {\n> +\t\tval = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n> +\t\tval &= ~EMMC_DPD_PARKING;\n> +\t\tpmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n> +\n> +\t\tval = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n> +\t\tval &= ~EMMC_DPD_PARKING;\n> +\t\tpmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n> +\t}\n> +}\n> +\n> +int __maybe_unused tegra_pinctrl_suspend(struct device *dev)\n> +{\n> +\tstruct tegra_pmx *pmx = dev_get_drvdata(dev);\n> +\tu32 *backup_regs = pmx->backup_regs;\n> +\tu32 *regs;\n> +\tint i, j;\n\nCan be unsigned int.\n\n> +\n> +\tfor (i = 0; i < pmx->nbanks; i++) {\n> +\t\tregs = pmx->regs[i];\n> +\t\tfor (j = 0; j < pmx->reg_bank_size[i] / 4; j++)\n> +\t\t\t*backup_regs++ = readl(regs++);\n> +\t}\n> +\n> +\treturn pinctrl_force_sleep(pmx->pctl);\n> +}\n> +\n> +int __maybe_unused tegra_pinctrl_resume(struct device *dev)\n> +{\n> +\tstruct tegra_pmx *pmx = dev_get_drvdata(dev);\n> +\tu32 *backup_regs = pmx->backup_regs;\n> +\tu32 *regs;\n> +\tint i, j;\n\nunsigned\n\n> +\n> +\tfor (i = 0; i < pmx->nbanks; i++) {\n> +\t\tregs = pmx->regs[i];\n> +\t\tfor (j = 0; j < pmx->reg_bank_size[i] / 4; j++)\n> +\t\t\twritel(*backup_regs++, regs++);\n> +\t}\n> +\n> +\treturn 0;\n> }\n> \n> static bool gpio_node_has_range(const char *compatible)\n> @@ -645,6 +692,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,\n> \tint i;\n> \tconst char **group_pins;\n> \tint fn, gn, gfn;\n> +\tunsigned long backup_regs_size = 0;\n> \n> \tpmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);\n> \tif (!pmx)\n> @@ -697,6 +745,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,\n> \t\tres = platform_get_resource(pdev, IORESOURCE_MEM, i);\n> \t\tif (!res)\n> \t\t\tbreak;\n> +\t\tbackup_regs_size += resource_size(res);\n> \t}\n> \tpmx->nbanks = i;\n> \n> @@ -705,11 +754,24 @@ int tegra_pinctrl_probe(struct platform_device *pdev,\n> \tif (!pmx->regs)\n> \t\treturn -ENOMEM;\n> \n> +\tpmx->reg_bank_size = devm_kcalloc(&pdev->dev, pmx->nbanks,\n> +\t\t\t\t\t sizeof(*pmx->reg_bank_size),\n> +\t\t\t\t\t GFP_KERNEL);\n> +\tif (!pmx->reg_bank_size)\n> +\t\treturn -ENOMEM;\n> +\n> +\tpmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,\n> +\t\t\t\t\tGFP_KERNEL);\n> +\tif (!pmx->backup_regs)\n> +\t\treturn -ENOMEM;\n> +\n> \tfor (i = 0; i < pmx->nbanks; i++) {\n> \t\tres = platform_get_resource(pdev, IORESOURCE_MEM, i);\n> \t\tpmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);\n> \t\tif (IS_ERR(pmx->regs[i]))\n> \t\t\treturn PTR_ERR(pmx->regs[i]);\n> +\n> +\t\tpmx->reg_bank_size[i] = resource_size(res);\n> \t}\n> \n> \tpmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h\n> index 287702660783..d63e472ee0e1 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra.h\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h\n> @@ -17,6 +17,8 @@ struct tegra_pmx {\n> \n> \tint nbanks;\n> \tvoid __iomem **regs;\n> +\tsize_t *reg_bank_size;\n> +\tu32 *backup_regs;\n> };\n> \n> enum tegra_pinconf_param {\n> @@ -191,8 +193,11 @@ struct tegra_pinctrl_soc_data {\n> \tbool hsm_in_mux;\n> \tbool schmitt_in_mux;\n> \tbool drvtype_in_mux;\n> +\tbool has_park_padcfg;\n> };\n> \n> int tegra_pinctrl_probe(struct platform_device *pdev,\n> \t\t\tconst struct tegra_pinctrl_soc_data *soc_data);\n> +int __maybe_unused tegra_pinctrl_suspend(struct device *dev);\n> +int __maybe_unused tegra_pinctrl_resume(struct device *dev);\n> #endif\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra114.c b/drivers/pinctrl/tegra/pinctrl-tegra114.c\n> index 762151f17a88..06ea8164df9d 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra114.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra114.c\n> @@ -1841,6 +1841,7 @@ static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {\n> \t.hsm_in_mux = false,\n> \t.schmitt_in_mux = false,\n> \t.drvtype_in_mux = false,\n> +\t.has_park_padcfg = false,\n> };\n> \n> static int tegra114_pinctrl_probe(struct platform_device *pdev)\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra124.c b/drivers/pinctrl/tegra/pinctrl-tegra124.c\n> index 930c43758c92..abc8fe92d154 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra124.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra124.c\n> @@ -2053,6 +2053,7 @@ static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {\n> \t.hsm_in_mux = false,\n> \t.schmitt_in_mux = false,\n> \t.drvtype_in_mux = false,\n> +\t.has_park_padcfg = false,\n> };\n> \n> static int tegra124_pinctrl_probe(struct platform_device *pdev)\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c\n> index 4b7837e38fb5..993b82cbfba7 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra20.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c\n> @@ -2223,6 +2223,7 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {\n> \t.hsm_in_mux = false,\n> \t.schmitt_in_mux = false,\n> \t.drvtype_in_mux = false,\n> +\t.has_park_padcfg = false,\n> };\n> \n> static const char *cdev1_parents[] = {\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n> index 0b56ad5c9c1c..10e8a2ec8094 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n> @@ -1555,6 +1555,7 @@ static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {\n> \t.hsm_in_mux = true,\n> \t.schmitt_in_mux = true,\n> \t.drvtype_in_mux = true,\n> +\t.has_park_padcfg = true,\n> };\n> \n> static int tegra210_pinctrl_probe(struct platform_device *pdev)\n> @@ -1562,6 +1563,17 @@ static int tegra210_pinctrl_probe(struct platform_device *pdev)\n> \treturn tegra_pinctrl_probe(pdev, &tegra210_pinctrl);\n> }\n> \n> +#ifdef CONFIG_PM_SLEEP\n> +static const struct dev_pm_ops tegra_pinctrl_pm = {\n> +\t.suspend = &tegra_pinctrl_suspend,\n> +\t.resume = &tegra_pinctrl_resume\n> +};\n> +\n> +#define TEGRA_PINCTRL_PM\t(&tegra_pinctrl_pm)\n> +#else\n> +#define TEGRA_PINCTRL_PM\tNULL\n> +#endif\n\nI think we can simplify this by just dropping the #ifdef. We don't allow\n!PM on Tegra anymore and suspend/resume is something that most users\nwill want to enable. There's very little gain in making the dev_pm_ops\nconditional, and keeping them around unconditionally make it simple.\n\n> +\n> static const struct of_device_id tegra210_pinctrl_of_match[] = {\n> \t{ .compatible = \"nvidia,tegra210-pinmux\", },\n> \t{ },\n> @@ -1571,6 +1583,7 @@ static struct platform_driver tegra210_pinctrl_driver = {\n> \t.driver = {\n> \t\t.name = \"tegra210-pinctrl\",\n> \t\t.of_match_table = tegra210_pinctrl_of_match,\n> +\t\t.pm = TEGRA_PINCTRL_PM,\n\nPlease use a single space around '='. No need for arbitrary padding.\n\nThierry Reding","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=gmail.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"k8PV0fEC\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45Sm9w2Hglz9s3C\n\tfor ;\n\tTue, 18 Jun 2019 21:31:15 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729647AbfFRLbP (ORCPT );\n\tTue, 18 Jun 2019 07:31:15 -0400","from mail-wm1-f67.google.com ([209.85.128.67]:38916 \"EHLO\n\tmail-wm1-f67.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1729110AbfFRLbP (ORCPT\n\t); Tue, 18 Jun 2019 07:31:15 -0400","by mail-wm1-f67.google.com with SMTP id z23so2843594wma.4;\n\tTue, 18 Jun 2019 04:31:12 -0700 (PDT)","from localhost (p2E5BEF36.dip0.t-ipconnect.de. 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\n\tTue, 18 Jun 2019 04:31:11 -0700 (PDT)","Date":"Tue, 18 Jun 2019 13:31:09 +0200","From":"Thierry Reding ","To":"Sowjanya Komatineni ","Cc":"jonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net,\n\tmarc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch,\n\tmark.rutland@arm.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com,\n\tsboyd@kernel.org, linux-clk@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com,\n\ttalho@nvidia.com, linux-tegra@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, mperttunen@nvidia.com,\n\tspatra@nvidia.com, robh+dt@kernel.org, digetx@gmail.com,\n\tdevicetree@vger.kernel.org","Subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","Message-ID":"<20190618113109.GE28892@ulmo>","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"AsxXAMtlQ5JHofzM\"","Content-Disposition":"inline","In-Reply-To":"<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>","User-Agent":"Mutt/1.11.4 (2019-03-13)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2196875,"web_url":"http://patchwork.ozlabs.org/comment/2196875/","msgid":"","list_archive_url":null,"date":"2019-06-18T15:41:03","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":12517,"url":"http://patchwork.ozlabs.org/api/people/12517/","name":"Stephen Warren","email":"swarren@wwwdotorg.org"},"content":"On 6/18/19 3:30 AM, Dmitry Osipenko wrote:\n> 18.06.2019 12:22, Dmitry Osipenko пишет:\n>> 18.06.2019 10:46, Sowjanya Komatineni пишет:\n>>> This patch adds suspend and resume support for Tegra pinctrl driver\n>>> and registers them to syscore so the pinmux settings are restored\n>>> before the devices resume.\n>>>\n>>> Signed-off-by: Sowjanya Komatineni \n>>> ---\n>>> drivers/pinctrl/tegra/pinctrl-tegra.c | 62 ++++++++++++++++++++++++++++++++\n>>> drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +++\n>>> drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 +\n>>> drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 +\n>>> drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 +\n>>> drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n>>> drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 +\n>>> 7 files changed, 84 insertions(+)\n>>>\n>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>> index 34596b246578..ceced30d8bd1 100644\n>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>> @@ -20,11 +20,16 @@\n>>> #include \n>>> #include \n>>> #include \n>>> +#include \n>>> \n>>> #include \"../core.h\"\n>>> #include \"../pinctrl-utils.h\"\n>>> #include \"pinctrl-tegra.h\"\n>>> \n>>> +#define EMMC2_PAD_CFGPADCTRL_0\t\t\t0x1c8\n>>> +#define EMMC4_PAD_CFGPADCTRL_0\t\t\t0x1e0\n>>> +#define EMMC_DPD_PARKING\t\t\t(0x1fff << 14)\n>>> +\n>>> static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n>>> {\n>>> \treturn readl(pmx->regs[bank] + reg);\n>>> @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n>>> \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n>>> \t\t}\n>>> \t}\n>>> +\n>>> +\tif (pmx->soc->has_park_padcfg) {\n>>> +\t\tval = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>> +\t\tval &= ~EMMC_DPD_PARKING;\n>>> +\t\tpmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>> +\n>>> +\t\tval = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>> +\t\tval &= ~EMMC_DPD_PARKING;\n>>> +\t\tpmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>> +\t}\n>>> +}\n>>\n>> Is there any reason why parked_bit can't be changed to parked_bitmask like I was\n>> asking in a comment to v2?\n>>\n>> I suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for\n>> consistency when possible, hence adding platform specifics here should be discouraged.\n>> And then the parked_bitmask will also result in a proper hardware description in the code.\n>>\n> \n> I'm now also vaguely recalling that Stephen Warren had some kind of a \"code generator\"\n> for the pinctrl drivers. So I guess all those tables were auto-generated initially.\n> \n> Stephen, maybe you could adjust the generator to take into account the bitmask (of\n> course if that's a part of the generated code) and then re-gen it all for Sowjanya?\n\nhttps://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that \ngenerate tegra-pinctrlNNN.c. See \tsoc-to-kernel-pinctrl-driver.py. \nIIRC, tegra-pinctrl.c (the core file) isn't auto-generated. Sowjanya is \nwelcome to send a patch to that repo if the code needs to be updated.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=wwwdotorg.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45Sstj1Zfmz9sCJ\n\tfor ;\n\tWed, 19 Jun 2019 01:48:29 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729472AbfFRPsX (ORCPT );\n\tTue, 18 Jun 2019 11:48:23 -0400","from avon.wwwdotorg.org ([104.237.132.123]:60274 \"EHLO\n\tavon.wwwdotorg.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1729209AbfFRPsX (ORCPT\n\t); Tue, 18 Jun 2019 11:48:23 -0400","from [10.20.204.51] (unknown [216.228.112.24])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby avon.wwwdotorg.org (Postfix) with ESMTPSA id 95AB01C015A;\n\tTue, 18 Jun 2019 09:41:05 -0600 (MDT)"],"X-Greylist":"delayed 435 seconds by postgrey-1.27 at vger.kernel.org;\n\tTue, 18 Jun 2019 11:48:22 EDT","X-Virus-Status":"Clean","X-Virus-Scanned":"clamav-milter 0.100.3 at avon.wwwdotorg.org","Subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","To":"Dmitry Osipenko ,\n\tSowjanya Komatineni ","Cc":"thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de,\n\tjason@lakedaemon.net, marc.zyngier@arm.com,\n\tlinus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com,\n\tpdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org,\n\tlinux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,\n\tjckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tmperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>\n\t<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>\n\t","From":"Stephen Warren ","Message-ID":"","Date":"Tue, 18 Jun 2019 09:41:03 -0600","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2196955,"web_url":"http://patchwork.ozlabs.org/comment/2196955/","msgid":"","list_archive_url":null,"date":"2019-06-18T16:50:43","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":75554,"url":"http://patchwork.ozlabs.org/api/people/75554/","name":"Sowjanya Komatineni","email":"skomatineni@nvidia.com"},"content":"On 6/18/19 8:41 AM, Stephen Warren wrote:\n> On 6/18/19 3:30 AM, Dmitry Osipenko wrote:\n>> 18.06.2019 12:22, Dmitry Osipenko пишет:\n>>> 18.06.2019 10:46, Sowjanya Komatineni пишет:\n>>>> This patch adds suspend and resume support for Tegra pinctrl driver\n>>>> and registers them to syscore so the pinmux settings are restored\n>>>> before the devices resume.\n>>>>\n>>>> Signed-off-by: Sowjanya Komatineni \n>>>> ---\n>>>>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 62 \n>>>> ++++++++++++++++++++++++++++++++\n>>>>   drivers/pinctrl/tegra/pinctrl-tegra.h    |  5 +++\n>>>>   drivers/pinctrl/tegra/pinctrl-tegra114.c |  1 +\n>>>>   drivers/pinctrl/tegra/pinctrl-tegra124.c |  1 +\n>>>>   drivers/pinctrl/tegra/pinctrl-tegra20.c  |  1 +\n>>>>   drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n>>>>   drivers/pinctrl/tegra/pinctrl-tegra30.c  |  1 +\n>>>>   7 files changed, 84 insertions(+)\n>>>>\n>>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c \n>>>> b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>> index 34596b246578..ceced30d8bd1 100644\n>>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>> @@ -20,11 +20,16 @@\n>>>>   #include \n>>>>   #include \n>>>>   #include \n>>>> +#include \n>>>>     #include \"../core.h\"\n>>>>   #include \"../pinctrl-utils.h\"\n>>>>   #include \"pinctrl-tegra.h\"\n>>>>   +#define EMMC2_PAD_CFGPADCTRL_0            0x1c8\n>>>> +#define EMMC4_PAD_CFGPADCTRL_0            0x1e0\n>>>> +#define EMMC_DPD_PARKING            (0x1fff << 14)\n>>>> +\n>>>>   static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 \n>>>> reg)\n>>>>   {\n>>>>       return readl(pmx->regs[bank] + reg);\n>>>> @@ -619,6 +624,48 @@ static void \n>>>> tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n>>>>               pmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n>>>>           }\n>>>>       }\n>>>> +\n>>>> +    if (pmx->soc->has_park_padcfg) {\n>>>> +        val = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>> +        pmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>> +\n>>>> +        val = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>> +        pmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>> +    }\n>>>> +}\n>>>\n>>> Is there any reason why parked_bit can't be changed to \n>>> parked_bitmask like I was\n>>> asking in a comment to v2?\n>>>\n>>> I suppose that it's more preferable to keep pinctrl-tegra.c \n>>> platform-agnostic for\n>>> consistency when possible, hence adding platform specifics here \n>>> should be discouraged.\n>>> And then the parked_bitmask will also result in a proper hardware \n>>> description in the code.\n>>>\n>>\n>> I'm now also vaguely recalling that Stephen Warren had some kind of a \n>> \"code generator\"\n>> for the pinctrl drivers. So I guess all those tables were \n>> auto-generated initially.\n>>\n>> Stephen, maybe you could adjust the generator to take into account \n>> the bitmask (of\n>> course if that's a part of the generated code) and then re-gen it all \n>> for Sowjanya?\n>\n> https://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that \n> generate tegra-pinctrlNNN.c. See soc-to-kernel-pinctrl-driver.py. \n> IIRC, tegra-pinctrl.c (the core file) isn't auto-generated. Sowjanya \n> is welcome to send a patch to that repo if the code needs to be updated.\n\n\nHi Dmitry,\n\nJust want to be clear on my understanding of your request.\n\n\"change parked_bit to parked_bitmask\" are you requested to change \nparked_bit of PINGROUP and DRV_PINGROUP to use bitmask value rather than \nbit position inorder to have parked bit configuration for EMMC PADs as \nwell to happen by masking rather than checking for existence of parked_bit?\n\nTrying to understand the reason/benefit for changing parked_bit to \nparked_bitmask.\n\n\nthanks\n\nSowjanya","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"oLXgwoYJ\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SvGh4Pphz9sN6\n\tfor ;\n\tWed, 19 Jun 2019 02:50:52 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1730087AbfFRQus (ORCPT );\n\tTue, 18 Jun 2019 12:50:48 -0400","from hqemgate15.nvidia.com ([216.228.121.64]:7884 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1729327AbfFRQus (ORCPT\n\t); Tue, 18 Jun 2019 12:50:48 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid ; Tue, 18 Jun 2019 09:50:46 -0700","from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 09:50:45 -0700","from [10.2.168.217] (10.124.1.5) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 16:50:42 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 09:50:45 -0700","Subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","To":"Stephen Warren ,\n\tDmitry Osipenko ","CC":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, , ,\n\t","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>\n\t<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>\n\t\n\t","From":"Sowjanya Komatineni ","Message-ID":"","Date":"Tue, 18 Jun 2019 09:50:43 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.0","MIME-Version":"1.0","In-Reply-To":"","X-Originating-IP":"[10.124.1.5]","X-ClientProxiedBy":"HQMAIL104.nvidia.com (172.18.146.11) To\n\tHQMAIL107.nvidia.com (172.20.187.13)","Content-Type":"text/plain; charset=\"utf-8\"; format=flowed","Content-Transfer-Encoding":"quoted-printable","Content-Language":"en-US","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560876646; bh=5ewJKPP9x+yjrdVa+IF7R1TIqyJxyuRq4n8ATlmTSi8=;\n\th=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date:\n\tUser-Agent:MIME-Version:In-Reply-To:X-Originating-IP:\n\tX-ClientProxiedBy:Content-Type:Content-Transfer-Encoding:\n\tContent-Language;\n\tb=oLXgwoYJsuaKPA+P5LeW5/e81zxqAoyQVYEKM/myVLbwzYNRQukxcYGG6Ydohv2hz\n\taPpBNb8iAHRVg9Rc+rrtwi8qasw1FXgrJDCDAIlsgPE3nYjahbaKH9IUElaDuUdmok\n\tvfXv9Fz0FM6nhVuJ20fOoZquNmCMm2qirXnm3Mx+ThR9L4VpsLJn0Fl7sVl2/eN1t4\n\t+GDfH5FMAaOWxHgD/Tb3l5T0XzmHOlEFOvDZCNO3FXBLVBAXzTi4bdlSJlrEkNjQmu\n\tEELGsx3xxevMd3oUXHgO/rvxuyY6KHFFQZy0QVeTTNtWouPa5jIEG0+RwB1/hng/C+\n\tSoQw6VJNLK5Zw==","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2197005,"web_url":"http://patchwork.ozlabs.org/comment/2197005/","msgid":"","list_archive_url":null,"date":"2019-06-18T17:34:59","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":75554,"url":"http://patchwork.ozlabs.org/api/people/75554/","name":"Sowjanya Komatineni","email":"skomatineni@nvidia.com"},"content":"On 6/18/19 9:50 AM, Sowjanya Komatineni wrote:\n>\n> On 6/18/19 8:41 AM, Stephen Warren wrote:\n>> On 6/18/19 3:30 AM, Dmitry Osipenko wrote:\n>>> 18.06.2019 12:22, Dmitry Osipenko пишет:\n>>>> 18.06.2019 10:46, Sowjanya Komatineni пишет:\n>>>>> This patch adds suspend and resume support for Tegra pinctrl driver\n>>>>> and registers them to syscore so the pinmux settings are restored\n>>>>> before the devices resume.\n>>>>>\n>>>>> Signed-off-by: Sowjanya Komatineni \n>>>>> ---\n>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 62 \n>>>>> ++++++++++++++++++++++++++++++++\n>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.h    |  5 +++\n>>>>>   drivers/pinctrl/tegra/pinctrl-tegra114.c |  1 +\n>>>>>   drivers/pinctrl/tegra/pinctrl-tegra124.c |  1 +\n>>>>>   drivers/pinctrl/tegra/pinctrl-tegra20.c  |  1 +\n>>>>>   drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n>>>>>   drivers/pinctrl/tegra/pinctrl-tegra30.c  |  1 +\n>>>>>   7 files changed, 84 insertions(+)\n>>>>>\n>>>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c \n>>>>> b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>> index 34596b246578..ceced30d8bd1 100644\n>>>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>> @@ -20,11 +20,16 @@\n>>>>>   #include \n>>>>>   #include \n>>>>>   #include \n>>>>> +#include \n>>>>>     #include \"../core.h\"\n>>>>>   #include \"../pinctrl-utils.h\"\n>>>>>   #include \"pinctrl-tegra.h\"\n>>>>>   +#define EMMC2_PAD_CFGPADCTRL_0            0x1c8\n>>>>> +#define EMMC4_PAD_CFGPADCTRL_0            0x1e0\n>>>>> +#define EMMC_DPD_PARKING            (0x1fff << 14)\n>>>>> +\n>>>>>   static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 \n>>>>> reg)\n>>>>>   {\n>>>>>       return readl(pmx->regs[bank] + reg);\n>>>>> @@ -619,6 +624,48 @@ static void \n>>>>> tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n>>>>>               pmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n>>>>>           }\n>>>>>       }\n>>>>> +\n>>>>> +    if (pmx->soc->has_park_padcfg) {\n>>>>> +        val = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>>> +        pmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>>> +\n>>>>> +        val = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>>> +        pmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>>> +    }\n>>>>> +}\n>>>>\n>>>> Is there any reason why parked_bit can't be changed to \n>>>> parked_bitmask like I was\n>>>> asking in a comment to v2?\n>>>>\n>>>> I suppose that it's more preferable to keep pinctrl-tegra.c \n>>>> platform-agnostic for\n>>>> consistency when possible, hence adding platform specifics here \n>>>> should be discouraged.\n>>>> And then the parked_bitmask will also result in a proper hardware \n>>>> description in the code.\n>>>>\n>>>\n>>> I'm now also vaguely recalling that Stephen Warren had some kind of \n>>> a \"code generator\"\n>>> for the pinctrl drivers. So I guess all those tables were \n>>> auto-generated initially.\n>>>\n>>> Stephen, maybe you could adjust the generator to take into account \n>>> the bitmask (of\n>>> course if that's a part of the generated code) and then re-gen it \n>>> all for Sowjanya?\n>>\n>> https://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that \n>> generate tegra-pinctrlNNN.c. See soc-to-kernel-pinctrl-driver.py. \n>> IIRC, tegra-pinctrl.c (the core file) isn't auto-generated. Sowjanya \n>> is welcome to send a patch to that repo if the code needs to be updated.\n>\n>\n> Hi Dmitry,\n>\n> Just want to be clear on my understanding of your request.\n>\n> \"change parked_bit to parked_bitmask\" are you requested to change \n> parked_bit of PINGROUP and DRV_PINGROUP to use bitmask value rather \n> than bit position inorder to have parked bit configuration for EMMC \n> PADs as well to happen by masking rather than checking for existence \n> of parked_bit?\n>\n> Trying to understand the reason/benefit for changing parked_bit to \n> parked_bitmask.\nAlso, Park bits in CFGPAD registers are not common for all CFGPAD \nregisters. Park bits are available only for EMMC and also those bits are \nused for something else on other CFGPAD registers so bitmask can't be \ncommon and this also need an update to DRV_PINGROUP macro args just only \nto handle EMMC parked_bitmask. So not sure of the benefit in using \nbitmask rather than parked_bit\n>\n> thanks\n>\n> Sowjanya\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"kwGAzBsQ\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SwFm2k8bz9sNT\n\tfor ;\n\tWed, 19 Jun 2019 03:35:08 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729774AbfFRRfE (ORCPT );\n\tTue, 18 Jun 2019 13:35:04 -0400","from hqemgate15.nvidia.com ([216.228.121.64]:10677 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1729586AbfFRRfD (ORCPT\n\t); Tue, 18 Jun 2019 13:35:03 -0400","from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid ; Tue, 18 Jun 2019 10:35:02 -0700","from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 10:35:01 -0700","from [10.2.168.217] (10.124.1.5) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 17:34:58 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 10:35:01 -0700","Subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","From":"Sowjanya Komatineni ","To":"Stephen Warren ,\n\tDmitry Osipenko ","CC":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, , ,\n\t","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>\n\t<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>\n\t\n\t\n\t","Message-ID":"","Date":"Tue, 18 Jun 2019 10:34:59 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.0","MIME-Version":"1.0","In-Reply-To":"","X-Originating-IP":"[10.124.1.5]","X-ClientProxiedBy":"HQMAIL105.nvidia.com (172.20.187.12) To\n\tHQMAIL107.nvidia.com (172.20.187.13)","Content-Type":"text/plain; charset=\"utf-8\"; format=flowed","Content-Transfer-Encoding":"quoted-printable","Content-Language":"en-US","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560879302; bh=EtLjwWpiDtqSfPhNA/8G8Clz5OAG+A5COmGeaCrkKVg=;\n\th=X-PGP-Universal:Subject:From:To:CC:References:Message-ID:Date:\n\tUser-Agent:MIME-Version:In-Reply-To:X-Originating-IP:\n\tX-ClientProxiedBy:Content-Type:Content-Transfer-Encoding:\n\tContent-Language;\n\tb=kwGAzBsQ1yoTWwKlo2/UOXv2gkDJ8firGCWiN14gqHzMxIIzL+NJZ9lpPELHx7++8\n\tC93tekf3G0sFEXan2CyLBApX5uH4osQ5xuNl+ata+wnHZmNVrOtlPPhO6hhKsV/Juf\n\tbZZ27nnu7W7H0ZnSISHtqcoPE+/xNqqhYTqKlosqswoYZXizfVaeos2MrmAZ08rpAS\n\tyLrxRqjT/pGG5gMZ13xiR+i9Huo6g16m5gpObtCMD/6v8RkLqVDaMmayD+7Pe8lziR\n\tFxzKA/nr4019w/Sj8inE7uex06rlPkDCg+nyeUgJDyr2rcvucvqnbVPNXZILdkVwtR\n\txtp0jurZ5tT0Q==","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2197132,"web_url":"http://patchwork.ozlabs.org/comment/2197132/","msgid":"<232324b1-c0eb-ba1b-0fd0-31fcbd701e07@gmail.com>","list_archive_url":null,"date":"2019-06-18T20:00:05","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"18.06.2019 20:34, Sowjanya Komatineni пишет:\n> \n> On 6/18/19 9:50 AM, Sowjanya Komatineni wrote:\n>>\n>> On 6/18/19 8:41 AM, Stephen Warren wrote:\n>>> On 6/18/19 3:30 AM, Dmitry Osipenko wrote:\n>>>> 18.06.2019 12:22, Dmitry Osipenko пишет:\n>>>>> 18.06.2019 10:46, Sowjanya Komatineni пишет:\n>>>>>> This patch adds suspend and resume support for Tegra pinctrl driver\n>>>>>> and registers them to syscore so the pinmux settings are restored\n>>>>>> before the devices resume.\n>>>>>>\n>>>>>> Signed-off-by: Sowjanya Komatineni \n>>>>>> ---\n>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 62 ++++++++++++++++++++++++++++++++\n>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.h    |  5 +++\n>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra114.c |  1 +\n>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra124.c |  1 +\n>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra20.c  |  1 +\n>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra30.c  |  1 +\n>>>>>>   7 files changed, 84 insertions(+)\n>>>>>>\n>>>>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>> b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>> index 34596b246578..ceced30d8bd1 100644\n>>>>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>> @@ -20,11 +20,16 @@\n>>>>>>   #include \n>>>>>>   #include \n>>>>>>   #include \n>>>>>> +#include \n>>>>>>     #include \"../core.h\"\n>>>>>>   #include \"../pinctrl-utils.h\"\n>>>>>>   #include \"pinctrl-tegra.h\"\n>>>>>>   +#define EMMC2_PAD_CFGPADCTRL_0            0x1c8\n>>>>>> +#define EMMC4_PAD_CFGPADCTRL_0            0x1e0\n>>>>>> +#define EMMC_DPD_PARKING            (0x1fff << 14)\n>>>>>> +\n>>>>>>   static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n>>>>>>   {\n>>>>>>       return readl(pmx->regs[bank] + reg);\n>>>>>> @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n>>>>>>               pmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n>>>>>>           }\n>>>>>>       }\n>>>>>> +\n>>>>>> +    if (pmx->soc->has_park_padcfg) {\n>>>>>> +        val = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>>>> +        pmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>>>> +\n>>>>>> +        val = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>>>> +        pmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>>>> +    }\n>>>>>> +}\n>>>>>\n>>>>> Is there any reason why parked_bit can't be changed to parked_bitmask like I was\n>>>>> asking in a comment to v2?\n>>>>>\n>>>>> I suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for\n>>>>> consistency when possible, hence adding platform specifics here should be discouraged.\n>>>>> And then the parked_bitmask will also result in a proper hardware description in the code.\n>>>>>\n>>>>\n>>>> I'm now also vaguely recalling that Stephen Warren had some kind of a \"code generator\"\n>>>> for the pinctrl drivers. So I guess all those tables were auto-generated initially.\n>>>>\n>>>> Stephen, maybe you could adjust the generator to take into account the bitmask (of\n>>>> course if that's a part of the generated code) and then re-gen it all for Sowjanya?\n>>>\n>>> https://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that generate\n>>> tegra-pinctrlNNN.c. See soc-to-kernel-pinctrl-driver.py. IIRC, tegra-pinctrl.c (the core\n>>> file) isn't auto-generated. Sowjanya is welcome to send a patch to that repo if the code\n>>> needs to be updated.\n>>\n>>\n>> Hi Dmitry,\n>>\n>> Just want to be clear on my understanding of your request.\n>>\n>> \"change parked_bit to parked_bitmask\" are you requested to change parked_bit of PINGROUP\n>> and DRV_PINGROUP to use bitmask value rather than bit position inorder to have parked bit\n>> configuration for EMMC PADs as well to happen by masking rather than checking for\n>> existence of parked_bit?\n>>\n>> Trying to understand the reason/benefit for changing parked_bit to parked_bitmask.\n> Also, Park bits in CFGPAD registers are not common for all CFGPAD registers. Park bits are\n> available only for EMMC and also those bits are used for something else on other CFGPAD\n> registers so bitmask can't be common and this also need an update to DRV_PINGROUP macro args\n> just only to handle EMMC parked_bitmask. So not sure of the benefit in using bitmask rather\n\nHi Sowjanya,\n\nThe main motivation is to describe hardware properly in the drivers. Why to make a\nhacky-looking workaround while you can make things properly? Especially if that doesn't take\nmuch effort.\n\nStephen, thank you very much for the pointer to the script. Looks like it should be easy to\nmodify the script accordingly to the required change.\n\nSowjanya, below is a draft of the change that I'm suggesting. I see this as two separate\npatches: first converts drivers to use parked_bitmask, second adds suspend-resume support.\n\nPlease note that in the end it's up to you and Tegra/PINCTRL maintainers to decide if this\nis a worthwhile change that I'm suggesting. In my opinion it is much better to have a\ngeneric solution rather than to have a special quirk solely for T210.\n\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\nindex 34596b246578..4150da74bd44 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n@@ -613,9 +613,9 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n\n \tfor (i = 0; i < pmx->soc->ngroups; ++i) {\n \t\tg = &pmx->soc->groups[i];\n-\t\tif (g->parked_bit >= 0) {\n+\t\tif (g->parked_bitmask != -1) {\n \t\t\tval = pmx_readl(pmx, g->mux_bank, g->mux_reg);\n-\t\t\tval &= ~(1 << g->parked_bit);\n+\t\t\tval &= ~g->parked_bitmask;\n \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n \t\t}\n \t}\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h\nindex 287702660783..875eb7a1d838 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra.h\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h\n@@ -96,7 +96,7 @@ struct tegra_function {\n * @tri_reg:\t\tTri-state register offset.\n * @tri_bank:\t\tTri-state register bank.\n * @tri_bit:\t\tTri-state register bit.\n- * @parked_bit:\t\tParked register bit. -1 if unsupported.\n+ * @parked_bitmask:\tParked register bitmask. -1 if unsupported.\n * @einput_bit:\t\tEnable-input register bit.\n * @odrain_bit:\t\tOpen-drain register bit.\n * @lock_bit:\t\tLock register bit.\n@@ -146,7 +146,7 @@ struct tegra_pingroup {\n \ts32 mux_bit:6;\n \ts32 pupd_bit:6;\n \ts32 tri_bit:6;\n-\ts32 parked_bit:6;\n+\ts32 parked_bitmask:26;\n \ts32 einput_bit:6;\n \ts32 odrain_bit:6;\n \ts32 lock_bit:6;\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c\nindex 0b56ad5c9c1c..d2ba13466e06 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra210.c\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n@@ -1302,7 +1302,7 @@ static struct tegra_function tegra210_functions[] = {\n \t\t.lock_bit = 7,\t\t\t\t\t\t\\\n \t\t.ioreset_bit = -1,\t\t\t\t\t\\\n \t\t.rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10),\t\t\\\n-\t\t.parked_bit = 5,\t\t\t\t\t\\\n+\t\t.parked_bitmask = BIT(5),\t\t\t\t\\\n \t\t.hsm_bit = PINGROUP_BIT_##hsm(9),\t\t\t\\\n \t\t.schmitt_bit = 12,\t\t\t\t\t\\\n \t\t.drvtype_bit = PINGROUP_BIT_##drvtype(13),\t\t\\\n@@ -1320,7 +1320,7 @@ static struct tegra_function tegra210_functions[] = {\n \t}\n\n #define DRV_PINGROUP(pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w,\t\\\n-\t\t slwr_b, slwr_w, slwf_b, slwf_w)\t\t\t\\\n+\t\t slwr_b, slwr_w, slwf_b, slwf_w, prk_mask)\t\t\\\n \t{\t\t\t\t\t\t\t\t\\\n \t\t.name = \"drive_\" #pg_name,\t\t\t\t\\\n \t\t.pins = drive_##pg_name##_pins,\t\t\t\t\\\n@@ -1335,7 +1335,7 @@ static struct tegra_function tegra210_functions[] = {\n \t\t.rcv_sel_bit = -1,\t\t\t\t\t\\\n \t\t.drv_reg = DRV_PINGROUP_REG(r),\t\t\t\t\\\n \t\t.drv_bank = 0,\t\t\t\t\t\t\\\n-\t\t.parked_bit = -1,\t\t\t\t\t\\\n+\t\t.parked_bitmask = prk_mask,\t\t\t\t\\\n \t\t.hsm_bit = -1,\t\t\t\t\t\t\\\n \t\t.schmitt_bit = -1,\t\t\t\t\t\\\n \t\t.lpmd_bit = -1,\t\t\t\t\t\t\\\n@@ -1516,31 +1516,31 @@ static const struct tegra_pingroup tegra210_groups[] = {\n \tPINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N,\n -1, -1, -1, -1, -1, -1, -1, -1, -1),\n\n \t/* pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */\n-\tDRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1),\n-\tDRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1),\n-\tDRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1),\n-\tDRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1),\n-\tDRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1),\n-\tDRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2),\n-\tDRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1),\n-\tDRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1),\n-\tDRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1),\n-\tDRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1),\n-\tDRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1),\n-\tDRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1),\n-\tDRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2),\n-\tDRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2),\n-\tDRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2),\n-\tDRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2),\n+\tDRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n+\tDRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2, 0x7ffc000),\n+\tDRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2, -1),\n+\tDRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2, 0x7ffc000),\n };\n\n static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=gmail.com","ozlabs.org; dkim=pass (2048-bit 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and resume support","To":"Sowjanya Komatineni ,\n\tStephen Warren ","Cc":"thierry.reding@gmail.com, jonathanh@nvidia.com, tglx@linutronix.de,\n\tjason@lakedaemon.net, marc.zyngier@arm.com,\n\tlinus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com,\n\tpdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org,\n\tlinux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,\n\tjckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tmperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>\n\t<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>\n\t\n\t\n\t\n\t","From":"Dmitry Osipenko ","Message-ID":"<232324b1-c0eb-ba1b-0fd0-31fcbd701e07@gmail.com>","Date":"Tue, 18 Jun 2019 23:00:05 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.1","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2197134,"web_url":"http://patchwork.ozlabs.org/comment/2197134/","msgid":"","list_archive_url":null,"date":"2019-06-18T20:04:57","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":75554,"url":"http://patchwork.ozlabs.org/api/people/75554/","name":"Sowjanya Komatineni","email":"skomatineni@nvidia.com"},"content":"On 6/18/19 1:00 PM, Dmitry Osipenko wrote:\n> 18.06.2019 20:34, Sowjanya Komatineni пишет:\n>> On 6/18/19 9:50 AM, Sowjanya Komatineni wrote:\n>>> On 6/18/19 8:41 AM, Stephen Warren wrote:\n>>>> On 6/18/19 3:30 AM, Dmitry Osipenko wrote:\n>>>>> 18.06.2019 12:22, Dmitry Osipenko пишет:\n>>>>>> 18.06.2019 10:46, Sowjanya Komatineni пишет:\n>>>>>>> This patch adds suspend and resume support for Tegra pinctrl driver\n>>>>>>> and registers them to syscore so the pinmux settings are restored\n>>>>>>> before the devices resume.\n>>>>>>>\n>>>>>>> Signed-off-by: Sowjanya Komatineni \n>>>>>>> ---\n>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 62 ++++++++++++++++++++++++++++++++\n>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.h    |  5 +++\n>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra114.c |  1 +\n>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra124.c |  1 +\n>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra20.c  |  1 +\n>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra30.c  |  1 +\n>>>>>>>   7 files changed, 84 insertions(+)\n>>>>>>>\n>>>>>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>>> b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>>> index 34596b246578..ceced30d8bd1 100644\n>>>>>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>>> @@ -20,11 +20,16 @@\n>>>>>>>   #include \n>>>>>>>   #include \n>>>>>>>   #include \n>>>>>>> +#include \n>>>>>>>     #include \"../core.h\"\n>>>>>>>   #include \"../pinctrl-utils.h\"\n>>>>>>>   #include \"pinctrl-tegra.h\"\n>>>>>>>   +#define EMMC2_PAD_CFGPADCTRL_0            0x1c8\n>>>>>>> +#define EMMC4_PAD_CFGPADCTRL_0            0x1e0\n>>>>>>> +#define EMMC_DPD_PARKING            (0x1fff << 14)\n>>>>>>> +\n>>>>>>>   static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n>>>>>>>   {\n>>>>>>>       return readl(pmx->regs[bank] + reg);\n>>>>>>> @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n>>>>>>>               pmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n>>>>>>>           }\n>>>>>>>       }\n>>>>>>> +\n>>>>>>> +    if (pmx->soc->has_park_padcfg) {\n>>>>>>> +        val = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>>>>> +        pmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>>>>> +\n>>>>>>> +        val = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>>>>> +        pmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>>>>> +    }\n>>>>>>> +}\n>>>>>> Is there any reason why parked_bit can't be changed to parked_bitmask like I was\n>>>>>> asking in a comment to v2?\n>>>>>>\n>>>>>> I suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for\n>>>>>> consistency when possible, hence adding platform specifics here should be discouraged.\n>>>>>> And then the parked_bitmask will also result in a proper hardware description in the code.\n>>>>>>\n>>>>> I'm now also vaguely recalling that Stephen Warren had some kind of a \"code generator\"\n>>>>> for the pinctrl drivers. So I guess all those tables were auto-generated initially.\n>>>>>\n>>>>> Stephen, maybe you could adjust the generator to take into account the bitmask (of\n>>>>> course if that's a part of the generated code) and then re-gen it all for Sowjanya?\n>>>> https://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that generate\n>>>> tegra-pinctrlNNN.c. See soc-to-kernel-pinctrl-driver.py. IIRC, tegra-pinctrl.c (the core\n>>>> file) isn't auto-generated. Sowjanya is welcome to send a patch to that repo if the code\n>>>> needs to be updated.\n>>>\n>>> Hi Dmitry,\n>>>\n>>> Just want to be clear on my understanding of your request.\n>>>\n>>> \"change parked_bit to parked_bitmask\" are you requested to change parked_bit of PINGROUP\n>>> and DRV_PINGROUP to use bitmask value rather than bit position inorder to have parked bit\n>>> configuration for EMMC PADs as well to happen by masking rather than checking for\n>>> existence of parked_bit?\n>>>\n>>> Trying to understand the reason/benefit for changing parked_bit to parked_bitmask.\n>> Also, Park bits in CFGPAD registers are not common for all CFGPAD registers. Park bits are\n>> available only for EMMC and also those bits are used for something else on other CFGPAD\n>> registers so bitmask can't be common and this also need an update to DRV_PINGROUP macro args\n>> just only to handle EMMC parked_bitmask. So not sure of the benefit in using bitmask rather\n> Hi Sowjanya,\n>\n> The main motivation is to describe hardware properly in the drivers. Why to make a\n> hacky-looking workaround while you can make things properly? Especially if that doesn't take\n> much effort.\n>\n> Stephen, thank you very much for the pointer to the script. Looks like it should be easy to\n> modify the script accordingly to the required change.\n>\n> Sowjanya, below is a draft of the change that I'm suggesting. I see this as two separate\n> patches: first converts drivers to use parked_bitmask, second adds suspend-resume support.\n>\n> Please note that in the end it's up to you and Tegra/PINCTRL maintainers to decide if this\n> is a worthwhile change that I'm suggesting. In my opinion it is much better to have a\n> generic solution rather than to have a special quirk solely for T210.\n\nOK I can change it. Just thought to find out the reason as I see other \npinmux field also using as bits rather than bitmask.\n\nGot it now. Will update in next version.\n\n>\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> index 34596b246578..4150da74bd44 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> @@ -613,9 +613,9 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n>\n> \tfor (i = 0; i < pmx->soc->ngroups; ++i) {\n> \t\tg = &pmx->soc->groups[i];\n> -\t\tif (g->parked_bit >= 0) {\n> +\t\tif (g->parked_bitmask != -1) {\n> \t\t\tval = pmx_readl(pmx, g->mux_bank, g->mux_reg);\n> -\t\t\tval &= ~(1 << g->parked_bit);\n> +\t\t\tval &= ~g->parked_bitmask;\n> \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n> \t\t}\n> \t}\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h\n> index 287702660783..875eb7a1d838 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra.h\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h\n> @@ -96,7 +96,7 @@ struct tegra_function {\n> * @tri_reg:\t\tTri-state register offset.\n> * @tri_bank:\t\tTri-state register bank.\n> * @tri_bit:\t\tTri-state register bit.\n> - * @parked_bit:\t\tParked register bit. -1 if unsupported.\n> + * @parked_bitmask:\tParked register bitmask. -1 if unsupported.\n> * @einput_bit:\t\tEnable-input register bit.\n> * @odrain_bit:\t\tOpen-drain register bit.\n> * @lock_bit:\t\tLock register bit.\n> @@ -146,7 +146,7 @@ struct tegra_pingroup {\n> \ts32 mux_bit:6;\n> \ts32 pupd_bit:6;\n> \ts32 tri_bit:6;\n> -\ts32 parked_bit:6;\n> +\ts32 parked_bitmask:26;\n> \ts32 einput_bit:6;\n> \ts32 odrain_bit:6;\n> \ts32 lock_bit:6;\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n> index 0b56ad5c9c1c..d2ba13466e06 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n> @@ -1302,7 +1302,7 @@ static struct tegra_function tegra210_functions[] = {\n> \t\t.lock_bit = 7,\t\t\t\t\t\t\\\n> \t\t.ioreset_bit = -1,\t\t\t\t\t\\\n> \t\t.rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10),\t\t\\\n> -\t\t.parked_bit = 5,\t\t\t\t\t\\\n> +\t\t.parked_bitmask = BIT(5),\t\t\t\t\\\n> \t\t.hsm_bit = PINGROUP_BIT_##hsm(9),\t\t\t\\\n> \t\t.schmitt_bit = 12,\t\t\t\t\t\\\n> \t\t.drvtype_bit = PINGROUP_BIT_##drvtype(13),\t\t\\\n> @@ -1320,7 +1320,7 @@ static struct tegra_function tegra210_functions[] = {\n> \t}\n>\n> #define DRV_PINGROUP(pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w,\t\\\n> -\t\t slwr_b, slwr_w, slwf_b, slwf_w)\t\t\t\\\n> +\t\t slwr_b, slwr_w, slwf_b, slwf_w, prk_mask)\t\t\\\n> \t{\t\t\t\t\t\t\t\t\\\n> \t\t.name = \"drive_\" #pg_name,\t\t\t\t\\\n> \t\t.pins = drive_##pg_name##_pins,\t\t\t\t\\\n> @@ -1335,7 +1335,7 @@ static struct tegra_function tegra210_functions[] = {\n> \t\t.rcv_sel_bit = -1,\t\t\t\t\t\\\n> \t\t.drv_reg = DRV_PINGROUP_REG(r),\t\t\t\t\\\n> \t\t.drv_bank = 0,\t\t\t\t\t\t\\\n> -\t\t.parked_bit = -1,\t\t\t\t\t\\\n> +\t\t.parked_bitmask = prk_mask,\t\t\t\t\\\n> \t\t.hsm_bit = -1,\t\t\t\t\t\t\\\n> \t\t.schmitt_bit = -1,\t\t\t\t\t\\\n> \t\t.lpmd_bit = -1,\t\t\t\t\t\t\\\n> @@ -1516,31 +1516,31 @@ static const struct tegra_pingroup tegra210_groups[] = {\n> \tPINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N,\n> -1, -1, -1, -1, -1, -1, -1, -1, -1),\n>\n> \t/* pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */\n> -\tDRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2),\n> +\tDRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2, 0x7ffc000),\n> +\tDRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2, 0x7ffc000),\n> };\n>\n> static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 13:04:59 -0700","from [10.2.168.217] (10.124.1.5) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 20:04:56 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 13:04:59 -0700","Subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","To":"Dmitry Osipenko ,\n\tStephen Warren ","CC":", ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, ,\n\t, , ,\n\t","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>\n\t<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>\n\t\n\t\n\t\n\t\n\t<232324b1-c0eb-ba1b-0fd0-31fcbd701e07@gmail.com>","From":"Sowjanya Komatineni ","Message-ID":"","Date":"Tue, 18 Jun 2019 13:04:57 -0700","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.0","MIME-Version":"1.0","In-Reply-To":"<232324b1-c0eb-ba1b-0fd0-31fcbd701e07@gmail.com>","X-Originating-IP":"[10.124.1.5]","X-ClientProxiedBy":"HQMAIL104.nvidia.com (172.18.146.11) To\n\tHQMAIL107.nvidia.com (172.20.187.13)","Content-Type":"text/plain; charset=\"utf-8\"; format=flowed","Content-Transfer-Encoding":"quoted-printable","Content-Language":"en-US","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560888300; 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support","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Tue, Jun 18, 2019 at 11:00:05PM +0300, Dmitry Osipenko wrote:\n> 18.06.2019 20:34, Sowjanya Komatineni пишет:\n> > \n> > On 6/18/19 9:50 AM, Sowjanya Komatineni wrote:\n> >>\n> >> On 6/18/19 8:41 AM, Stephen Warren wrote:\n> >>> On 6/18/19 3:30 AM, Dmitry Osipenko wrote:\n> >>>> 18.06.2019 12:22, Dmitry Osipenko пишет:\n> >>>>> 18.06.2019 10:46, Sowjanya Komatineni пишет:\n> >>>>>> This patch adds suspend and resume support for Tegra pinctrl driver\n> >>>>>> and registers them to syscore so the pinmux settings are restored\n> >>>>>> before the devices resume.\n> >>>>>>\n> >>>>>> Signed-off-by: Sowjanya Komatineni \n> >>>>>> ---\n> >>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 62 ++++++++++++++++++++++++++++++++\n> >>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.h    |  5 +++\n> >>>>>>   drivers/pinctrl/tegra/pinctrl-tegra114.c |  1 +\n> >>>>>>   drivers/pinctrl/tegra/pinctrl-tegra124.c |  1 +\n> >>>>>>   drivers/pinctrl/tegra/pinctrl-tegra20.c  |  1 +\n> >>>>>>   drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n> >>>>>>   drivers/pinctrl/tegra/pinctrl-tegra30.c  |  1 +\n> >>>>>>   7 files changed, 84 insertions(+)\n> >>>>>>\n> >>>>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c\n> >>>>>> b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> >>>>>> index 34596b246578..ceced30d8bd1 100644\n> >>>>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n> >>>>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> >>>>>> @@ -20,11 +20,16 @@\n> >>>>>>   #include \n> >>>>>>   #include \n> >>>>>>   #include \n> >>>>>> +#include \n> >>>>>>     #include \"../core.h\"\n> >>>>>>   #include \"../pinctrl-utils.h\"\n> >>>>>>   #include \"pinctrl-tegra.h\"\n> >>>>>>   +#define EMMC2_PAD_CFGPADCTRL_0            0x1c8\n> >>>>>> +#define EMMC4_PAD_CFGPADCTRL_0            0x1e0\n> >>>>>> +#define EMMC_DPD_PARKING            (0x1fff << 14)\n> >>>>>> +\n> >>>>>>   static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n> >>>>>>   {\n> >>>>>>       return readl(pmx->regs[bank] + reg);\n> >>>>>> @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n> >>>>>>               pmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n> >>>>>>           }\n> >>>>>>       }\n> >>>>>> +\n> >>>>>> +    if (pmx->soc->has_park_padcfg) {\n> >>>>>> +        val = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n> >>>>>> +        val &= ~EMMC_DPD_PARKING;\n> >>>>>> +        pmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n> >>>>>> +\n> >>>>>> +        val = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n> >>>>>> +        val &= ~EMMC_DPD_PARKING;\n> >>>>>> +        pmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n> >>>>>> +    }\n> >>>>>> +}\n> >>>>>\n> >>>>> Is there any reason why parked_bit can't be changed to parked_bitmask like I was\n> >>>>> asking in a comment to v2?\n> >>>>>\n> >>>>> I suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for\n> >>>>> consistency when possible, hence adding platform specifics here should be discouraged.\n> >>>>> And then the parked_bitmask will also result in a proper hardware description in the code.\n> >>>>>\n> >>>>\n> >>>> I'm now also vaguely recalling that Stephen Warren had some kind of a \"code generator\"\n> >>>> for the pinctrl drivers. So I guess all those tables were auto-generated initially.\n> >>>>\n> >>>> Stephen, maybe you could adjust the generator to take into account the bitmask (of\n> >>>> course if that's a part of the generated code) and then re-gen it all for Sowjanya?\n> >>>\n> >>> https://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that generate\n> >>> tegra-pinctrlNNN.c. See soc-to-kernel-pinctrl-driver.py. IIRC, tegra-pinctrl.c (the core\n> >>> file) isn't auto-generated. Sowjanya is welcome to send a patch to that repo if the code\n> >>> needs to be updated.\n> >>\n> >>\n> >> Hi Dmitry,\n> >>\n> >> Just want to be clear on my understanding of your request.\n> >>\n> >> \"change parked_bit to parked_bitmask\" are you requested to change parked_bit of PINGROUP\n> >> and DRV_PINGROUP to use bitmask value rather than bit position inorder to have parked bit\n> >> configuration for EMMC PADs as well to happen by masking rather than checking for\n> >> existence of parked_bit?\n> >>\n> >> Trying to understand the reason/benefit for changing parked_bit to parked_bitmask.\n> > Also, Park bits in CFGPAD registers are not common for all CFGPAD registers. Park bits are\n> > available only for EMMC and also those bits are used for something else on other CFGPAD\n> > registers so bitmask can't be common and this also need an update to DRV_PINGROUP macro args\n> > just only to handle EMMC parked_bitmask. So not sure of the benefit in using bitmask rather\n> \n> Hi Sowjanya,\n> \n> The main motivation is to describe hardware properly in the drivers. Why to make a\n> hacky-looking workaround while you can make things properly? Especially if that doesn't take\n> much effort.\n> \n> Stephen, thank you very much for the pointer to the script. Looks like it should be easy to\n> modify the script accordingly to the required change.\n> \n> Sowjanya, below is a draft of the change that I'm suggesting. I see this as two separate\n> patches: first converts drivers to use parked_bitmask, second adds suspend-resume support.\n> \n> Please note that in the end it's up to you and Tegra/PINCTRL maintainers to decide if this\n> is a worthwhile change that I'm suggesting. In my opinion it is much better to have a\n> generic solution rather than to have a special quirk solely for T210.\n> \n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> index 34596b246578..4150da74bd44 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> @@ -613,9 +613,9 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n> \n> \tfor (i = 0; i < pmx->soc->ngroups; ++i) {\n> \t\tg = &pmx->soc->groups[i];\n> -\t\tif (g->parked_bit >= 0) {\n> +\t\tif (g->parked_bitmask != -1) {\n> \t\t\tval = pmx_readl(pmx, g->mux_bank, g->mux_reg);\n> -\t\t\tval &= ~(1 << g->parked_bit);\n> +\t\t\tval &= ~g->parked_bitmask;\n> \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n> \t\t}\n> \t}\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h\n> index 287702660783..875eb7a1d838 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra.h\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h\n> @@ -96,7 +96,7 @@ struct tegra_function {\n> * @tri_reg:\t\tTri-state register offset.\n> * @tri_bank:\t\tTri-state register bank.\n> * @tri_bit:\t\tTri-state register bit.\n> - * @parked_bit:\t\tParked register bit. -1 if unsupported.\n> + * @parked_bitmask:\tParked register bitmask. -1 if unsupported.\n\nIf we're already moving to a bitmask, wouldn't it be easier to just make\n0 the case where it is unsupported?\n\n> * @einput_bit:\t\tEnable-input register bit.\n> * @odrain_bit:\t\tOpen-drain register bit.\n> * @lock_bit:\t\tLock register bit.\n> @@ -146,7 +146,7 @@ struct tegra_pingroup {\n> \ts32 mux_bit:6;\n> \ts32 pupd_bit:6;\n> \ts32 tri_bit:6;\n> -\ts32 parked_bit:6;\n> +\ts32 parked_bitmask:26;\n\nIf we make parked_bitmask == 0 the case for \"unsupported\" we could make\nthis u32 while at it.\n\n> \ts32 einput_bit:6;\n> \ts32 odrain_bit:6;\n> \ts32 lock_bit:6;\n> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n> index 0b56ad5c9c1c..d2ba13466e06 100644\n> --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c\n> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n> @@ -1302,7 +1302,7 @@ static struct tegra_function tegra210_functions[] = {\n> \t\t.lock_bit = 7,\t\t\t\t\t\t\\\n> \t\t.ioreset_bit = -1,\t\t\t\t\t\\\n> \t\t.rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10),\t\t\\\n> -\t\t.parked_bit = 5,\t\t\t\t\t\\\n> +\t\t.parked_bitmask = BIT(5),\t\t\t\t\\\n> \t\t.hsm_bit = PINGROUP_BIT_##hsm(9),\t\t\t\\\n> \t\t.schmitt_bit = 12,\t\t\t\t\t\\\n> \t\t.drvtype_bit = PINGROUP_BIT_##drvtype(13),\t\t\\\n> @@ -1320,7 +1320,7 @@ static struct tegra_function tegra210_functions[] = {\n> \t}\n> \n> #define DRV_PINGROUP(pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w,\t\\\n> -\t\t slwr_b, slwr_w, slwf_b, slwf_w)\t\t\t\\\n> +\t\t slwr_b, slwr_w, slwf_b, slwf_w, prk_mask)\t\t\\\n> \t{\t\t\t\t\t\t\t\t\\\n> \t\t.name = \"drive_\" #pg_name,\t\t\t\t\\\n> \t\t.pins = drive_##pg_name##_pins,\t\t\t\t\\\n> @@ -1335,7 +1335,7 @@ static struct tegra_function tegra210_functions[] = {\n> \t\t.rcv_sel_bit = -1,\t\t\t\t\t\\\n> \t\t.drv_reg = DRV_PINGROUP_REG(r),\t\t\t\t\\\n> \t\t.drv_bank = 0,\t\t\t\t\t\t\\\n> -\t\t.parked_bit = -1,\t\t\t\t\t\\\n> +\t\t.parked_bitmask = prk_mask,\t\t\t\t\\\n> \t\t.hsm_bit = -1,\t\t\t\t\t\t\\\n> \t\t.schmitt_bit = -1,\t\t\t\t\t\\\n> \t\t.lpmd_bit = -1,\t\t\t\t\t\t\\\n> @@ -1516,31 +1516,31 @@ static const struct tegra_pingroup tegra210_groups[] = {\n> \tPINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N,\n> -1, -1, -1, -1, -1, -1, -1, -1, -1),\n> \n> \t/* pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */\n> -\tDRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1),\n> -\tDRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2),\n> -\tDRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2),\n> +\tDRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n> +\tDRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2, 0x7ffc000),\n> +\tDRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2, -1),\n> +\tDRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2, 0x7ffc000),\n\nMight be worth adding a new DRV_PINGROUP_PARK (or whatever) macro that\ntakes the additional parameter. that way we could avoid the extra churn.\n\nThierry\n\n> };\n> \n> static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=gmail.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"SH/GsEHV\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45TJ884lfgz9sNC\n\tfor ;\n\tWed, 19 Jun 2019 18:31:36 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1731164AbfFSIbf (ORCPT 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micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"eWbcAUUbgrfSEG1c\"","Content-Disposition":"inline","In-Reply-To":"<232324b1-c0eb-ba1b-0fd0-31fcbd701e07@gmail.com>","User-Agent":"Mutt/1.11.4 (2019-03-13)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2197488,"web_url":"http://patchwork.ozlabs.org/comment/2197488/","msgid":"<20190619083308.GM3187@ulmo>","list_archive_url":null,"date":"2019-06-19T08:33:08","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Tue, Jun 18, 2019 at 09:41:03AM -0600, Stephen Warren wrote:\n> On 6/18/19 3:30 AM, Dmitry Osipenko wrote:\n> > 18.06.2019 12:22, Dmitry Osipenko пишет:\n> > > 18.06.2019 10:46, Sowjanya Komatineni пишет:\n> > > > This patch adds suspend and resume support for Tegra pinctrl driver\n> > > > and registers them to syscore so the pinmux settings are restored\n> > > > before the devices resume.\n> > > > \n> > > > Signed-off-by: Sowjanya Komatineni \n> > > > ---\n> > > > drivers/pinctrl/tegra/pinctrl-tegra.c | 62 ++++++++++++++++++++++++++++++++\n> > > > drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +++\n> > > > drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 +\n> > > > drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 +\n> > > > drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 +\n> > > > drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n> > > > drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 +\n> > > > 7 files changed, 84 insertions(+)\n> > > > \n> > > > diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> > > > index 34596b246578..ceced30d8bd1 100644\n> > > > --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n> > > > +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> > > > @@ -20,11 +20,16 @@\n> > > > #include \n> > > > #include \n> > > > #include \n> > > > +#include \n> > > > #include \"../core.h\"\n> > > > #include \"../pinctrl-utils.h\"\n> > > > #include \"pinctrl-tegra.h\"\n> > > > +#define EMMC2_PAD_CFGPADCTRL_0\t\t\t0x1c8\n> > > > +#define EMMC4_PAD_CFGPADCTRL_0\t\t\t0x1e0\n> > > > +#define EMMC_DPD_PARKING\t\t\t(0x1fff << 14)\n> > > > +\n> > > > static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n> > > > {\n> > > > \treturn readl(pmx->regs[bank] + reg);\n> > > > @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n> > > > \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n> > > > \t\t}\n> > > > \t}\n> > > > +\n> > > > +\tif (pmx->soc->has_park_padcfg) {\n> > > > +\t\tval = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n> > > > +\t\tval &= ~EMMC_DPD_PARKING;\n> > > > +\t\tpmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n> > > > +\n> > > > +\t\tval = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n> > > > +\t\tval &= ~EMMC_DPD_PARKING;\n> > > > +\t\tpmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n> > > > +\t}\n> > > > +}\n> > > \n> > > Is there any reason why parked_bit can't be changed to parked_bitmask like I was\n> > > asking in a comment to v2?\n> > > \n> > > I suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for\n> > > consistency when possible, hence adding platform specifics here should be discouraged.\n> > > And then the parked_bitmask will also result in a proper hardware description in the code.\n> > > \n> > \n> > I'm now also vaguely recalling that Stephen Warren had some kind of a \"code generator\"\n> > for the pinctrl drivers. So I guess all those tables were auto-generated initially.\n> > \n> > Stephen, maybe you could adjust the generator to take into account the bitmask (of\n> > course if that's a part of the generated code) and then re-gen it all for Sowjanya?\n> \n> https://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that\n> generate tegra-pinctrlNNN.c. See \tsoc-to-kernel-pinctrl-driver.py. IIRC,\n> tegra-pinctrl.c (the core file) isn't auto-generated. Sowjanya is welcome to\n> send a patch to that repo if the code needs to be updated.\n\nIf we want to do that, we may need to start off by bringing the pinmux\nscripts up to date with the latest version of the generated files. There\nhave been a number of changes in the meantime that cause the scripts to\ngenerate a bit of diff with regards to what's currently upstream. Sounds\nlike something fairly trivial, though.\n\nThierry","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=gmail.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"CMzGEE1l\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45TJB25Qm6z9s5c\n\tfor ;\n\tWed, 19 Jun 2019 18:33:14 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1731213AbfFSIdO (ORCPT );\n\tWed, 19 Jun 2019 04:33:14 -0400","from mail-wr1-f68.google.com ([209.85.221.68]:46257 \"EHLO\n\tmail-wr1-f68.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1731063AbfFSIdN (ORCPT\n\t); Wed, 19 Jun 2019 04:33:13 -0400","by mail-wr1-f68.google.com with SMTP id n4so2308093wrw.13;\n\tWed, 19 Jun 2019 01:33:11 -0700 (PDT)","from localhost (p2E5BEF36.dip0.t-ipconnect.de. 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\n\tWed, 19 Jun 2019 01:33:10 -0700 (PDT)","Date":"Wed, 19 Jun 2019 10:33:08 +0200","From":"Thierry Reding ","To":"Stephen Warren ","Cc":"Dmitry Osipenko ,\n\tSowjanya Komatineni ,\n\tjonathanh@nvidia.com, tglx@linutronix.de, jason@lakedaemon.net,\n\tmarc.zyngier@arm.com, linus.walleij@linaro.org, stefan@agner.ch,\n\tmark.rutland@arm.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com,\n\tsboyd@kernel.org, linux-clk@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org, jckuo@nvidia.com, josephl@nvidia.com,\n\ttalho@nvidia.com, linux-tegra@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, mperttunen@nvidia.com,\n\tspatra@nvidia.com, robh+dt@kernel.org, devicetree@vger.kernel.org","Subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","Message-ID":"<20190619083308.GM3187@ulmo>","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>\n\t<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>\n\t\n\t","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"Nj4mAaUCx+wbOcQD\"","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.11.4 (2019-03-13)","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2197496,"web_url":"http://patchwork.ozlabs.org/comment/2197496/","msgid":"<995011d5-784a-81b0-d413-78c8aaf86056@gmail.com>","list_archive_url":null,"date":"2019-06-19T08:40:37","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"19.06.2019 11:31, Thierry Reding пишет:\n> On Tue, Jun 18, 2019 at 11:00:05PM +0300, Dmitry Osipenko wrote:\n>> 18.06.2019 20:34, Sowjanya Komatineni пишет:\n>>>\n>>> On 6/18/19 9:50 AM, Sowjanya Komatineni wrote:\n>>>>\n>>>> On 6/18/19 8:41 AM, Stephen Warren wrote:\n>>>>> On 6/18/19 3:30 AM, Dmitry Osipenko wrote:\n>>>>>> 18.06.2019 12:22, Dmitry Osipenko пишет:\n>>>>>>> 18.06.2019 10:46, Sowjanya Komatineni пишет:\n>>>>>>>> This patch adds suspend and resume support for Tegra pinctrl driver\n>>>>>>>> and registers them to syscore so the pinmux settings are restored\n>>>>>>>> before the devices resume.\n>>>>>>>>\n>>>>>>>> Signed-off-by: Sowjanya Komatineni \n>>>>>>>> ---\n>>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.c    | 62 ++++++++++++++++++++++++++++++++\n>>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra.h    |  5 +++\n>>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra114.c |  1 +\n>>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra124.c |  1 +\n>>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra20.c  |  1 +\n>>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n>>>>>>>>   drivers/pinctrl/tegra/pinctrl-tegra30.c  |  1 +\n>>>>>>>>   7 files changed, 84 insertions(+)\n>>>>>>>>\n>>>>>>>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>>>> b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>>>> index 34596b246578..ceced30d8bd1 100644\n>>>>>>>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>>>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>>>>>>>> @@ -20,11 +20,16 @@\n>>>>>>>>   #include \n>>>>>>>>   #include \n>>>>>>>>   #include \n>>>>>>>> +#include \n>>>>>>>>     #include \"../core.h\"\n>>>>>>>>   #include \"../pinctrl-utils.h\"\n>>>>>>>>   #include \"pinctrl-tegra.h\"\n>>>>>>>>   +#define EMMC2_PAD_CFGPADCTRL_0            0x1c8\n>>>>>>>> +#define EMMC4_PAD_CFGPADCTRL_0            0x1e0\n>>>>>>>> +#define EMMC_DPD_PARKING            (0x1fff << 14)\n>>>>>>>> +\n>>>>>>>>   static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n>>>>>>>>   {\n>>>>>>>>       return readl(pmx->regs[bank] + reg);\n>>>>>>>> @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n>>>>>>>>               pmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n>>>>>>>>           }\n>>>>>>>>       }\n>>>>>>>> +\n>>>>>>>> +    if (pmx->soc->has_park_padcfg) {\n>>>>>>>> +        val = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>>>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>>>>>> +        pmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n>>>>>>>> +\n>>>>>>>> +        val = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>>>>>> +        val &= ~EMMC_DPD_PARKING;\n>>>>>>>> +        pmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n>>>>>>>> +    }\n>>>>>>>> +}\n>>>>>>>\n>>>>>>> Is there any reason why parked_bit can't be changed to parked_bitmask like I was\n>>>>>>> asking in a comment to v2?\n>>>>>>>\n>>>>>>> I suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for\n>>>>>>> consistency when possible, hence adding platform specifics here should be discouraged.\n>>>>>>> And then the parked_bitmask will also result in a proper hardware description in the code.\n>>>>>>>\n>>>>>>\n>>>>>> I'm now also vaguely recalling that Stephen Warren had some kind of a \"code generator\"\n>>>>>> for the pinctrl drivers. So I guess all those tables were auto-generated initially.\n>>>>>>\n>>>>>> Stephen, maybe you could adjust the generator to take into account the bitmask (of\n>>>>>> course if that's a part of the generated code) and then re-gen it all for Sowjanya?\n>>>>>\n>>>>> https://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that generate\n>>>>> tegra-pinctrlNNN.c. See soc-to-kernel-pinctrl-driver.py. IIRC, tegra-pinctrl.c (the core\n>>>>> file) isn't auto-generated. Sowjanya is welcome to send a patch to that repo if the code\n>>>>> needs to be updated.\n>>>>\n>>>>\n>>>> Hi Dmitry,\n>>>>\n>>>> Just want to be clear on my understanding of your request.\n>>>>\n>>>> \"change parked_bit to parked_bitmask\" are you requested to change parked_bit of PINGROUP\n>>>> and DRV_PINGROUP to use bitmask value rather than bit position inorder to have parked bit\n>>>> configuration for EMMC PADs as well to happen by masking rather than checking for\n>>>> existence of parked_bit?\n>>>>\n>>>> Trying to understand the reason/benefit for changing parked_bit to parked_bitmask.\n>>> Also, Park bits in CFGPAD registers are not common for all CFGPAD registers. Park bits are\n>>> available only for EMMC and also those bits are used for something else on other CFGPAD\n>>> registers so bitmask can't be common and this also need an update to DRV_PINGROUP macro args\n>>> just only to handle EMMC parked_bitmask. So not sure of the benefit in using bitmask rather\n>>\n>> Hi Sowjanya,\n>>\n>> The main motivation is to describe hardware properly in the drivers. Why to make a\n>> hacky-looking workaround while you can make things properly? Especially if that doesn't take\n>> much effort.\n>>\n>> Stephen, thank you very much for the pointer to the script. Looks like it should be easy to\n>> modify the script accordingly to the required change.\n>>\n>> Sowjanya, below is a draft of the change that I'm suggesting. I see this as two separate\n>> patches: first converts drivers to use parked_bitmask, second adds suspend-resume support.\n>>\n>> Please note that in the end it's up to you and Tegra/PINCTRL maintainers to decide if this\n>> is a worthwhile change that I'm suggesting. In my opinion it is much better to have a\n>> generic solution rather than to have a special quirk solely for T210.\n>>\n>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>> index 34596b246578..4150da74bd44 100644\n>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n>> @@ -613,9 +613,9 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n>>\n>> \tfor (i = 0; i < pmx->soc->ngroups; ++i) {\n>> \t\tg = &pmx->soc->groups[i];\n>> -\t\tif (g->parked_bit >= 0) {\n>> +\t\tif (g->parked_bitmask != -1) {\n>> \t\t\tval = pmx_readl(pmx, g->mux_bank, g->mux_reg);\n>> -\t\t\tval &= ~(1 << g->parked_bit);\n>> +\t\t\tval &= ~g->parked_bitmask;\n>> \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n>> \t\t}\n>> \t}\n>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h\n>> index 287702660783..875eb7a1d838 100644\n>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.h\n>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.h\n>> @@ -96,7 +96,7 @@ struct tegra_function {\n>> * @tri_reg:\t\tTri-state register offset.\n>> * @tri_bank:\t\tTri-state register bank.\n>> * @tri_bit:\t\tTri-state register bit.\n>> - * @parked_bit:\t\tParked register bit. -1 if unsupported.\n>> + * @parked_bitmask:\tParked register bitmask. -1 if unsupported.\n> \n> If we're already moving to a bitmask, wouldn't it be easier to just make\n> 0 the case where it is unsupported?\n> \n>> * @einput_bit:\t\tEnable-input register bit.\n>> * @odrain_bit:\t\tOpen-drain register bit.\n>> * @lock_bit:\t\tLock register bit.\n>> @@ -146,7 +146,7 @@ struct tegra_pingroup {\n>> \ts32 mux_bit:6;\n>> \ts32 pupd_bit:6;\n>> \ts32 tri_bit:6;\n>> -\ts32 parked_bit:6;\n>> +\ts32 parked_bitmask:26;\n> \n> If we make parked_bitmask == 0 the case for \"unsupported\" we could make\n> this u32 while at it.\n> \n>> \ts32 einput_bit:6;\n>> \ts32 odrain_bit:6;\n>> \ts32 lock_bit:6;\n>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n>> index 0b56ad5c9c1c..d2ba13466e06 100644\n>> --- a/drivers/pinctrl/tegra/pinctrl-tegra210.c\n>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n>> @@ -1302,7 +1302,7 @@ static struct tegra_function tegra210_functions[] = {\n>> \t\t.lock_bit = 7,\t\t\t\t\t\t\\\n>> \t\t.ioreset_bit = -1,\t\t\t\t\t\\\n>> \t\t.rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10),\t\t\\\n>> -\t\t.parked_bit = 5,\t\t\t\t\t\\\n>> +\t\t.parked_bitmask = BIT(5),\t\t\t\t\\\n>> \t\t.hsm_bit = PINGROUP_BIT_##hsm(9),\t\t\t\\\n>> \t\t.schmitt_bit = 12,\t\t\t\t\t\\\n>> \t\t.drvtype_bit = PINGROUP_BIT_##drvtype(13),\t\t\\\n>> @@ -1320,7 +1320,7 @@ static struct tegra_function tegra210_functions[] = {\n>> \t}\n>>\n>> #define DRV_PINGROUP(pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w,\t\\\n>> -\t\t slwr_b, slwr_w, slwf_b, slwf_w)\t\t\t\\\n>> +\t\t slwr_b, slwr_w, slwf_b, slwf_w, prk_mask)\t\t\\\n>> \t{\t\t\t\t\t\t\t\t\\\n>> \t\t.name = \"drive_\" #pg_name,\t\t\t\t\\\n>> \t\t.pins = drive_##pg_name##_pins,\t\t\t\t\\\n>> @@ -1335,7 +1335,7 @@ static struct tegra_function tegra210_functions[] = {\n>> \t\t.rcv_sel_bit = -1,\t\t\t\t\t\\\n>> \t\t.drv_reg = DRV_PINGROUP_REG(r),\t\t\t\t\\\n>> \t\t.drv_bank = 0,\t\t\t\t\t\t\\\n>> -\t\t.parked_bit = -1,\t\t\t\t\t\\\n>> +\t\t.parked_bitmask = prk_mask,\t\t\t\t\\\n>> \t\t.hsm_bit = -1,\t\t\t\t\t\t\\\n>> \t\t.schmitt_bit = -1,\t\t\t\t\t\\\n>> \t\t.lpmd_bit = -1,\t\t\t\t\t\t\\\n>> @@ -1516,31 +1516,31 @@ static const struct tegra_pingroup tegra210_groups[] = {\n>> \tPINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N,\n>> -1, -1, -1, -1, -1, -1, -1, -1, -1),\n>>\n>> \t/* pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */\n>> -\tDRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1),\n>> -\tDRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2),\n>> -\tDRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2),\n>> +\tDRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1, -1),\n>> +\tDRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2, 0x7ffc000),\n>> +\tDRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2, -1),\n>> +\tDRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2, 0x7ffc000),\n> \n> Might be worth adding a new DRV_PINGROUP_PARK (or whatever) macro that\n> takes the additional parameter. that way we could avoid the extra churn.\n\nSounds like a very good call! +1","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=gmail.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"bkHc0kui\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45TJLg5Gt0z9s5c\n\tfor ;\n\tWed, 19 Jun 2019 18:40:43 +1000 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and resume support","To":"Thierry Reding ,\n\tSowjanya Komatineni ","Cc":"Stephen Warren , jonathanh@nvidia.com,\n\ttglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com,\n\tlinus.walleij@linaro.org, stefan@agner.ch, mark.rutland@arm.com,\n\tpdeschrijver@nvidia.com, pgaikwad@nvidia.com, sboyd@kernel.org,\n\tlinux-clk@vger.kernel.org, linux-gpio@vger.kernel.org,\n\tjckuo@nvidia.com, josephl@nvidia.com, talho@nvidia.com,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tmperttunen@nvidia.com, spatra@nvidia.com, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org","References":"<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>\n\t<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>\n\t<7706a287-44b7-3ad6-37ff-47e97172a798@gmail.com>\n\t\n\t\n\t\n\t\n\t<232324b1-c0eb-ba1b-0fd0-31fcbd701e07@gmail.com>\n\t<20190619083127.GL3187@ulmo>","From":"Dmitry Osipenko ","Message-ID":"<995011d5-784a-81b0-d413-78c8aaf86056@gmail.com>","Date":"Wed, 19 Jun 2019 11:40:37 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101\n\tThunderbird/60.7.1","MIME-Version":"1.0","In-Reply-To":"<20190619083127.GL3187@ulmo>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"linux-gpio-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-gpio@vger.kernel.org"}},{"id":2197510,"web_url":"http://patchwork.ozlabs.org/comment/2197510/","msgid":"<20190619085726.GN3187@ulmo>","list_archive_url":null,"date":"2019-06-19T08:57:26","subject":"Re: [PATCH V3 02/17] pinctrl: tegra: add suspend and resume support","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Wed, Jun 19, 2019 at 10:33:08AM +0200, Thierry Reding wrote:\n> On Tue, Jun 18, 2019 at 09:41:03AM -0600, Stephen Warren wrote:\n> > On 6/18/19 3:30 AM, Dmitry Osipenko wrote:\n> > > 18.06.2019 12:22, Dmitry Osipenko пишет:\n> > > > 18.06.2019 10:46, Sowjanya Komatineni пишет:\n> > > > > This patch adds suspend and resume support for Tegra pinctrl driver\n> > > > > and registers them to syscore so the pinmux settings are restored\n> > > > > before the devices resume.\n> > > > > \n> > > > > Signed-off-by: Sowjanya Komatineni \n> > > > > ---\n> > > > > drivers/pinctrl/tegra/pinctrl-tegra.c | 62 ++++++++++++++++++++++++++++++++\n> > > > > drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +++\n> > > > > drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 +\n> > > > > drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 +\n> > > > > drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 +\n> > > > > drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n> > > > > drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 +\n> > > > > 7 files changed, 84 insertions(+)\n> > > > > \n> > > > > diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> > > > > index 34596b246578..ceced30d8bd1 100644\n> > > > > --- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n> > > > > +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n> > > > > @@ -20,11 +20,16 @@\n> > > > > #include \n> > > > > #include \n> > > > > #include \n> > > > > +#include \n> > > > > #include \"../core.h\"\n> > > > > #include \"../pinctrl-utils.h\"\n> > > > > #include \"pinctrl-tegra.h\"\n> > > > > +#define EMMC2_PAD_CFGPADCTRL_0\t\t\t0x1c8\n> > > > > +#define EMMC4_PAD_CFGPADCTRL_0\t\t\t0x1e0\n> > > > > +#define EMMC_DPD_PARKING\t\t\t(0x1fff << 14)\n> > > > > +\n> > > > > static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n> > > > > {\n> > > > > \treturn readl(pmx->regs[bank] + reg);\n> > > > > @@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n> > > > > \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n> > > > > \t\t}\n> > > > > \t}\n> > > > > +\n> > > > > +\tif (pmx->soc->has_park_padcfg) {\n> > > > > +\t\tval = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n> > > > > +\t\tval &= ~EMMC_DPD_PARKING;\n> > > > > +\t\tpmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n> > > > > +\n> > > > > +\t\tval = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n> > > > > +\t\tval &= ~EMMC_DPD_PARKING;\n> > > > > +\t\tpmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n> > > > > +\t}\n> > > > > +}\n> > > > \n> > > > Is there any reason why parked_bit can't be changed to parked_bitmask like I was\n> > > > asking in a comment to v2?\n> > > > \n> > > > I suppose that it's more preferable to keep pinctrl-tegra.c platform-agnostic for\n> > > > consistency when possible, hence adding platform specifics here should be discouraged.\n> > > > And then the parked_bitmask will also result in a proper hardware description in the code.\n> > > > \n> > > \n> > > I'm now also vaguely recalling that Stephen Warren had some kind of a \"code generator\"\n> > > for the pinctrl drivers. So I guess all those tables were auto-generated initially.\n> > > \n> > > Stephen, maybe you could adjust the generator to take into account the bitmask (of\n> > > course if that's a part of the generated code) and then re-gen it all for Sowjanya?\n> > \n> > https://github.com/NVIDIA/tegra-pinmux-scripts holds the scripts that\n> > generate tegra-pinctrlNNN.c. See \tsoc-to-kernel-pinctrl-driver.py. IIRC,\n> > tegra-pinctrl.c (the core file) isn't auto-generated. Sowjanya is welcome to\n> > send a patch to that repo if the code needs to be updated.\n> \n> If we want to do that, we may need to start off by bringing the pinmux\n> scripts up to date with the latest version of the generated files. There\n> have been a number of changes in the meantime that cause the scripts to\n> generate a bit of diff with regards to what's currently upstream. Sounds\n> like something fairly trivial, though.\n\nSomething like the below should do the trick.\n\nThierry\n\n--- >8 ---\nFrom 9a684d2ad3c0e0c7b4dbda5904db1fda3757072b Mon Sep 17 00:00:00 2001\nFrom: Thierry Reding \nDate: Wed, 19 Jun 2019 10:50:57 +0200\nSubject: [pinmux scripts PATCH] Update kernel driver template\n\nSome changes in recent years have modified the upstream kernel driver in\nsome ways that make it incompatible with the current template. Update\nthe template to take into account changes introduced by the following\ncommits:\n\n\tcommit e3d2160f12d6aa7a87d9db09d8458b4a3492cd45\n\tAuthor: Paul Gortmaker \n\tDate: Mon May 22 16:56:47 2017 -0400\n\n\t pinctrl: tegra: clean up modular vs. non-modular distinctions\n\n\t None of the Kconfigs for any of these drivers are tristate,\n\t meaning that they currently are not being built as a module by anyone.\n\n\t Lets remove the modular code that is essentially orphaned, so that\n\t when reading the drivers there is no doubt they are builtin-only. All\n\t drivers get similar changes, so they are handled in batch.\n\n\t We remove module.h from code that isn't doing anything modular at\n\t all; if they have __init sections, then replace it with init.h.\n\n\t A couple drivers have module_exit() code that is essentially orphaned,\n\t and so we remove that.\n\n\t Quite a few bool drivers (hence non-modular) are converted over to\n\t to builtin_platform_driver().\n\n\t Since module_platform_driver() uses the same init level priority as\n\t builtin_platform_driver() the init ordering remains unchanged with\n\t this commit.\n\n\t Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code.\n\n\t We also delete the MODULE_LICENSE tag etc. since all that information\n\t was (or is now) contained at the top of the file in the comments.\n\n\t Cc: Linus Walleij \n\t Cc: Stephen Warren \n\t Cc: Thierry Reding \n\t Cc: Alexandre Courbot \n\t Cc: Pritesh Raithatha \n\t Cc: Ashwini Ghuge \n\t Cc: linux-gpio@vger.kernel.org\n\t Cc: linux-tegra@vger.kernel.org\n\t Signed-off-by: Paul Gortmaker \n\t Signed-off-by: Linus Walleij \n\n\tcommit 3c94d2d08a032d911bbe34f2edb24cb63a63644a\n\tAuthor: Stefan Agner \n\tDate: Thu Jul 26 17:40:24 2018 +0200\n\n\t pinctrl: tegra: define GPIO compatible node per SoC\n\n\t Tegra 2 uses a different GPIO controller which uses \"tegra20-gpio\" as\n\t compatible string.\n\n\t Make the compatible string the GPIO node is using a SoC specific\n\t property. This prevents the kernel from registering the GPIO range\n\t twice in case the GPIO range is specified in the device tree.\n\n\t Fixes: 9462510ce31e (\"pinctrl: tegra: Only set the gpio range if needed\")\n\t Signed-off-by: Stefan Agner \n\t Signed-off-by: Linus Walleij \n\n\tcommit 1e0813ee5599932c856bda64a568895ed7a33d3a\n\tAuthor: Dmitry Osipenko \n\tDate: Thu Aug 2 14:11:43 2018 +0300\n\n\t pinctrl: tegra: Move drivers registration to arch_init level\n\n\t There is a bug in regards to deferred probing within the drivers core\n\t that causes GPIO-driver to suspend after its users. The bug appears if\n\t GPIO-driver probe is getting deferred, which happens after introducing\n\t dependency on PINCTRL-driver for the GPIO-driver by defining \"gpio-ranges\"\n\t property in device-tree. The bug in the drivers core is old (more than 4\n\t years now) and is well known, unfortunately there is no easy fix for it.\n\t The good news is that we can workaround the deferred probe issue by\n\t changing GPIO / PINCTRL drivers registration order and hence by moving\n\t PINCTRL driver registration to the arch_init level and GPIO to the\n\t subsys_init.\n\n\t Signed-off-by: Dmitry Osipenko \n\t Acked-by: Stefan Agner \n\t Signed-off-by: Linus Walleij \n\nNote that the last one is something that we probably should fix\ncorrectly by using device links rather than working around it by playing\ninit level tricks.\n\nSigned-off-by: Thierry Reding \n---\n soc-to-kernel-pinctrl-driver.py | 27 +++++++++++----------------\n 1 file changed, 11 insertions(+), 16 deletions(-)\n\ndiff --git a/soc-to-kernel-pinctrl-driver.py b/soc-to-kernel-pinctrl-driver.py\nindex 65e4c604f1c9..37f34b15db2b 100755\n--- a/soc-to-kernel-pinctrl-driver.py\n+++ b/soc-to-kernel-pinctrl-driver.py\n@@ -41,22 +41,16 @@ if dbg: print(args)\n soc = tegra_pmx_soc_parser.load_soc(args.soc)\n \n print('''\\\n+// SPDX-License-Identifier: GPL-2.0-only\n /*\n * Pinctrl data for the NVIDIA %s pinmux\n *\n- * Copyright (c) %s, NVIDIA CORPORATION. All rights reserved.\n- *\n- * This program is free software; you can redistribute it and/or modify it\n- * under the terms and conditions of the GNU General Public License,\n- * version 2, as published by the Free Software Foundation.\n+ * Author: %s\n *\n- * This program is distributed in the hope it will be useful, but WITHOUT\n- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n- * more details.\n+ * Copyright (c) %s, NVIDIA CORPORATION. All rights reserved.\n */\n \n-#include \n+#include \n #include \n #include \n #include \n@@ -68,7 +62,7 @@ print('''\\\n * Most pins affected by the pinmux can also be GPIOs. Define these first.\n * These must match how the GPIO driver names/numbers its pins.\n */\n-''' % (soc.titlename, soc.kernel_copyright_years), end='')\n+''' % (soc.titlename, soc.kernel_author, soc.kernel_copyright_years), end='')\n \n # Do not add any more exceptions here; new SoCs should be formatted correctly\n if soc.name == 'tegra30':\n@@ -615,6 +609,7 @@ print('''\\\n \n static const struct tegra_pinctrl_soc_data %(soc)s_pinctrl = {\n \t.ngpios = NUM_GPIOS,\n+\t.gpio_compatible = \"nvidia,%(soc)s-gpio\",\n \t.pins = %(soc)s_pins,\n \t.npins = ARRAY_SIZE(%(soc)s_pins),\n \t.functions = %(soc)s_functions,\n@@ -635,7 +630,6 @@ static const struct of_device_id %(soc)s_pinctrl_of_match[] = {\n \t{ .compatible = \"nvidia,%(soc)s-pinmux\", },\n \t{ },\n };\n-MODULE_DEVICE_TABLE(of, %(soc)s_pinctrl_of_match);\n \n static struct platform_driver %(soc)s_pinctrl_driver = {\n \t.driver = {\n@@ -644,9 +638,10 @@ static struct platform_driver %(soc)s_pinctrl_driver = {\n \t},\n \t.probe = %(soc)s_pinctrl_probe,\n };\n-module_platform_driver(%(soc)s_pinctrl_driver);\n \n-MODULE_AUTHOR(\"%(author)s\");\n-MODULE_DESCRIPTION(\"NVIDIA %(usoc)s pinctrl driver\");\n-MODULE_LICENSE(\"GPL v2\");\n+static int __init %(soc)s_pinctrl_init(void)\n+{\n+\treturn platform_driver_register(&%(soc)s_pinctrl_driver);\n+}\n+arch_initcall(%(soc)s_pinctrl_init);\n ''' % socvars, end='')","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=gmail.com","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"ROA09wuW\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45TJk644DHz9s5c\n\tfor ;\n\tWed, 19 Jun 2019 18:57:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1731064AbfFSI5d (ORCPT );\n\tWed, 19 Jun 2019 04:57:33 -0400","from mail-wr1-f68.google.com ([209.85.221.68]:36417 \"EHLO\n\tmail-wr1-f68.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1730783AbfFSI5d (ORCPT\n\t); Wed, 19 Jun 2019 04:57:33 -0400","by mail-wr1-f68.google.com with SMTP id n4so2468095wrs.3;\n\tWed, 19 Jun 2019 01:57:29 -0700 (PDT)","from localhost (p2E5BEF36.dip0.t-ipconnect.de. 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