[{"id":1798132,"web_url":"http://patchwork.ozlabs.org/comment/1798132/","msgid":"<5625af45-a071-4abf-88ed-f167abff1b73@arm.com>","list_archive_url":null,"date":"2017-11-02T17:45:50","subject":"Re: [PATCH V3 04/11] clk: sprd: add gate clock support","submitter":{"id":72256,"url":"http://patchwork.ozlabs.org/api/people/72256/","name":"Julien Thierry","email":"julien.thierry@arm.com"},"content":"Hi,\n\nOn 02/11/17 06:56, Chunyan Zhang wrote:\n> Some clocks on the Spreadtrum's SoCs are just simple gates. Add\n> support for those clocks.\n> \n> Signed-off-by: Chunyan Zhang \n> ---\n> drivers/clk/sprd/Makefile | 1 +\n> drivers/clk/sprd/gate.c | 106 ++++++++++++++++++++++++++++++++++++++++++++++\n> drivers/clk/sprd/gate.h | 54 +++++++++++++++++++++++\n> 3 files changed, 161 insertions(+)\n> create mode 100644 drivers/clk/sprd/gate.c\n> create mode 100644 drivers/clk/sprd/gate.h\n> \n> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n> index 74f4b80..8cd5592 100644\n> --- a/drivers/clk/sprd/Makefile\n> +++ b/drivers/clk/sprd/Makefile\n> @@ -1,3 +1,4 @@\n> obj-$(CONFIG_SPRD_COMMON_CLK)\t+= clk-sprd.o\n> \n> clk-sprd-y\t+= common.o\n> +clk-sprd-y\t+= gate.o\n> diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c\n> new file mode 100644\n> index 0000000..831ef81\n> --- /dev/null\n> +++ b/drivers/clk/sprd/gate.c\n> @@ -0,0 +1,106 @@\n> +/*\n> + * Spreadtrum gate clock driver\n> + *\n> + * Copyright (C) 2017 Spreadtrum, Inc.\n> + * Author: Chunyan Zhang \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#include \n> +#include \n> +\n> +#include \"gate.h\"\n> +\n> +DEFINE_SPINLOCK(sprd_gate_lock);\n> +EXPORT_SYMBOL_GPL(sprd_gate_lock);\n> +\n> +static void sprd_gate_endisable(const struct sprd_gate *sg, u32 en)\n> +{\n> +\tconst struct sprd_clk_common *common = &sg->common;\n> +\tunsigned long flags = 0;\n> +\tunsigned int reg;\n> +\tint set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;\n> +\n> +\tset ^= en;\n> +\n> +\tspin_lock_irqsave(common->lock, flags);\n> +\n> +\tsprd_regmap_read(common->regmap, common->reg, ®);\n> +\n> +\tif (set)\n> +\t\treg |= sg->op_bit;\n> +\telse\n> +\t\treg &= ~sg->op_bit;\n> +\n> +\tsprd_regmap_write(common->regmap, common->reg, reg);\n> +\n> +\tspin_unlock_irqrestore(common->lock, flags);\n> +}\n> +\n> +static void clk_sc_gate_endisable(const struct sprd_gate *sg, u32 en)\n> +{\n> +\tconst struct sprd_clk_common *common = &sg->common;\n> +\tunsigned long flags = 0;\n> +\tint set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;\n> +\tunsigned int offset;\n> +\n> +\tset ^= en;\n> +\n> +\t/*\n> +\t * Each set/clear gate clock has three registers:\n> +\t * common->reg\t\t\t- base register\n> +\t * common->reg + offset\t\t- set register\n> +\t * common->reg + 2 * offset\t- clear register\n> +\t */\n> +\toffset = set ? sg->sc_offset : sg->sc_offset * 2;\n> +\n> +\tspin_lock_irqsave(common->lock, flags);\n> +\tsprd_regmap_write(common->regmap, common->reg + offset, sg->op_bit);\n> +\tspin_unlock_irqrestore(common->lock, flags);\n> +}\n> +\n> +static void sprd_gate_disable(struct clk_hw *hw)\n> +{\n> +\tstruct sprd_gate *sg = hw_to_sprd_gate(hw);\n> +\n> +\tif (sg->sc_offset)\n> +\t\tclk_sc_gate_endisable(sg, 0);\n> +\telse\n> +\t\tsprd_gate_endisable(sg, 0);\n> +}\n> +\n> +static int sprd_gate_enable(struct clk_hw *hw)\n> +{\n> +\tstruct sprd_gate *sg = hw_to_sprd_gate(hw);\n> +\n> +\tif (sg->sc_offset)\n> +\t\tclk_sc_gate_endisable(sg, 1);\n> +\telse\n> +\t\tsprd_gate_endisable(sg, 1);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int sprd_gate_is_enabled(struct clk_hw *hw)\n> +{\n> +\tstruct sprd_gate *sg = hw_to_sprd_gate(hw);\n> +\tstruct sprd_clk_common *common = &sg->common;\n> +\tunsigned int reg;\n> +\n> +\tsprd_regmap_read(common->regmap, common->reg, ®);\n> +\n> +\tif (sg->flags & CLK_GATE_SET_TO_DISABLE)\n> +\t\treg ^= sg->op_bit;\n> +\n> +\treg &= sg->op_bit;\n> +\n> +\treturn reg ? 1 : 0;\n> +}\n> +\n> +const struct clk_ops sprd_gate_ops = {\n> +\t.disable\t= sprd_gate_disable,\n> +\t.enable\t\t= sprd_gate_enable,\n> +\t.is_enabled\t= sprd_gate_is_enabled,\n> +};\n> +EXPORT_SYMBOL_GPL(sprd_gate_ops);\n\nI think it would be better to have a set of ops for each mode,\nsprd_gate_ops and sprd_sc_gate_ops rather than have each function decide \nwhether it should use set/clear registers or the base registers.\n\nSo you can have a macro SPRD_GATE_CLK that doesn't take an sc_offet and \nselects the sprd_gate_ops and another one that SPRD_SC_GATE_CLK using \nsprd_sc_gate_ops that takes the sc_offset as parameter.\n\nAlso, I feel keeping enable/disable function separate would be nicer \ninstead of having \"endisable\" functions.\n\nCheers,\n\n> diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h\n> new file mode 100644\n> index 0000000..5aeb53c\n> --- /dev/null\n> +++ b/drivers/clk/sprd/gate.h\n> @@ -0,0 +1,54 @@\n> +/*\n> + * Spreadtrum gate clock driver\n> + *\n> + * Copyright (C) 2017 Spreadtrum, Inc.\n> + * Author: Chunyan Zhang \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#ifndef _SPRD_GATE_H_\n> +#define _SPRD_GATE_H_\n> +\n> +#include \"common.h\"\n> +\n> +struct sprd_gate {\n> +\tu32\t\t\top_bit;\n> +\tu16\t\t\tflags;\n> +\tu16\t\t\tsc_offset;\n> +\n> +\tstruct sprd_clk_common\tcommon;\n> +};\n> +\n> +#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset,\t\\\n> +\t\t _op_bit, _flags, _gate_flags)\t\t\t\\\n> +\tstruct sprd_gate _struct = {\t\t\t\t\t\\\n> +\t\t.op_bit\t\t= _op_bit,\t\t\t\t\\\n> +\t\t.sc_offset\t= _sc_offset,\t\t\t\t\\\n> +\t\t.flags\t\t= _gate_flags,\t\t\t\t\\\n> +\t\t.common\t= {\t\t\t\t\t\t\\\n> +\t\t\t.regmap\t\t= NULL,\t\t\t\t\\\n> +\t\t\t.reg\t\t= _reg,\t\t\t\t\\\n> +\t\t\t.lock\t\t= &sprd_gate_lock,\t\t\\\n> +\t\t\t.hw.init\t= CLK_HW_INIT(_name,\t\t\\\n> +\t\t\t\t\t\t _parent,\t\t\\\n> +\t\t\t\t\t\t &sprd_gate_ops,\t\\\n> +\t\t\t\t\t\t _flags),\t\t\\\n> +\t\t}\t\t\t\t\t\t\t\\\n> +\t}\n> +\n> +static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)\n> +{\n> +\tstruct sprd_clk_common *common = hw_to_sprd_clk_common(hw);\n> +\n> +\treturn container_of(common, struct sprd_gate, common);\n> +}\n> +\n> +void sprd_gate_helper_disable(struct sprd_clk_common *common, u32 gate);\n> +int sprd_gate_helper_enable(struct sprd_clk_common *common, u32 gate);\n> +int sprd_gate_helper_is_enabled(struct sprd_clk_common *common, u32 gate);\n> +\n> +extern const struct clk_ops sprd_gate_ops;\n> +extern spinlock_t sprd_gate_lock;\n> +\n> +#endif /* _SPRD_GATE_H_ */\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySXZ92Rlzz9sNd\n\tfor ;\n\tFri, 3 Nov 2017 04:46:09 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755938AbdKBRp5 (ORCPT\n\t);\n\tThu, 2 Nov 2017 13:45:57 -0400","from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:34950 \"EHLO\n\tfoss.arm.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1755586AbdKBRpy (ORCPT );\n\tThu, 2 Nov 2017 13:45:54 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 66CE01435;\n\tThu, 2 Nov 2017 10:45:54 -0700 (PDT)","from [10.1.207.56] (e112298-lin.cambridge.arm.com [10.1.207.56])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tA84133F3E1; Thu, 2 Nov 2017 10:45:51 -0700 (PDT)"],"Subject":"Re: [PATCH V3 04/11] clk: sprd: add gate clock support","To":"Chunyan Zhang ,\n\tStephen Boyd ,\n\tMichael Turquette ,\n\tRob Herring , Mark Rutland ","Cc":"Catalin Marinas ,\n\tWill Deacon , linux-clk@vger.kernel.org,\n\tdevicetree@vger.kernel.org, Arnd Bergmann ,\n\tMark Brown ,\n\tXiaolong Zhang ,\n\tBen Li ,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tOrson Zhai ,\n\tChunyan Zhang ","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-5-chunyan.zhang@spreadtrum.com>","From":"Julien Thierry ","Message-ID":"<5625af45-a071-4abf-88ed-f167abff1b73@arm.com>","Date":"Thu, 2 Nov 2017 17:45:50 +0000","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20171102065626.21835-5-chunyan.zhang@spreadtrum.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1798156,"web_url":"http://patchwork.ozlabs.org/comment/1798156/","msgid":"<532aed43-03bf-ea26-bdc2-d7deb1093f53@arm.com>","list_archive_url":null,"date":"2017-11-02T18:11:05","subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","submitter":{"id":72256,"url":"http://patchwork.ozlabs.org/api/people/72256/","name":"Julien Thierry","email":"julien.thierry@arm.com"},"content":"Hi,\n\nOn 02/11/17 06:56, Chunyan Zhang wrote:\n> This patch adds clock multiplexor support for Spreadtrum platforms,\n> the mux clocks also can be found in sprd composite clocks, so\n> provides two helpers that can be reused later on.\n> \n> Signed-off-by: Chunyan Zhang \n> ---\n> drivers/clk/sprd/Makefile | 1 +\n> drivers/clk/sprd/mux.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++\n> drivers/clk/sprd/mux.h | 65 ++++++++++++++++++++++++++++++++++\n> 3 files changed, 155 insertions(+)\n> create mode 100644 drivers/clk/sprd/mux.c\n> create mode 100644 drivers/clk/sprd/mux.h\n> \n> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n> index 8cd5592..cee36b5 100644\n> --- a/drivers/clk/sprd/Makefile\n> +++ b/drivers/clk/sprd/Makefile\n> @@ -2,3 +2,4 @@ obj-$(CONFIG_SPRD_COMMON_CLK)\t+= clk-sprd.o\n> \n> clk-sprd-y\t+= common.o\n> clk-sprd-y\t+= gate.o\n> +clk-sprd-y\t+= mux.o\n> diff --git a/drivers/clk/sprd/mux.c b/drivers/clk/sprd/mux.c\n> new file mode 100644\n> index 0000000..5a344e0\n> --- /dev/null\n> +++ b/drivers/clk/sprd/mux.c\n> @@ -0,0 +1,89 @@\n> +/*\n> + * Spreadtrum multiplexer clock driver\n> + *\n> + * Copyright (C) 2017 Spreadtrum, Inc.\n> + * Author: Chunyan Zhang \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +#include \"mux.h\"\n> +\n> +DEFINE_SPINLOCK(sprd_mux_lock);\n> +EXPORT_SYMBOL_GPL(sprd_mux_lock);\n> +\n> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n> +\t\t\t const struct sprd_mux_internal *mux)\n> +{\n> +\tunsigned int reg;\n> +\tu8 parent;\n> +\tint num_parents;\n> +\tint i;\n> +\n> +\tsprd_regmap_read(common->regmap, common->reg, ®);\n> +\tparent = reg >> mux->shift;\n> +\tparent &= (1 << mux->width) - 1;\n> +\n> +\tif (mux->table) {\n> +\t\tnum_parents = clk_hw_get_num_parents(&common->hw);\n> +\n> +\t\tfor (i = 0; i < num_parents; i++)\n> +\t\t\tif (parent == mux->table[i] ||\n> +\t\t\t (i < (num_parents - 1) && parent > mux->table[i] &&\n> +\t\t\t parent < mux->table[i + 1]))\n> +\t\t\t\treturn i;\n> +\t\tif (i == num_parents)\n> +\t\t\treturn i - 1;\n\nThe if branch is not necessary since you only get there when the loop \nhas finished, so the condition is always true. And the loop can be \nsimplified to:\n\nfor (i = 0; i < num_parents - 1; i++)\n\tif (parent >= mux->table[i] && parent < mux->table[i + 1])\n\t\treturn i;\n\nreturn num_parents;\n\n\n> +\t}\n> +\n> +\treturn parent;\n> +}\n> +EXPORT_SYMBOL_GPL(sprd_mux_helper_get_parent);\n> +\n> +static u8 sprd_mux_get_parent(struct clk_hw *hw)\n> +{\n> +\tstruct sprd_mux *cm = hw_to_sprd_mux(hw);\n> +\n> +\treturn sprd_mux_helper_get_parent(&cm->common, &cm->mux);\n> +}\n> +\n> +int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,\n> +\t\t\t const struct sprd_mux_internal *mux,\n> +\t\t\t u8 index)\n> +{\n> +\tunsigned long flags = 0;\n> +\tunsigned int reg;\n> +\n> +\tif (mux->table)\n> +\t\tindex = mux->table[index];\n> +\n> +\tspin_lock_irqsave(common->lock, flags);\n> +\n> +\tsprd_regmap_read(common->regmap, common->reg, ®);\n> +\treg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift);\n> +\tsprd_regmap_write(common->regmap, common->reg,\n> +\t\t\t reg | (index << mux->shift));\n> +\n> +\tspin_unlock_irqrestore(common->lock, flags);\n> +\n> +\treturn 0;\n> +}\n> +EXPORT_SYMBOL_GPL(sprd_mux_helper_set_parent);\n> +\n> +static int sprd_mux_set_parent(struct clk_hw *hw, u8 index)\n> +{\n> +\tstruct sprd_mux *cm = hw_to_sprd_mux(hw);\n> +\n> +\treturn sprd_mux_helper_set_parent(&cm->common, &cm->mux, index);\n> +}\n> +\n> +const struct clk_ops sprd_mux_ops = {\n> +\t.get_parent = sprd_mux_get_parent,\n> +\t.set_parent = sprd_mux_set_parent,\n> +\t.determine_rate = __clk_mux_determine_rate,\n> +};\n> +EXPORT_SYMBOL_GPL(sprd_mux_ops);\n\nSame as with the other patch, I'd recommend have one set of ops for \ndirect mux and another one for a mux using a table to map the parents. \nKeeping functions for both modes separate.\n\nCheers,\n\n> diff --git a/drivers/clk/sprd/mux.h b/drivers/clk/sprd/mux.h\n> new file mode 100644\n> index 0000000..148ca8c\n> --- /dev/null\n> +++ b/drivers/clk/sprd/mux.h\n> @@ -0,0 +1,65 @@\n> +/*\n> + * Spreadtrum multiplexer clock driver\n> + *\n> + * Copyright (C) 2017 Spreadtrum, Inc.\n> + * Author: Chunyan Zhang \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#ifndef _SPRD_MUX_H_\n> +#define _SPRD_MUX_H_\n> +\n> +#include \"common.h\"\n> +\n> +struct sprd_mux_internal {\n> +\tu8\t\tshift;\n> +\tu8\t\twidth;\n> +\tconst u8\t*table;\n> +};\n> +\n> +struct sprd_mux {\n> +\tstruct sprd_mux_internal mux;\n> +\tstruct sprd_clk_common\tcommon;\n> +};\n> +\n> +#define _SPRD_MUX_CLK(_shift, _width, _table)\t\t\\\n> +\t{\t\t\t\t\t\t\\\n> +\t\t.shift\t= _shift,\t\t\t\\\n> +\t\t.width\t= _width,\t\t\t\\\n> +\t\t.table\t= _table,\t\t\t\\\n> +\t}\n> +\n> +#define SPRD_MUX_CLK(_struct, _name, _parents, _table,\t\t\t\\\n> +\t\t\t\t _reg, _shift, _width,\t\t\\\n> +\t\t\t\t _flags)\t\t\t\t\\\n> +\tstruct sprd_mux _struct = {\t\t\t\t\t\\\n> +\t\t.mux\t= _SPRD_MUX_CLK(_shift, _width, _table),\t\\\n> +\t\t.common\t= {\t\t\t\t\t\t\\\n> +\t\t\t.regmap\t\t= NULL,\t\t\t\t\\\n> +\t\t\t.reg\t\t= _reg,\t\t\t\t\\\n> +\t\t\t.lock\t\t= &sprd_mux_lock,\t\t\\\n> +\t\t\t.hw.init = CLK_HW_INIT_PARENTS(_name,\t\t\\\n> +\t\t\t\t\t\t _parents,\t\\\n> +\t\t\t\t\t\t &sprd_mux_ops,\t\\\n> +\t\t\t\t\t\t _flags),\t\t\\\n> +\t\t}\t\t\t\t\t\t\t\\\n> +\t}\n> +\n> +static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)\n> +{\n> +\tstruct sprd_clk_common *common = hw_to_sprd_clk_common(hw);\n> +\n> +\treturn container_of(common, struct sprd_mux, common);\n> +}\n> +\n> +extern const struct clk_ops sprd_mux_ops;\n> +extern spinlock_t sprd_mux_lock;\n> +\n> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n> +\t\t\t const struct sprd_mux_internal *mux);\n> +int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,\n> +\t\t\t const struct sprd_mux_internal *mux,\n> +\t\t\t u8 index);\n> +\n> +#endif /* _SPRD_MUX_H_ */\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySY744MFnz9sRq\n\tfor ;\n\tFri, 3 Nov 2017 05:11:12 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S933396AbdKBSLK (ORCPT );\n\tThu, 2 Nov 2017 14:11:10 -0400","from foss.arm.com ([217.140.101.70]:35222 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S933025AbdKBSLK (ORCPT );\n\tThu, 2 Nov 2017 14:11:10 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 856541435;\n\tThu, 2 Nov 2017 11:11:09 -0700 (PDT)","from [10.1.207.56] (e112298-lin.cambridge.arm.com [10.1.207.56])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\tAF3813F3E1; Thu, 2 Nov 2017 11:11:06 -0700 (PDT)"],"Subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","To":"Chunyan Zhang ,\n\tStephen Boyd ,\n\tMichael Turquette ,\n\tRob Herring , Mark Rutland ","Cc":"Catalin Marinas ,\n\tWill Deacon , linux-clk@vger.kernel.org,\n\tdevicetree@vger.kernel.org, Arnd Bergmann ,\n\tMark Brown ,\n\tXiaolong Zhang ,\n\tBen Li ,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tOrson Zhai ,\n\tChunyan Zhang ","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-6-chunyan.zhang@spreadtrum.com>","From":"Julien Thierry ","Message-ID":"<532aed43-03bf-ea26-bdc2-d7deb1093f53@arm.com>","Date":"Thu, 2 Nov 2017 18:11:05 +0000","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20171102065626.21835-6-chunyan.zhang@spreadtrum.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1798169,"web_url":"http://patchwork.ozlabs.org/comment/1798169/","msgid":"","list_archive_url":null,"date":"2017-11-02T18:22:22","subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","submitter":{"id":72256,"url":"http://patchwork.ozlabs.org/api/people/72256/","name":"Julien Thierry","email":"julien.thierry@arm.com"},"content":"On 02/11/17 18:11, Julien Thierry wrote:\n> Hi,\n> \n> On 02/11/17 06:56, Chunyan Zhang wrote:\n>> This patch adds clock multiplexor support for Spreadtrum platforms,\n>> the mux clocks also can be found in sprd composite clocks, so\n>> provides two helpers that can be reused later on.\n>>\n>> Signed-off-by: Chunyan Zhang \n>> ---\n>> drivers/clk/sprd/Makefile | 1 +\n>> drivers/clk/sprd/mux.c | 89 \n>> +++++++++++++++++++++++++++++++++++++++++++++++\n>> drivers/clk/sprd/mux.h | 65 ++++++++++++++++++++++++++++++++++\n>> 3 files changed, 155 insertions(+)\n>> create mode 100644 drivers/clk/sprd/mux.c\n>> create mode 100644 drivers/clk/sprd/mux.h\n>>\n>> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n>> index 8cd5592..cee36b5 100644\n>> --- a/drivers/clk/sprd/Makefile\n>> +++ b/drivers/clk/sprd/Makefile\n>> @@ -2,3 +2,4 @@ obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o\n>> clk-sprd-y += common.o\n>> clk-sprd-y += gate.o\n>> +clk-sprd-y += mux.o\n>> diff --git a/drivers/clk/sprd/mux.c b/drivers/clk/sprd/mux.c\n>> new file mode 100644\n>> index 0000000..5a344e0\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/mux.c\n>> @@ -0,0 +1,89 @@\n>> +/*\n>> + * Spreadtrum multiplexer clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +#include \"mux.h\"\n>> +\n>> +DEFINE_SPINLOCK(sprd_mux_lock);\n>> +EXPORT_SYMBOL_GPL(sprd_mux_lock);\n>> +\n>> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux)\n>> +{\n>> + unsigned int reg;\n>> + u8 parent;\n>> + int num_parents;\n>> + int i;\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> + parent = reg >> mux->shift;\n>> + parent &= (1 << mux->width) - 1;\n>> +\n>> + if (mux->table) {\n>> + num_parents = clk_hw_get_num_parents(&common->hw);\n>> +\n>> + for (i = 0; i < num_parents; i++)\n>> + if (parent == mux->table[i] ||\n>> + (i < (num_parents - 1) && parent > mux->table[i] &&\n>> + parent < mux->table[i + 1]))\n>> + return i;\n>> + if (i == num_parents)\n>> + return i - 1;\n> \n> The if branch is not necessary since you only get there when the loop \n> has finished, so the condition is always true. And the loop can be \n> simplified to:\n> \n> for (i = 0; i < num_parents - 1; i++)\n> if (parent >= mux->table[i] && parent < mux->table[i + 1])\n> return i;\n> \n> return num_parents;\n\nOops, meant to say \"return num_parents - 1;\" on that last line.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySYNM4xsLz9sNw\n\tfor ;\n\tFri, 3 Nov 2017 05:22:30 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S933701AbdKBSW2 (ORCPT );\n\tThu, 2 Nov 2017 14:22:28 -0400","from foss.arm.com ([217.140.101.70]:35346 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S933207AbdKBSW1 (ORCPT );\n\tThu, 2 Nov 2017 14:22:27 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 304081435;\n\tThu, 2 Nov 2017 11:22:27 -0700 (PDT)","from [10.1.207.56] (e112298-lin.cambridge.arm.com [10.1.207.56])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t4993F3F3E1; Thu, 2 Nov 2017 11:22:24 -0700 (PDT)"],"Subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","From":"Julien Thierry ","To":"Chunyan Zhang ,\n\tStephen Boyd ,\n\tMichael Turquette ,\n\tRob Herring , Mark Rutland ","Cc":"Catalin Marinas ,\n\tWill Deacon , linux-clk@vger.kernel.org,\n\tdevicetree@vger.kernel.org, Arnd Bergmann ,\n\tMark Brown ,\n\tXiaolong Zhang ,\n\tBen Li ,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tOrson Zhai ,\n\tChunyan Zhang ","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-6-chunyan.zhang@spreadtrum.com>\n\t<532aed43-03bf-ea26-bdc2-d7deb1093f53@arm.com>","Message-ID":"","Date":"Thu, 2 Nov 2017 18:22:22 +0000","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<532aed43-03bf-ea26-bdc2-d7deb1093f53@arm.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1798569,"web_url":"http://patchwork.ozlabs.org/comment/1798569/","msgid":"","list_archive_url":null,"date":"2017-11-03T12:12:51","subject":"Re: [PATCH V3 04/11] clk: sprd: add gate clock support","submitter":{"id":64876,"url":"http://patchwork.ozlabs.org/api/people/64876/","name":"Chunyan Zhang","email":"zhang.lyra@gmail.com"},"content":"Hi Julien,\n\nOn 3 November 2017 at 01:45, Julien Thierry wrote:\n> Hi,\n>\n>\n> On 02/11/17 06:56, Chunyan Zhang wrote:\n>>\n>> Some clocks on the Spreadtrum's SoCs are just simple gates. Add\n>> support for those clocks.\n>>\n>> Signed-off-by: Chunyan Zhang \n>> ---\n>> drivers/clk/sprd/Makefile | 1 +\n>> drivers/clk/sprd/gate.c | 106\n>> ++++++++++++++++++++++++++++++++++++++++++++++\n>> drivers/clk/sprd/gate.h | 54 +++++++++++++++++++++++\n>> 3 files changed, 161 insertions(+)\n>> create mode 100644 drivers/clk/sprd/gate.c\n>> create mode 100644 drivers/clk/sprd/gate.h\n>>\n>> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n>> index 74f4b80..8cd5592 100644\n>> --- a/drivers/clk/sprd/Makefile\n>> +++ b/drivers/clk/sprd/Makefile\n>> @@ -1,3 +1,4 @@\n>> obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o\n>> clk-sprd-y += common.o\n>> +clk-sprd-y += gate.o\n>> diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c\n>> new file mode 100644\n>> index 0000000..831ef81\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/gate.c\n>> @@ -0,0 +1,106 @@\n>> +/*\n>> + * Spreadtrum gate clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +\n>> +#include \"gate.h\"\n>> +\n>> +DEFINE_SPINLOCK(sprd_gate_lock);\n>> +EXPORT_SYMBOL_GPL(sprd_gate_lock);\n>> +\n>> +static void sprd_gate_endisable(const struct sprd_gate *sg, u32 en)\n>> +{\n>> + const struct sprd_clk_common *common = &sg->common;\n>> + unsigned long flags = 0;\n>> + unsigned int reg;\n>> + int set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;\n>> +\n>> + set ^= en;\n>> +\n>> + spin_lock_irqsave(common->lock, flags);\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> +\n>> + if (set)\n>> + reg |= sg->op_bit;\n>> + else\n>> + reg &= ~sg->op_bit;\n>> +\n>> + sprd_regmap_write(common->regmap, common->reg, reg);\n>> +\n>> + spin_unlock_irqrestore(common->lock, flags);\n>> +}\n>> +\n>> +static void clk_sc_gate_endisable(const struct sprd_gate *sg, u32 en)\n>> +{\n>> + const struct sprd_clk_common *common = &sg->common;\n>> + unsigned long flags = 0;\n>> + int set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;\n>> + unsigned int offset;\n>> +\n>> + set ^= en;\n>> +\n>> + /*\n>> + * Each set/clear gate clock has three registers:\n>> + * common->reg - base register\n>> + * common->reg + offset - set register\n>> + * common->reg + 2 * offset - clear register\n>> + */\n>> + offset = set ? sg->sc_offset : sg->sc_offset * 2;\n>> +\n>> + spin_lock_irqsave(common->lock, flags);\n>> + sprd_regmap_write(common->regmap, common->reg + offset,\n>> sg->op_bit);\n>> + spin_unlock_irqrestore(common->lock, flags);\n>> +}\n>> +\n>> +static void sprd_gate_disable(struct clk_hw *hw)\n>> +{\n>> + struct sprd_gate *sg = hw_to_sprd_gate(hw);\n>> +\n>> + if (sg->sc_offset)\n>> + clk_sc_gate_endisable(sg, 0);\n>> + else\n>> + sprd_gate_endisable(sg, 0);\n>> +}\n>> +\n>> +static int sprd_gate_enable(struct clk_hw *hw)\n>> +{\n>> + struct sprd_gate *sg = hw_to_sprd_gate(hw);\n>> +\n>> + if (sg->sc_offset)\n>> + clk_sc_gate_endisable(sg, 1);\n>> + else\n>> + sprd_gate_endisable(sg, 1);\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +static int sprd_gate_is_enabled(struct clk_hw *hw)\n>> +{\n>> + struct sprd_gate *sg = hw_to_sprd_gate(hw);\n>> + struct sprd_clk_common *common = &sg->common;\n>> + unsigned int reg;\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> +\n>> + if (sg->flags & CLK_GATE_SET_TO_DISABLE)\n>> + reg ^= sg->op_bit;\n>> +\n>> + reg &= sg->op_bit;\n>> +\n>> + return reg ? 1 : 0;\n>> +}\n>> +\n>> +const struct clk_ops sprd_gate_ops = {\n>> + .disable = sprd_gate_disable,\n>> + .enable = sprd_gate_enable,\n>> + .is_enabled = sprd_gate_is_enabled,\n>> +};\n>> +EXPORT_SYMBOL_GPL(sprd_gate_ops);\n>\n>\n> I think it would be better to have a set of ops for each mode,\n> sprd_gate_ops and sprd_sc_gate_ops rather than have each function decide\n> whether it should use set/clear registers or the base registers.\n>\n> So you can have a macro SPRD_GATE_CLK that doesn't take an sc_offet and\n> selects the sprd_gate_ops and another one that SPRD_SC_GATE_CLK using\n> sprd_sc_gate_ops that takes the sc_offset as parameter.\n>\n\nThat makes more sense, I will revise in the next version.\n\n> Also, I feel keeping enable/disable function separate would be nicer instead\n> of having \"endisable\" functions.\n\nTo avoid duplicate code, I prefer to keep the enable and disable\nfunctions together, but I agree that 'endisable' is indeed not good\nname for the function, I will revise the name to 'toggle' which I saw\nqcom clk drivers use, it might make more sense.\n\nThanks,\nChunyan\n\n>\n> Cheers,\n>\n>\n>> diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h\n>> new file mode 100644\n>> index 0000000..5aeb53c\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/gate.h\n>> @@ -0,0 +1,54 @@\n>> +/*\n>> + * Spreadtrum gate clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#ifndef _SPRD_GATE_H_\n>> +#define _SPRD_GATE_H_\n>> +\n>> +#include \"common.h\"\n>> +\n>> +struct sprd_gate {\n>> + u32 op_bit;\n>> + u16 flags;\n>> + u16 sc_offset;\n>> +\n>> + struct sprd_clk_common common;\n>> +};\n>> +\n>> +#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \\\n>> + _op_bit, _flags, _gate_flags) \\\n>> + struct sprd_gate _struct = { \\\n>> + .op_bit = _op_bit, \\\n>> + .sc_offset = _sc_offset, \\\n>> + .flags = _gate_flags, \\\n>> + .common = { \\\n>> + .regmap = NULL, \\\n>> + .reg = _reg, \\\n>> + .lock = &sprd_gate_lock, \\\n>> + .hw.init = CLK_HW_INIT(_name, \\\n>> + _parent, \\\n>> + &sprd_gate_ops, \\\n>> + _flags), \\\n>> + } \\\n>> + }\n>> +\n>> +static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)\n>> +{\n>> + struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);\n>> +\n>> + return container_of(common, struct sprd_gate, common);\n>> +}\n>> +\n>> +void sprd_gate_helper_disable(struct sprd_clk_common *common, u32 gate);\n>> +int sprd_gate_helper_enable(struct sprd_clk_common *common, u32 gate);\n>> +int sprd_gate_helper_is_enabled(struct sprd_clk_common *common, u32\n>> gate);\n>> +\n>> +extern const struct clk_ops sprd_gate_ops;\n>> +extern spinlock_t sprd_gate_lock;\n>> +\n>> +#endif /* _SPRD_GATE_H_ */\n>>\n>\n> --\n> Julien Thierry\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<5625af45-a071-4abf-88ed-f167abff1b73@arm.com>","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-5-chunyan.zhang@spreadtrum.com>\n\t<5625af45-a071-4abf-88ed-f167abff1b73@arm.com>","From":"Chunyan Zhang ","Date":"Fri, 3 Nov 2017 20:12:51 +0800","Message-ID":"","Subject":"Re: [PATCH V3 04/11] clk: sprd: add gate clock support","To":"Julien Thierry ","Cc":"Chunyan Zhang ,\n\tStephen Boyd ,\n\tMichael Turquette ,\n\tRob Herring , Mark Rutland ,\n\tCatalin Marinas ,\n\tWill Deacon ,\n\tlinux-clk , \n\t\"devicetree@vger.kernel.org\" ,\n\tArnd Bergmann , Mark Brown ,\n\tXiaolong Zhang ,\n\tBen Li , \"linux-arm-kernel@lists.infradead.org\" \n\t,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tOrson Zhai ","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1798570,"web_url":"http://patchwork.ozlabs.org/comment/1798570/","msgid":"","list_archive_url":null,"date":"2017-11-03T12:12:42","subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","submitter":{"id":64876,"url":"http://patchwork.ozlabs.org/api/people/64876/","name":"Chunyan Zhang","email":"zhang.lyra@gmail.com"},"content":"On 3 November 2017 at 02:22, Julien Thierry wrote:\n>\n>\n> On 02/11/17 18:11, Julien Thierry wrote:\n>>\n>> Hi,\n>>\n>> On 02/11/17 06:56, Chunyan Zhang wrote:\n>>>\n>>> This patch adds clock multiplexor support for Spreadtrum platforms,\n>>> the mux clocks also can be found in sprd composite clocks, so\n>>> provides two helpers that can be reused later on.\n>>>\n>>> Signed-off-by: Chunyan Zhang \n>>> ---\n>>> drivers/clk/sprd/Makefile | 1 +\n>>> drivers/clk/sprd/mux.c | 89\n>>> +++++++++++++++++++++++++++++++++++++++++++++++\n>>> drivers/clk/sprd/mux.h | 65 ++++++++++++++++++++++++++++++++++\n>>> 3 files changed, 155 insertions(+)\n>>> create mode 100644 drivers/clk/sprd/mux.c\n>>> create mode 100644 drivers/clk/sprd/mux.h\n>>>\n>>> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n>>> index 8cd5592..cee36b5 100644\n>>> --- a/drivers/clk/sprd/Makefile\n>>> +++ b/drivers/clk/sprd/Makefile\n>>> @@ -2,3 +2,4 @@ obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o\n>>> clk-sprd-y += common.o\n>>> clk-sprd-y += gate.o\n>>> +clk-sprd-y += mux.o\n>>> diff --git a/drivers/clk/sprd/mux.c b/drivers/clk/sprd/mux.c\n>>> new file mode 100644\n>>> index 0000000..5a344e0\n>>> --- /dev/null\n>>> +++ b/drivers/clk/sprd/mux.c\n>>> @@ -0,0 +1,89 @@\n>>> +/*\n>>> + * Spreadtrum multiplexer clock driver\n>>> + *\n>>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>>> + * Author: Chunyan Zhang \n>>> + *\n>>> + * SPDX-License-Identifier: GPL-2.0\n>>> + */\n>>> +\n>>> +#include \n>>> +#include \n>>> +#include \n>>> +\n>>> +#include \"mux.h\"\n>>> +\n>>> +DEFINE_SPINLOCK(sprd_mux_lock);\n>>> +EXPORT_SYMBOL_GPL(sprd_mux_lock);\n>>> +\n>>> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n>>> + const struct sprd_mux_internal *mux)\n>>> +{\n>>> + unsigned int reg;\n>>> + u8 parent;\n>>> + int num_parents;\n>>> + int i;\n>>> +\n>>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>>> + parent = reg >> mux->shift;\n>>> + parent &= (1 << mux->width) - 1;\n>>> +\n>>> + if (mux->table) {\n>>> + num_parents = clk_hw_get_num_parents(&common->hw);\n>>> +\n>>> + for (i = 0; i < num_parents; i++)\n>>> + if (parent == mux->table[i] ||\n>>> + (i < (num_parents - 1) && parent > mux->table[i] &&\n>>> + parent < mux->table[i + 1]))\n>>> + return i;\n>>> + if (i == num_parents)\n>>> + return i - 1;\n>>\n>>\n>> The if branch is not necessary since you only get there when the loop has\n>> finished, so the condition is always true. And the loop can be simplified\n>> to:\n>>\n>> for (i = 0; i < num_parents - 1; i++)\n>> if (parent >= mux->table[i] && parent < mux->table[i + 1])\n>> return i;\n>>\n>> return num_parents;\n>\n>\n> Oops, meant to say \"return num_parents - 1;\" on that last line.\n\nYes, that makes the code nicer, and thanks to your reminder, I even\nmake it more clean by moving the check for 'mux->table' up.\n\n\nThanks,\nChunyan\n\n>\n> --\n> Julien Thierry\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"U1pSb7iT\"; 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charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1798571,"web_url":"http://patchwork.ozlabs.org/comment/1798571/","msgid":"","list_archive_url":null,"date":"2017-11-03T12:12:35","subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","submitter":{"id":64876,"url":"http://patchwork.ozlabs.org/api/people/64876/","name":"Chunyan Zhang","email":"zhang.lyra@gmail.com"},"content":"Hi Julien,\n\nOn 3 November 2017 at 02:11, Julien Thierry wrote:\n> Hi,\n>\n>\n> On 02/11/17 06:56, Chunyan Zhang wrote:\n>>\n>> This patch adds clock multiplexor support for Spreadtrum platforms,\n>> the mux clocks also can be found in sprd composite clocks, so\n>> provides two helpers that can be reused later on.\n>>\n>> Signed-off-by: Chunyan Zhang \n>> ---\n>> drivers/clk/sprd/Makefile | 1 +\n>> drivers/clk/sprd/mux.c | 89\n>> +++++++++++++++++++++++++++++++++++++++++++++++\n>> drivers/clk/sprd/mux.h | 65 ++++++++++++++++++++++++++++++++++\n>> 3 files changed, 155 insertions(+)\n>> create mode 100644 drivers/clk/sprd/mux.c\n>> create mode 100644 drivers/clk/sprd/mux.h\n>>\n>> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n>> index 8cd5592..cee36b5 100644\n>> --- a/drivers/clk/sprd/Makefile\n>> +++ b/drivers/clk/sprd/Makefile\n>> @@ -2,3 +2,4 @@ obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o\n>> clk-sprd-y += common.o\n>> clk-sprd-y += gate.o\n>> +clk-sprd-y += mux.o\n>> diff --git a/drivers/clk/sprd/mux.c b/drivers/clk/sprd/mux.c\n>> new file mode 100644\n>> index 0000000..5a344e0\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/mux.c\n>> @@ -0,0 +1,89 @@\n>> +/*\n>> + * Spreadtrum multiplexer clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +#include \"mux.h\"\n>> +\n>> +DEFINE_SPINLOCK(sprd_mux_lock);\n>> +EXPORT_SYMBOL_GPL(sprd_mux_lock);\n>> +\n>> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux)\n>> +{\n>> + unsigned int reg;\n>> + u8 parent;\n>> + int num_parents;\n>> + int i;\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> + parent = reg >> mux->shift;\n>> + parent &= (1 << mux->width) - 1;\n>> +\n>> + if (mux->table) {\n>> + num_parents = clk_hw_get_num_parents(&common->hw);\n>> +\n>> + for (i = 0; i < num_parents; i++)\n>> + if (parent == mux->table[i] ||\n>> + (i < (num_parents - 1) && parent >\n>> mux->table[i] &&\n>> + parent < mux->table[i + 1]))\n>> + return i;\n>> + if (i == num_parents)\n>> + return i - 1;\n>\n>\n> The if branch is not necessary since you only get there when the loop has\n> finished, so the condition is always true. And the loop can be simplified\n> to:\n>\n> for (i = 0; i < num_parents - 1; i++)\n> if (parent >= mux->table[i] && parent < mux->table[i + 1])\n> return i;\n>\n> return num_parents;\n>\n>\n>\n>> + }\n>> +\n>> + return parent;\n>> +}\n>> +EXPORT_SYMBOL_GPL(sprd_mux_helper_get_parent);\n>> +\n>> +static u8 sprd_mux_get_parent(struct clk_hw *hw)\n>> +{\n>> + struct sprd_mux *cm = hw_to_sprd_mux(hw);\n>> +\n>> + return sprd_mux_helper_get_parent(&cm->common, &cm->mux);\n>> +}\n>> +\n>> +int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux,\n>> + u8 index)\n>> +{\n>> + unsigned long flags = 0;\n>> + unsigned int reg;\n>> +\n>> + if (mux->table)\n>> + index = mux->table[index];\n>> +\n>> + spin_lock_irqsave(common->lock, flags);\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> + reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift);\n>> + sprd_regmap_write(common->regmap, common->reg,\n>> + reg | (index << mux->shift));\n>> +\n>> + spin_unlock_irqrestore(common->lock, flags);\n>> +\n>> + return 0;\n>> +}\n>> +EXPORT_SYMBOL_GPL(sprd_mux_helper_set_parent);\n>> +\n>> +static int sprd_mux_set_parent(struct clk_hw *hw, u8 index)\n>> +{\n>> + struct sprd_mux *cm = hw_to_sprd_mux(hw);\n>> +\n>> + return sprd_mux_helper_set_parent(&cm->common, &cm->mux, index);\n>> +}\n>> +\n>> +const struct clk_ops sprd_mux_ops = {\n>> + .get_parent = sprd_mux_get_parent,\n>> + .set_parent = sprd_mux_set_parent,\n>> + .determine_rate = __clk_mux_determine_rate,\n>> +};\n>> +EXPORT_SYMBOL_GPL(sprd_mux_ops);\n>\n>\n> Same as with the other patch, I'd recommend have one set of ops for direct\n> mux and another one for a mux using a table to map the parents. Keeping\n> functions for both modes separate.\n>\n\nI might prefer to keep them together, since separating them will\nincrease many lines of code for maintaining :)\nAnd will export double of these functions, not only for mux driver but\nalso for composite driver.\nAnd I think the name like \"sprd_mux_helper_set_parent_table\" is a little long.\n\nThanks,\nChunyan\n\n> Cheers,\n>\n>\n>> diff --git a/drivers/clk/sprd/mux.h b/drivers/clk/sprd/mux.h\n>> new file mode 100644\n>> index 0000000..148ca8c\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/mux.h\n>> @@ -0,0 +1,65 @@\n>> +/*\n>> + * Spreadtrum multiplexer clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#ifndef _SPRD_MUX_H_\n>> +#define _SPRD_MUX_H_\n>> +\n>> +#include \"common.h\"\n>> +\n>> +struct sprd_mux_internal {\n>> + u8 shift;\n>> + u8 width;\n>> + const u8 *table;\n>> +};\n>> +\n>> +struct sprd_mux {\n>> + struct sprd_mux_internal mux;\n>> + struct sprd_clk_common common;\n>> +};\n>> +\n>> +#define _SPRD_MUX_CLK(_shift, _width, _table) \\\n>> + { \\\n>> + .shift = _shift, \\\n>> + .width = _width, \\\n>> + .table = _table, \\\n>> + }\n>> +\n>> +#define SPRD_MUX_CLK(_struct, _name, _parents, _table, \\\n>> + _reg, _shift, _width, \\\n>> + _flags) \\\n>> + struct sprd_mux _struct = { \\\n>> + .mux = _SPRD_MUX_CLK(_shift, _width, _table), \\\n>> + .common = { \\\n>> + .regmap = NULL, \\\n>> + .reg = _reg, \\\n>> + .lock = &sprd_mux_lock, \\\n>> + .hw.init = CLK_HW_INIT_PARENTS(_name, \\\n>> + _parents, \\\n>> + &sprd_mux_ops, \\\n>> + _flags), \\\n>> + } \\\n>> + }\n>> +\n>> +static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)\n>> +{\n>> + struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);\n>> +\n>> + return container_of(common, struct sprd_mux, common);\n>> +}\n>> +\n>> +extern const struct clk_ops sprd_mux_ops;\n>> +extern spinlock_t sprd_mux_lock;\n>> +\n>> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux);\n>> +int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux,\n>> + u8 index);\n>> +\n>> +#endif /* _SPRD_MUX_H_ */\n>>\n>\n> --\n> Julien Thierry\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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