[{"id":1798133,"web_url":"http://patchwork.ozlabs.org/comment/1798133/","msgid":"<5625af45-a071-4abf-88ed-f167abff1b73@arm.com>","list_archive_url":null,"date":"2017-11-02T17:45:50","subject":"Re: [PATCH V3 04/11] clk: sprd: add gate clock support","submitter":{"id":72256,"url":"http://patchwork.ozlabs.org/api/people/72256/","name":"Julien Thierry","email":"julien.thierry@arm.com"},"content":"Hi,\n\nOn 02/11/17 06:56, Chunyan Zhang wrote:\n> Some clocks on the Spreadtrum's SoCs are just simple gates. Add\n> support for those clocks.\n> \n> Signed-off-by: Chunyan Zhang \n> ---\n> drivers/clk/sprd/Makefile | 1 +\n> drivers/clk/sprd/gate.c | 106 ++++++++++++++++++++++++++++++++++++++++++++++\n> drivers/clk/sprd/gate.h | 54 +++++++++++++++++++++++\n> 3 files changed, 161 insertions(+)\n> create mode 100644 drivers/clk/sprd/gate.c\n> create mode 100644 drivers/clk/sprd/gate.h\n> \n> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n> index 74f4b80..8cd5592 100644\n> --- a/drivers/clk/sprd/Makefile\n> +++ b/drivers/clk/sprd/Makefile\n> @@ -1,3 +1,4 @@\n> obj-$(CONFIG_SPRD_COMMON_CLK)\t+= clk-sprd.o\n> \n> clk-sprd-y\t+= common.o\n> +clk-sprd-y\t+= gate.o\n> diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c\n> new file mode 100644\n> index 0000000..831ef81\n> --- /dev/null\n> +++ b/drivers/clk/sprd/gate.c\n> @@ -0,0 +1,106 @@\n> +/*\n> + * Spreadtrum gate clock driver\n> + *\n> + * Copyright (C) 2017 Spreadtrum, Inc.\n> + * Author: Chunyan Zhang \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#include \n> +#include \n> +\n> +#include \"gate.h\"\n> +\n> +DEFINE_SPINLOCK(sprd_gate_lock);\n> +EXPORT_SYMBOL_GPL(sprd_gate_lock);\n> +\n> +static void sprd_gate_endisable(const struct sprd_gate *sg, u32 en)\n> +{\n> +\tconst struct sprd_clk_common *common = &sg->common;\n> +\tunsigned long flags = 0;\n> +\tunsigned int reg;\n> +\tint set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;\n> +\n> +\tset ^= en;\n> +\n> +\tspin_lock_irqsave(common->lock, flags);\n> +\n> +\tsprd_regmap_read(common->regmap, common->reg, ®);\n> +\n> +\tif (set)\n> +\t\treg |= sg->op_bit;\n> +\telse\n> +\t\treg &= ~sg->op_bit;\n> +\n> +\tsprd_regmap_write(common->regmap, common->reg, reg);\n> +\n> +\tspin_unlock_irqrestore(common->lock, flags);\n> +}\n> +\n> +static void clk_sc_gate_endisable(const struct sprd_gate *sg, u32 en)\n> +{\n> +\tconst struct sprd_clk_common *common = &sg->common;\n> +\tunsigned long flags = 0;\n> +\tint set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;\n> +\tunsigned int offset;\n> +\n> +\tset ^= en;\n> +\n> +\t/*\n> +\t * Each set/clear gate clock has three registers:\n> +\t * common->reg\t\t\t- base register\n> +\t * common->reg + offset\t\t- set register\n> +\t * common->reg + 2 * offset\t- clear register\n> +\t */\n> +\toffset = set ? sg->sc_offset : sg->sc_offset * 2;\n> +\n> +\tspin_lock_irqsave(common->lock, flags);\n> +\tsprd_regmap_write(common->regmap, common->reg + offset, sg->op_bit);\n> +\tspin_unlock_irqrestore(common->lock, flags);\n> +}\n> +\n> +static void sprd_gate_disable(struct clk_hw *hw)\n> +{\n> +\tstruct sprd_gate *sg = hw_to_sprd_gate(hw);\n> +\n> +\tif (sg->sc_offset)\n> +\t\tclk_sc_gate_endisable(sg, 0);\n> +\telse\n> +\t\tsprd_gate_endisable(sg, 0);\n> +}\n> +\n> +static int sprd_gate_enable(struct clk_hw *hw)\n> +{\n> +\tstruct sprd_gate *sg = hw_to_sprd_gate(hw);\n> +\n> +\tif (sg->sc_offset)\n> +\t\tclk_sc_gate_endisable(sg, 1);\n> +\telse\n> +\t\tsprd_gate_endisable(sg, 1);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int sprd_gate_is_enabled(struct clk_hw *hw)\n> +{\n> +\tstruct sprd_gate *sg = hw_to_sprd_gate(hw);\n> +\tstruct sprd_clk_common *common = &sg->common;\n> +\tunsigned int reg;\n> +\n> +\tsprd_regmap_read(common->regmap, common->reg, ®);\n> +\n> +\tif (sg->flags & CLK_GATE_SET_TO_DISABLE)\n> +\t\treg ^= sg->op_bit;\n> +\n> +\treg &= sg->op_bit;\n> +\n> +\treturn reg ? 1 : 0;\n> +}\n> +\n> +const struct clk_ops sprd_gate_ops = {\n> +\t.disable\t= sprd_gate_disable,\n> +\t.enable\t\t= sprd_gate_enable,\n> +\t.is_enabled\t= sprd_gate_is_enabled,\n> +};\n> +EXPORT_SYMBOL_GPL(sprd_gate_ops);\n\nI think it would be better to have a set of ops for each mode,\nsprd_gate_ops and sprd_sc_gate_ops rather than have each function decide \nwhether it should use set/clear registers or the base registers.\n\nSo you can have a macro SPRD_GATE_CLK that doesn't take an sc_offet and \nselects the sprd_gate_ops and another one that SPRD_SC_GATE_CLK using \nsprd_sc_gate_ops that takes the sc_offset as parameter.\n\nAlso, I feel keeping enable/disable function separate would be nicer \ninstead of having \"endisable\" functions.\n\nCheers,\n\n> diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h\n> new file mode 100644\n> index 0000000..5aeb53c\n> --- /dev/null\n> +++ b/drivers/clk/sprd/gate.h\n> @@ -0,0 +1,54 @@\n> +/*\n> + * Spreadtrum gate clock driver\n> + *\n> + * Copyright (C) 2017 Spreadtrum, Inc.\n> + * Author: Chunyan Zhang \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#ifndef _SPRD_GATE_H_\n> +#define _SPRD_GATE_H_\n> +\n> +#include \"common.h\"\n> +\n> +struct sprd_gate {\n> +\tu32\t\t\top_bit;\n> +\tu16\t\t\tflags;\n> +\tu16\t\t\tsc_offset;\n> +\n> +\tstruct sprd_clk_common\tcommon;\n> +};\n> +\n> +#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset,\t\\\n> +\t\t _op_bit, _flags, _gate_flags)\t\t\t\\\n> +\tstruct sprd_gate _struct = {\t\t\t\t\t\\\n> +\t\t.op_bit\t\t= _op_bit,\t\t\t\t\\\n> +\t\t.sc_offset\t= _sc_offset,\t\t\t\t\\\n> +\t\t.flags\t\t= _gate_flags,\t\t\t\t\\\n> +\t\t.common\t= {\t\t\t\t\t\t\\\n> +\t\t\t.regmap\t\t= NULL,\t\t\t\t\\\n> +\t\t\t.reg\t\t= _reg,\t\t\t\t\\\n> +\t\t\t.lock\t\t= &sprd_gate_lock,\t\t\\\n> +\t\t\t.hw.init\t= CLK_HW_INIT(_name,\t\t\\\n> +\t\t\t\t\t\t _parent,\t\t\\\n> +\t\t\t\t\t\t &sprd_gate_ops,\t\\\n> +\t\t\t\t\t\t _flags),\t\t\\\n> +\t\t}\t\t\t\t\t\t\t\\\n> +\t}\n> +\n> +static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)\n> +{\n> +\tstruct sprd_clk_common *common = hw_to_sprd_clk_common(hw);\n> +\n> +\treturn container_of(common, struct sprd_gate, common);\n> +}\n> +\n> +void sprd_gate_helper_disable(struct sprd_clk_common *common, u32 gate);\n> +int sprd_gate_helper_enable(struct sprd_clk_common *common, u32 gate);\n> +int sprd_gate_helper_is_enabled(struct sprd_clk_common *common, u32 gate);\n> +\n> +extern const struct clk_ops sprd_gate_ops;\n> +extern spinlock_t sprd_gate_lock;\n> +\n> +#endif /* _SPRD_GATE_H_ */\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"uoIYP361\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3ySXZV408Rz9t2Q\n\tfor ;\n\tFri, 3 Nov 2017 04:46:23 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with 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h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From:\n\tReferences:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=WIsUG7Wia2hRcaGtkDpoJRxc6CvG3eBxtmvNz+tCs8U=;\n\tb=uoIYP361NM62UlcR+y3d86/Xk\n\t+IcuwPpTtUG0uTLxmjVijr7xfh98NofXgBhOTi8iJI1Ul3Bf82xIVf36zMuDDBX7YmXaipgkj3IPe\n\t48/BSMjxC9+f94FkHjIebQIXs3pyO5YGus5vh6scGdzy/H0e7hesNWFrL/jfysQh6k/xJXDhO1ufP\n\tXvM1WxVzhjgIIpCBlAcHOOQ0dlY006KVHgj6CC1noAcvlJ6mvA3tj0Du2DYkZ0Abhxz9KvS6L6vak\n\tEshQMO16+qd3kWez1dgGFjUOFrwrkt9iwB0t4FpjJ0tz/7SOcC+SXdt8TSspCsdUq9CSDc1ZScWLY\n\t3CdSzzN4A==;","Subject":"Re: [PATCH V3 04/11] clk: sprd: add gate clock support","To":"Chunyan Zhang ,\n\tStephen Boyd ,\n\tMichael Turquette , Rob Herring\n\t, Mark Rutland ","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-5-chunyan.zhang@spreadtrum.com>","From":"Julien Thierry ","Message-ID":"<5625af45-a071-4abf-88ed-f167abff1b73@arm.com>","Date":"Thu, 2 Nov 2017 17:45:50 +0000","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20171102065626.21835-5-chunyan.zhang@spreadtrum.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171102_104614_933658_213DD50C ","X-CRM114-Status":"GOOD ( 19.07 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Orson Zhai ,\n\tArnd Bergmann ,\n\tCatalin Marinas , \n\tBen Li , Will Deacon ,\n\tlinux-kernel@vger.kernel.org, Mark Brown ,\n\tChunyan Zhang , linux-clk@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tXiaolong Zhang ","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1798159,"web_url":"http://patchwork.ozlabs.org/comment/1798159/","msgid":"<532aed43-03bf-ea26-bdc2-d7deb1093f53@arm.com>","list_archive_url":null,"date":"2017-11-02T18:11:05","subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","submitter":{"id":72256,"url":"http://patchwork.ozlabs.org/api/people/72256/","name":"Julien Thierry","email":"julien.thierry@arm.com"},"content":"Hi,\n\nOn 02/11/17 06:56, Chunyan Zhang wrote:\n> This patch adds clock multiplexor support for Spreadtrum platforms,\n> the mux clocks also can be found in sprd composite clocks, so\n> provides two helpers that can be reused later on.\n> \n> Signed-off-by: Chunyan Zhang \n> ---\n> drivers/clk/sprd/Makefile | 1 +\n> drivers/clk/sprd/mux.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++\n> drivers/clk/sprd/mux.h | 65 ++++++++++++++++++++++++++++++++++\n> 3 files changed, 155 insertions(+)\n> create mode 100644 drivers/clk/sprd/mux.c\n> create mode 100644 drivers/clk/sprd/mux.h\n> \n> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n> index 8cd5592..cee36b5 100644\n> --- a/drivers/clk/sprd/Makefile\n> +++ b/drivers/clk/sprd/Makefile\n> @@ -2,3 +2,4 @@ obj-$(CONFIG_SPRD_COMMON_CLK)\t+= clk-sprd.o\n> \n> clk-sprd-y\t+= common.o\n> clk-sprd-y\t+= gate.o\n> +clk-sprd-y\t+= mux.o\n> diff --git a/drivers/clk/sprd/mux.c b/drivers/clk/sprd/mux.c\n> new file mode 100644\n> index 0000000..5a344e0\n> --- /dev/null\n> +++ b/drivers/clk/sprd/mux.c\n> @@ -0,0 +1,89 @@\n> +/*\n> + * Spreadtrum multiplexer clock driver\n> + *\n> + * Copyright (C) 2017 Spreadtrum, Inc.\n> + * Author: Chunyan Zhang \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +\n> +#include \"mux.h\"\n> +\n> +DEFINE_SPINLOCK(sprd_mux_lock);\n> +EXPORT_SYMBOL_GPL(sprd_mux_lock);\n> +\n> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n> +\t\t\t const struct sprd_mux_internal *mux)\n> +{\n> +\tunsigned int reg;\n> +\tu8 parent;\n> +\tint num_parents;\n> +\tint i;\n> +\n> +\tsprd_regmap_read(common->regmap, common->reg, ®);\n> +\tparent = reg >> mux->shift;\n> +\tparent &= (1 << mux->width) - 1;\n> +\n> +\tif (mux->table) {\n> +\t\tnum_parents = clk_hw_get_num_parents(&common->hw);\n> +\n> +\t\tfor (i = 0; i < num_parents; i++)\n> +\t\t\tif (parent == mux->table[i] ||\n> +\t\t\t (i < (num_parents - 1) && parent > mux->table[i] &&\n> +\t\t\t parent < mux->table[i + 1]))\n> +\t\t\t\treturn i;\n> +\t\tif (i == num_parents)\n> +\t\t\treturn i - 1;\n\nThe if branch is not necessary since you only get there when the loop \nhas finished, so the condition is always true. And the loop can be \nsimplified to:\n\nfor (i = 0; i < num_parents - 1; i++)\n\tif (parent >= mux->table[i] && parent < mux->table[i + 1])\n\t\treturn i;\n\nreturn num_parents;\n\n\n> +\t}\n> +\n> +\treturn parent;\n> +}\n> +EXPORT_SYMBOL_GPL(sprd_mux_helper_get_parent);\n> +\n> +static u8 sprd_mux_get_parent(struct clk_hw *hw)\n> +{\n> +\tstruct sprd_mux *cm = hw_to_sprd_mux(hw);\n> +\n> +\treturn sprd_mux_helper_get_parent(&cm->common, &cm->mux);\n> +}\n> +\n> +int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,\n> +\t\t\t const struct sprd_mux_internal *mux,\n> +\t\t\t u8 index)\n> +{\n> +\tunsigned long flags = 0;\n> +\tunsigned int reg;\n> +\n> +\tif (mux->table)\n> +\t\tindex = mux->table[index];\n> +\n> +\tspin_lock_irqsave(common->lock, flags);\n> +\n> +\tsprd_regmap_read(common->regmap, common->reg, ®);\n> +\treg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift);\n> +\tsprd_regmap_write(common->regmap, common->reg,\n> +\t\t\t reg | (index << mux->shift));\n> +\n> +\tspin_unlock_irqrestore(common->lock, flags);\n> +\n> +\treturn 0;\n> +}\n> +EXPORT_SYMBOL_GPL(sprd_mux_helper_set_parent);\n> +\n> +static int sprd_mux_set_parent(struct clk_hw *hw, u8 index)\n> +{\n> +\tstruct sprd_mux *cm = hw_to_sprd_mux(hw);\n> +\n> +\treturn sprd_mux_helper_set_parent(&cm->common, &cm->mux, index);\n> +}\n> +\n> +const struct clk_ops sprd_mux_ops = {\n> +\t.get_parent = sprd_mux_get_parent,\n> +\t.set_parent = sprd_mux_set_parent,\n> +\t.determine_rate = __clk_mux_determine_rate,\n> +};\n> +EXPORT_SYMBOL_GPL(sprd_mux_ops);\n\nSame as with the other patch, I'd recommend have one set of ops for \ndirect mux and another one for a mux using a table to map the parents. \nKeeping functions for both modes separate.\n\nCheers,\n\n> diff --git a/drivers/clk/sprd/mux.h b/drivers/clk/sprd/mux.h\n> new file mode 100644\n> index 0000000..148ca8c\n> --- /dev/null\n> +++ b/drivers/clk/sprd/mux.h\n> @@ -0,0 +1,65 @@\n> +/*\n> + * Spreadtrum multiplexer clock driver\n> + *\n> + * Copyright (C) 2017 Spreadtrum, Inc.\n> + * Author: Chunyan Zhang \n> + *\n> + * SPDX-License-Identifier: GPL-2.0\n> + */\n> +\n> +#ifndef _SPRD_MUX_H_\n> +#define _SPRD_MUX_H_\n> +\n> +#include \"common.h\"\n> +\n> +struct sprd_mux_internal {\n> +\tu8\t\tshift;\n> +\tu8\t\twidth;\n> +\tconst u8\t*table;\n> +};\n> +\n> +struct sprd_mux {\n> +\tstruct sprd_mux_internal mux;\n> +\tstruct sprd_clk_common\tcommon;\n> +};\n> +\n> +#define _SPRD_MUX_CLK(_shift, _width, _table)\t\t\\\n> +\t{\t\t\t\t\t\t\\\n> +\t\t.shift\t= _shift,\t\t\t\\\n> +\t\t.width\t= _width,\t\t\t\\\n> +\t\t.table\t= _table,\t\t\t\\\n> +\t}\n> +\n> +#define SPRD_MUX_CLK(_struct, _name, _parents, _table,\t\t\t\\\n> +\t\t\t\t _reg, _shift, _width,\t\t\\\n> +\t\t\t\t _flags)\t\t\t\t\\\n> +\tstruct sprd_mux _struct = {\t\t\t\t\t\\\n> +\t\t.mux\t= _SPRD_MUX_CLK(_shift, _width, _table),\t\\\n> +\t\t.common\t= {\t\t\t\t\t\t\\\n> +\t\t\t.regmap\t\t= NULL,\t\t\t\t\\\n> +\t\t\t.reg\t\t= _reg,\t\t\t\t\\\n> +\t\t\t.lock\t\t= &sprd_mux_lock,\t\t\\\n> +\t\t\t.hw.init = CLK_HW_INIT_PARENTS(_name,\t\t\\\n> +\t\t\t\t\t\t _parents,\t\\\n> +\t\t\t\t\t\t &sprd_mux_ops,\t\\\n> +\t\t\t\t\t\t _flags),\t\t\\\n> +\t\t}\t\t\t\t\t\t\t\\\n> +\t}\n> +\n> +static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)\n> +{\n> +\tstruct sprd_clk_common *common = hw_to_sprd_clk_common(hw);\n> +\n> +\treturn container_of(common, struct sprd_mux, common);\n> +}\n> +\n> +extern const struct clk_ops sprd_mux_ops;\n> +extern spinlock_t sprd_mux_lock;\n> +\n> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n> +\t\t\t const struct sprd_mux_internal *mux);\n> +int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,\n> +\t\t\t const struct sprd_mux_internal *mux,\n> +\t\t\t u8 index);\n> +\n> +#endif /* _SPRD_MUX_H_ */\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Thu, 2 Nov 2017 11:11:06 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From:\n\tReferences:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=eVIZk3L+bQmy3++mnqZjrK/7VdZzVGFo3f54hoN9g/Y=;\n\tb=ofP2kiaQAnAPI+xiMzFC3VNBK\n\tfJkzYJA60Ph9wOXnYdGKrZqFRP2VDQCmdMPGnVlLkrhgIRcZwDKqOcOqbPgcqSM1HwB4lfRAbCEXx\n\tkpfQzL5kn43ctmu4zNYiazdfJYjCK6b342e0Izt5RJri7JTcV2+xeQT2KofDm05U7f4T3LSBpohDD\n\tq7gYuah75Se5/e2tSidjSQLkfxCaF5BbORxSNEiq/93DqBkJ+VJsZoR/Q8Lu7Rte7oPF0pFh1VbxW\n\tuvAv/cIywCmjQDZ1gM6HXX3VurpoqXHO4jiK70C5rn4H3ZqoH5K0z2Uu6x2kIk1mwnUgOEeIoRNDq\n\tL5o8spwEw==;","Subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","To":"Chunyan Zhang ,\n\tStephen Boyd ,\n\tMichael Turquette , Rob Herring\n\t, Mark Rutland ","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-6-chunyan.zhang@spreadtrum.com>","From":"Julien Thierry ","Message-ID":"<532aed43-03bf-ea26-bdc2-d7deb1093f53@arm.com>","Date":"Thu, 2 Nov 2017 18:11:05 +0000","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20171102065626.21835-6-chunyan.zhang@spreadtrum.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171102_111137_609870_56CCEF8C ","X-CRM114-Status":"GOOD ( 19.58 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Orson Zhai ,\n\tArnd Bergmann ,\n\tCatalin Marinas , \n\tBen Li , Will Deacon ,\n\tlinux-kernel@vger.kernel.org, Mark Brown ,\n\tChunyan Zhang , linux-clk@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tXiaolong Zhang ","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1798170,"web_url":"http://patchwork.ozlabs.org/comment/1798170/","msgid":"","list_archive_url":null,"date":"2017-11-02T18:22:22","subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","submitter":{"id":72256,"url":"http://patchwork.ozlabs.org/api/people/72256/","name":"Julien Thierry","email":"julien.thierry@arm.com"},"content":"On 02/11/17 18:11, Julien Thierry wrote:\n> Hi,\n> \n> On 02/11/17 06:56, Chunyan Zhang wrote:\n>> This patch adds clock multiplexor support for Spreadtrum platforms,\n>> the mux clocks also can be found in sprd composite clocks, so\n>> provides two helpers that can be reused later on.\n>>\n>> Signed-off-by: Chunyan Zhang \n>> ---\n>> drivers/clk/sprd/Makefile | 1 +\n>> drivers/clk/sprd/mux.c | 89 \n>> +++++++++++++++++++++++++++++++++++++++++++++++\n>> drivers/clk/sprd/mux.h | 65 ++++++++++++++++++++++++++++++++++\n>> 3 files changed, 155 insertions(+)\n>> create mode 100644 drivers/clk/sprd/mux.c\n>> create mode 100644 drivers/clk/sprd/mux.h\n>>\n>> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n>> index 8cd5592..cee36b5 100644\n>> --- a/drivers/clk/sprd/Makefile\n>> +++ b/drivers/clk/sprd/Makefile\n>> @@ -2,3 +2,4 @@ obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o\n>> clk-sprd-y += common.o\n>> clk-sprd-y += gate.o\n>> +clk-sprd-y += mux.o\n>> diff --git a/drivers/clk/sprd/mux.c b/drivers/clk/sprd/mux.c\n>> new file mode 100644\n>> index 0000000..5a344e0\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/mux.c\n>> @@ -0,0 +1,89 @@\n>> +/*\n>> + * Spreadtrum multiplexer clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +#include \"mux.h\"\n>> +\n>> +DEFINE_SPINLOCK(sprd_mux_lock);\n>> +EXPORT_SYMBOL_GPL(sprd_mux_lock);\n>> +\n>> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux)\n>> +{\n>> + unsigned int reg;\n>> + u8 parent;\n>> + int num_parents;\n>> + int i;\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> + parent = reg >> mux->shift;\n>> + parent &= (1 << mux->width) - 1;\n>> +\n>> + if (mux->table) {\n>> + num_parents = clk_hw_get_num_parents(&common->hw);\n>> +\n>> + for (i = 0; i < num_parents; i++)\n>> + if (parent == mux->table[i] ||\n>> + (i < (num_parents - 1) && parent > mux->table[i] &&\n>> + parent < mux->table[i + 1]))\n>> + return i;\n>> + if (i == num_parents)\n>> + return i - 1;\n> \n> The if branch is not necessary since you only get there when the loop \n> has finished, so the condition is always true. And the loop can be \n> simplified to:\n> \n> for (i = 0; i < num_parents - 1; i++)\n> if (parent >= mux->table[i] && parent < mux->table[i + 1])\n> return i;\n> \n> return num_parents;\n\nOops, meant to say \"return num_parents - 1;\" on that last line.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Lw4Erxi1\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3ySYNg4fvWz9sNd\n\tfor ;\n\tFri, 3 Nov 2017 05:22:59 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1eAK8j-0004gD-4E; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<532aed43-03bf-ea26-bdc2-d7deb1093f53@arm.com>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171102_112247_856812_44088F0D ","X-CRM114-Status":"GOOD ( 16.15 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Orson Zhai ,\n\tArnd Bergmann ,\n\tCatalin Marinas , \n\tBen Li , Will Deacon ,\n\tlinux-kernel@vger.kernel.org, Mark Brown ,\n\tChunyan Zhang , linux-clk@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tXiaolong Zhang ","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1798568,"web_url":"http://patchwork.ozlabs.org/comment/1798568/","msgid":"","list_archive_url":null,"date":"2017-11-03T12:12:35","subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","submitter":{"id":64876,"url":"http://patchwork.ozlabs.org/api/people/64876/","name":"Chunyan Zhang","email":"zhang.lyra@gmail.com"},"content":"Hi Julien,\n\nOn 3 November 2017 at 02:11, Julien Thierry wrote:\n> Hi,\n>\n>\n> On 02/11/17 06:56, Chunyan Zhang wrote:\n>>\n>> This patch adds clock multiplexor support for Spreadtrum platforms,\n>> the mux clocks also can be found in sprd composite clocks, so\n>> provides two helpers that can be reused later on.\n>>\n>> Signed-off-by: Chunyan Zhang \n>> ---\n>> drivers/clk/sprd/Makefile | 1 +\n>> drivers/clk/sprd/mux.c | 89\n>> +++++++++++++++++++++++++++++++++++++++++++++++\n>> drivers/clk/sprd/mux.h | 65 ++++++++++++++++++++++++++++++++++\n>> 3 files changed, 155 insertions(+)\n>> create mode 100644 drivers/clk/sprd/mux.c\n>> create mode 100644 drivers/clk/sprd/mux.h\n>>\n>> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n>> index 8cd5592..cee36b5 100644\n>> --- a/drivers/clk/sprd/Makefile\n>> +++ b/drivers/clk/sprd/Makefile\n>> @@ -2,3 +2,4 @@ obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o\n>> clk-sprd-y += common.o\n>> clk-sprd-y += gate.o\n>> +clk-sprd-y += mux.o\n>> diff --git a/drivers/clk/sprd/mux.c b/drivers/clk/sprd/mux.c\n>> new file mode 100644\n>> index 0000000..5a344e0\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/mux.c\n>> @@ -0,0 +1,89 @@\n>> +/*\n>> + * Spreadtrum multiplexer clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +#include \n>> +\n>> +#include \"mux.h\"\n>> +\n>> +DEFINE_SPINLOCK(sprd_mux_lock);\n>> +EXPORT_SYMBOL_GPL(sprd_mux_lock);\n>> +\n>> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux)\n>> +{\n>> + unsigned int reg;\n>> + u8 parent;\n>> + int num_parents;\n>> + int i;\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> + parent = reg >> mux->shift;\n>> + parent &= (1 << mux->width) - 1;\n>> +\n>> + if (mux->table) {\n>> + num_parents = clk_hw_get_num_parents(&common->hw);\n>> +\n>> + for (i = 0; i < num_parents; i++)\n>> + if (parent == mux->table[i] ||\n>> + (i < (num_parents - 1) && parent >\n>> mux->table[i] &&\n>> + parent < mux->table[i + 1]))\n>> + return i;\n>> + if (i == num_parents)\n>> + return i - 1;\n>\n>\n> The if branch is not necessary since you only get there when the loop has\n> finished, so the condition is always true. And the loop can be simplified\n> to:\n>\n> for (i = 0; i < num_parents - 1; i++)\n> if (parent >= mux->table[i] && parent < mux->table[i + 1])\n> return i;\n>\n> return num_parents;\n>\n>\n>\n>> + }\n>> +\n>> + return parent;\n>> +}\n>> +EXPORT_SYMBOL_GPL(sprd_mux_helper_get_parent);\n>> +\n>> +static u8 sprd_mux_get_parent(struct clk_hw *hw)\n>> +{\n>> + struct sprd_mux *cm = hw_to_sprd_mux(hw);\n>> +\n>> + return sprd_mux_helper_get_parent(&cm->common, &cm->mux);\n>> +}\n>> +\n>> +int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux,\n>> + u8 index)\n>> +{\n>> + unsigned long flags = 0;\n>> + unsigned int reg;\n>> +\n>> + if (mux->table)\n>> + index = mux->table[index];\n>> +\n>> + spin_lock_irqsave(common->lock, flags);\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> + reg &= ~GENMASK(mux->width + mux->shift - 1, mux->shift);\n>> + sprd_regmap_write(common->regmap, common->reg,\n>> + reg | (index << mux->shift));\n>> +\n>> + spin_unlock_irqrestore(common->lock, flags);\n>> +\n>> + return 0;\n>> +}\n>> +EXPORT_SYMBOL_GPL(sprd_mux_helper_set_parent);\n>> +\n>> +static int sprd_mux_set_parent(struct clk_hw *hw, u8 index)\n>> +{\n>> + struct sprd_mux *cm = hw_to_sprd_mux(hw);\n>> +\n>> + return sprd_mux_helper_set_parent(&cm->common, &cm->mux, index);\n>> +}\n>> +\n>> +const struct clk_ops sprd_mux_ops = {\n>> + .get_parent = sprd_mux_get_parent,\n>> + .set_parent = sprd_mux_set_parent,\n>> + .determine_rate = __clk_mux_determine_rate,\n>> +};\n>> +EXPORT_SYMBOL_GPL(sprd_mux_ops);\n>\n>\n> Same as with the other patch, I'd recommend have one set of ops for direct\n> mux and another one for a mux using a table to map the parents. Keeping\n> functions for both modes separate.\n>\n\nI might prefer to keep them together, since separating them will\nincrease many lines of code for maintaining :)\nAnd will export double of these functions, not only for mux driver but\nalso for composite driver.\nAnd I think the name like \"sprd_mux_helper_set_parent_table\" is a little long.\n\nThanks,\nChunyan\n\n> Cheers,\n>\n>\n>> diff --git a/drivers/clk/sprd/mux.h b/drivers/clk/sprd/mux.h\n>> new file mode 100644\n>> index 0000000..148ca8c\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/mux.h\n>> @@ -0,0 +1,65 @@\n>> +/*\n>> + * Spreadtrum multiplexer clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#ifndef _SPRD_MUX_H_\n>> +#define _SPRD_MUX_H_\n>> +\n>> +#include \"common.h\"\n>> +\n>> +struct sprd_mux_internal {\n>> + u8 shift;\n>> + u8 width;\n>> + const u8 *table;\n>> +};\n>> +\n>> +struct sprd_mux {\n>> + struct sprd_mux_internal mux;\n>> + struct sprd_clk_common common;\n>> +};\n>> +\n>> +#define _SPRD_MUX_CLK(_shift, _width, _table) \\\n>> + { \\\n>> + .shift = _shift, \\\n>> + .width = _width, \\\n>> + .table = _table, \\\n>> + }\n>> +\n>> +#define SPRD_MUX_CLK(_struct, _name, _parents, _table, \\\n>> + _reg, _shift, _width, \\\n>> + _flags) \\\n>> + struct sprd_mux _struct = { \\\n>> + .mux = _SPRD_MUX_CLK(_shift, _width, _table), \\\n>> + .common = { \\\n>> + .regmap = NULL, \\\n>> + .reg = _reg, \\\n>> + .lock = &sprd_mux_lock, \\\n>> + .hw.init = CLK_HW_INIT_PARENTS(_name, \\\n>> + _parents, \\\n>> + &sprd_mux_ops, \\\n>> + _flags), \\\n>> + } \\\n>> + }\n>> +\n>> +static inline struct sprd_mux *hw_to_sprd_mux(const struct clk_hw *hw)\n>> +{\n>> + struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);\n>> +\n>> + return container_of(common, struct sprd_mux, common);\n>> +}\n>> +\n>> +extern const struct clk_ops sprd_mux_ops;\n>> +extern spinlock_t sprd_mux_lock;\n>> +\n>> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux);\n>> +int sprd_mux_helper_set_parent(const struct sprd_clk_common *common,\n>> + const struct sprd_mux_internal *mux,\n>> + u8 index);\n>> +\n>> +#endif /* _SPRD_MUX_H_ */\n>>\n>\n> --\n> Julien Thierry","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1798572,"web_url":"http://patchwork.ozlabs.org/comment/1798572/","msgid":"","list_archive_url":null,"date":"2017-11-03T12:12:51","subject":"Re: [PATCH V3 04/11] clk: sprd: add gate clock support","submitter":{"id":64876,"url":"http://patchwork.ozlabs.org/api/people/64876/","name":"Chunyan Zhang","email":"zhang.lyra@gmail.com"},"content":"Hi Julien,\n\nOn 3 November 2017 at 01:45, Julien Thierry wrote:\n> Hi,\n>\n>\n> On 02/11/17 06:56, Chunyan Zhang wrote:\n>>\n>> Some clocks on the Spreadtrum's SoCs are just simple gates. Add\n>> support for those clocks.\n>>\n>> Signed-off-by: Chunyan Zhang \n>> ---\n>> drivers/clk/sprd/Makefile | 1 +\n>> drivers/clk/sprd/gate.c | 106\n>> ++++++++++++++++++++++++++++++++++++++++++++++\n>> drivers/clk/sprd/gate.h | 54 +++++++++++++++++++++++\n>> 3 files changed, 161 insertions(+)\n>> create mode 100644 drivers/clk/sprd/gate.c\n>> create mode 100644 drivers/clk/sprd/gate.h\n>>\n>> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n>> index 74f4b80..8cd5592 100644\n>> --- a/drivers/clk/sprd/Makefile\n>> +++ b/drivers/clk/sprd/Makefile\n>> @@ -1,3 +1,4 @@\n>> obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o\n>> clk-sprd-y += common.o\n>> +clk-sprd-y += gate.o\n>> diff --git a/drivers/clk/sprd/gate.c b/drivers/clk/sprd/gate.c\n>> new file mode 100644\n>> index 0000000..831ef81\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/gate.c\n>> @@ -0,0 +1,106 @@\n>> +/*\n>> + * Spreadtrum gate clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#include \n>> +#include \n>> +\n>> +#include \"gate.h\"\n>> +\n>> +DEFINE_SPINLOCK(sprd_gate_lock);\n>> +EXPORT_SYMBOL_GPL(sprd_gate_lock);\n>> +\n>> +static void sprd_gate_endisable(const struct sprd_gate *sg, u32 en)\n>> +{\n>> + const struct sprd_clk_common *common = &sg->common;\n>> + unsigned long flags = 0;\n>> + unsigned int reg;\n>> + int set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;\n>> +\n>> + set ^= en;\n>> +\n>> + spin_lock_irqsave(common->lock, flags);\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> +\n>> + if (set)\n>> + reg |= sg->op_bit;\n>> + else\n>> + reg &= ~sg->op_bit;\n>> +\n>> + sprd_regmap_write(common->regmap, common->reg, reg);\n>> +\n>> + spin_unlock_irqrestore(common->lock, flags);\n>> +}\n>> +\n>> +static void clk_sc_gate_endisable(const struct sprd_gate *sg, u32 en)\n>> +{\n>> + const struct sprd_clk_common *common = &sg->common;\n>> + unsigned long flags = 0;\n>> + int set = sg->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;\n>> + unsigned int offset;\n>> +\n>> + set ^= en;\n>> +\n>> + /*\n>> + * Each set/clear gate clock has three registers:\n>> + * common->reg - base register\n>> + * common->reg + offset - set register\n>> + * common->reg + 2 * offset - clear register\n>> + */\n>> + offset = set ? sg->sc_offset : sg->sc_offset * 2;\n>> +\n>> + spin_lock_irqsave(common->lock, flags);\n>> + sprd_regmap_write(common->regmap, common->reg + offset,\n>> sg->op_bit);\n>> + spin_unlock_irqrestore(common->lock, flags);\n>> +}\n>> +\n>> +static void sprd_gate_disable(struct clk_hw *hw)\n>> +{\n>> + struct sprd_gate *sg = hw_to_sprd_gate(hw);\n>> +\n>> + if (sg->sc_offset)\n>> + clk_sc_gate_endisable(sg, 0);\n>> + else\n>> + sprd_gate_endisable(sg, 0);\n>> +}\n>> +\n>> +static int sprd_gate_enable(struct clk_hw *hw)\n>> +{\n>> + struct sprd_gate *sg = hw_to_sprd_gate(hw);\n>> +\n>> + if (sg->sc_offset)\n>> + clk_sc_gate_endisable(sg, 1);\n>> + else\n>> + sprd_gate_endisable(sg, 1);\n>> +\n>> + return 0;\n>> +}\n>> +\n>> +static int sprd_gate_is_enabled(struct clk_hw *hw)\n>> +{\n>> + struct sprd_gate *sg = hw_to_sprd_gate(hw);\n>> + struct sprd_clk_common *common = &sg->common;\n>> + unsigned int reg;\n>> +\n>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>> +\n>> + if (sg->flags & CLK_GATE_SET_TO_DISABLE)\n>> + reg ^= sg->op_bit;\n>> +\n>> + reg &= sg->op_bit;\n>> +\n>> + return reg ? 1 : 0;\n>> +}\n>> +\n>> +const struct clk_ops sprd_gate_ops = {\n>> + .disable = sprd_gate_disable,\n>> + .enable = sprd_gate_enable,\n>> + .is_enabled = sprd_gate_is_enabled,\n>> +};\n>> +EXPORT_SYMBOL_GPL(sprd_gate_ops);\n>\n>\n> I think it would be better to have a set of ops for each mode,\n> sprd_gate_ops and sprd_sc_gate_ops rather than have each function decide\n> whether it should use set/clear registers or the base registers.\n>\n> So you can have a macro SPRD_GATE_CLK that doesn't take an sc_offet and\n> selects the sprd_gate_ops and another one that SPRD_SC_GATE_CLK using\n> sprd_sc_gate_ops that takes the sc_offset as parameter.\n>\n\nThat makes more sense, I will revise in the next version.\n\n> Also, I feel keeping enable/disable function separate would be nicer instead\n> of having \"endisable\" functions.\n\nTo avoid duplicate code, I prefer to keep the enable and disable\nfunctions together, but I agree that 'endisable' is indeed not good\nname for the function, I will revise the name to 'toggle' which I saw\nqcom clk drivers use, it might make more sense.\n\nThanks,\nChunyan\n\n>\n> Cheers,\n>\n>\n>> diff --git a/drivers/clk/sprd/gate.h b/drivers/clk/sprd/gate.h\n>> new file mode 100644\n>> index 0000000..5aeb53c\n>> --- /dev/null\n>> +++ b/drivers/clk/sprd/gate.h\n>> @@ -0,0 +1,54 @@\n>> +/*\n>> + * Spreadtrum gate clock driver\n>> + *\n>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>> + * Author: Chunyan Zhang \n>> + *\n>> + * SPDX-License-Identifier: GPL-2.0\n>> + */\n>> +\n>> +#ifndef _SPRD_GATE_H_\n>> +#define _SPRD_GATE_H_\n>> +\n>> +#include \"common.h\"\n>> +\n>> +struct sprd_gate {\n>> + u32 op_bit;\n>> + u16 flags;\n>> + u16 sc_offset;\n>> +\n>> + struct sprd_clk_common common;\n>> +};\n>> +\n>> +#define SPRD_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \\\n>> + _op_bit, _flags, _gate_flags) \\\n>> + struct sprd_gate _struct = { \\\n>> + .op_bit = _op_bit, \\\n>> + .sc_offset = _sc_offset, \\\n>> + .flags = _gate_flags, \\\n>> + .common = { \\\n>> + .regmap = NULL, \\\n>> + .reg = _reg, \\\n>> + .lock = &sprd_gate_lock, \\\n>> + .hw.init = CLK_HW_INIT(_name, \\\n>> + _parent, \\\n>> + &sprd_gate_ops, \\\n>> + _flags), \\\n>> + } \\\n>> + }\n>> +\n>> +static inline struct sprd_gate *hw_to_sprd_gate(const struct clk_hw *hw)\n>> +{\n>> + struct sprd_clk_common *common = hw_to_sprd_clk_common(hw);\n>> +\n>> + return container_of(common, struct sprd_gate, common);\n>> +}\n>> +\n>> +void sprd_gate_helper_disable(struct sprd_clk_common *common, u32 gate);\n>> +int sprd_gate_helper_enable(struct sprd_clk_common *common, u32 gate);\n>> +int sprd_gate_helper_is_enabled(struct sprd_clk_common *common, u32\n>> gate);\n>> +\n>> +extern const struct clk_ops sprd_gate_ops;\n>> +extern spinlock_t sprd_gate_lock;\n>> +\n>> +#endif /* _SPRD_GATE_H_ */\n>>\n>\n> --\n> Julien Thierry","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"L/vC5N7o\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com 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(PDT)","MIME-Version":"1.0","In-Reply-To":"<5625af45-a071-4abf-88ed-f167abff1b73@arm.com>","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-5-chunyan.zhang@spreadtrum.com>\n\t<5625af45-a071-4abf-88ed-f167abff1b73@arm.com>","From":"Chunyan Zhang ","Date":"Fri, 3 Nov 2017 20:12:51 +0800","Message-ID":"","Subject":"Re: [PATCH V3 04/11] clk: sprd: add gate clock support","To":"Julien Thierry ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171103_051355_431834_30EFB978 ","X-CRM114-Status":"GOOD ( 20.35 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:4010:c07:0:0:0:244 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (zhang.lyra[at]gmail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland ,\n\t\"devicetree@vger.kernel.org\" ,\n\tOrson Zhai , Arnd Bergmann ,\n\tCatalin Marinas ,\n\tMichael Turquette ,\n\tBen Li , Stephen Boyd ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tWill Deacon , Rob Herring , \n\tMark Brown ,\n\tChunyan Zhang , \n\tlinux-clk ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t, \n\tXiaolong Zhang ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1798576,"web_url":"http://patchwork.ozlabs.org/comment/1798576/","msgid":"","list_archive_url":null,"date":"2017-11-03T12:12:42","subject":"Re: [PATCH V3 05/11] clk: sprd: add mux clock support","submitter":{"id":64876,"url":"http://patchwork.ozlabs.org/api/people/64876/","name":"Chunyan Zhang","email":"zhang.lyra@gmail.com"},"content":"On 3 November 2017 at 02:22, Julien Thierry wrote:\n>\n>\n> On 02/11/17 18:11, Julien Thierry wrote:\n>>\n>> Hi,\n>>\n>> On 02/11/17 06:56, Chunyan Zhang wrote:\n>>>\n>>> This patch adds clock multiplexor support for Spreadtrum platforms,\n>>> the mux clocks also can be found in sprd composite clocks, so\n>>> provides two helpers that can be reused later on.\n>>>\n>>> Signed-off-by: Chunyan Zhang \n>>> ---\n>>> drivers/clk/sprd/Makefile | 1 +\n>>> drivers/clk/sprd/mux.c | 89\n>>> +++++++++++++++++++++++++++++++++++++++++++++++\n>>> drivers/clk/sprd/mux.h | 65 ++++++++++++++++++++++++++++++++++\n>>> 3 files changed, 155 insertions(+)\n>>> create mode 100644 drivers/clk/sprd/mux.c\n>>> create mode 100644 drivers/clk/sprd/mux.h\n>>>\n>>> diff --git a/drivers/clk/sprd/Makefile b/drivers/clk/sprd/Makefile\n>>> index 8cd5592..cee36b5 100644\n>>> --- a/drivers/clk/sprd/Makefile\n>>> +++ b/drivers/clk/sprd/Makefile\n>>> @@ -2,3 +2,4 @@ obj-$(CONFIG_SPRD_COMMON_CLK) += clk-sprd.o\n>>> clk-sprd-y += common.o\n>>> clk-sprd-y += gate.o\n>>> +clk-sprd-y += mux.o\n>>> diff --git a/drivers/clk/sprd/mux.c b/drivers/clk/sprd/mux.c\n>>> new file mode 100644\n>>> index 0000000..5a344e0\n>>> --- /dev/null\n>>> +++ b/drivers/clk/sprd/mux.c\n>>> @@ -0,0 +1,89 @@\n>>> +/*\n>>> + * Spreadtrum multiplexer clock driver\n>>> + *\n>>> + * Copyright (C) 2017 Spreadtrum, Inc.\n>>> + * Author: Chunyan Zhang \n>>> + *\n>>> + * SPDX-License-Identifier: GPL-2.0\n>>> + */\n>>> +\n>>> +#include \n>>> +#include \n>>> +#include \n>>> +\n>>> +#include \"mux.h\"\n>>> +\n>>> +DEFINE_SPINLOCK(sprd_mux_lock);\n>>> +EXPORT_SYMBOL_GPL(sprd_mux_lock);\n>>> +\n>>> +u8 sprd_mux_helper_get_parent(const struct sprd_clk_common *common,\n>>> + const struct sprd_mux_internal *mux)\n>>> +{\n>>> + unsigned int reg;\n>>> + u8 parent;\n>>> + int num_parents;\n>>> + int i;\n>>> +\n>>> + sprd_regmap_read(common->regmap, common->reg, ®);\n>>> + parent = reg >> mux->shift;\n>>> + parent &= (1 << mux->width) - 1;\n>>> +\n>>> + if (mux->table) {\n>>> + num_parents = clk_hw_get_num_parents(&common->hw);\n>>> +\n>>> + for (i = 0; i < num_parents; i++)\n>>> + if (parent == mux->table[i] ||\n>>> + (i < (num_parents - 1) && parent > mux->table[i] &&\n>>> + parent < mux->table[i + 1]))\n>>> + return i;\n>>> + if (i == num_parents)\n>>> + return i - 1;\n>>\n>>\n>> The if branch is not necessary since you only get there when the loop has\n>> finished, so the condition is always true. And the loop can be simplified\n>> to:\n>>\n>> for (i = 0; i < num_parents - 1; i++)\n>> if (parent >= mux->table[i] && parent < mux->table[i + 1])\n>> return i;\n>>\n>> return num_parents;\n>\n>\n> Oops, meant to say \"return num_parents - 1;\" on that last line.\n\nYes, that makes the code nicer, and thanks to your reminder, I even\nmake it more clean by moving the check for 'mux->table' up.\n\n\nThanks,\nChunyan\n\n>\n> --\n> Julien Thierry","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Cp7DRVoL\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"U1pSb7iT\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1799850,"web_url":"http://patchwork.ozlabs.org/comment/1799850/","msgid":"<20171106171519.xomnca72adqtzm2n@rob-hp-laptop>","list_archive_url":null,"date":"2017-11-06T17:15:19","subject":"Re: [PATCH V3 02/11] dt-bindings: Add Spreadtrum clock binding\n\tdocumentation","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Nov 02, 2017 at 02:56:17PM +0800, Chunyan Zhang wrote:\n> Introduce a new binding with its documentation for Spreadtrum clock\n> sub-framework.\n> \n> Signed-off-by: Chunyan Zhang \n> ---\n> Documentation/devicetree/bindings/clock/sprd.txt | 55 ++++++++++++++++++++++++\n> 1 file changed, 55 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/clock/sprd.txt\n> \n> diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd.txt\n> new file mode 100644\n> index 0000000..5c09529\n> --- /dev/null\n> +++ b/Documentation/devicetree/bindings/clock/sprd.txt\n> @@ -0,0 +1,55 @@\n> +Spreadtrum Clock Binding\n> +------------------------\n> +\n> +Required properties:\n> +- compatible: should contain the following compatible strings:\n> +\t- \"sprd,sc9860-pmu-gate\"\n> +\t- \"sprd,sc9860-pll\"\n> +\t- \"sprd,sc9860-ap-clk\"\n> +\t- \"sprd,sc9860-aon-prediv\"\n> +\t- \"sprd,sc9860-apahb-gate\"\n> +\t- \"sprd,sc9860-aon-gate\"\n> +\t- \"sprd,sc9860-aonsecure-clk\"\n> +\t- \"sprd,sc9860-agcp-gate\"\n> +\t- \"sprd,sc9860-gpu-clk\"\n> +\t- \"sprd,sc9860-vsp-clk\"\n> +\t- \"sprd,sc9860-vsp-gate\"\n> +\t- \"sprd,sc9860-cam-clk\"\n> +\t- \"sprd,sc9860-cam-gate\"\n> +\t- \"sprd,sc9860-disp-clk\"\n> +\t- \"sprd,sc9860-disp-gate\"\n> +\t- \"sprd,sc9860-apapb-gate\"\n> +\n> +- #clock-cells: must be 1\n> +\n> +- clocks : shall be the input parent clock(s) phandle for the clock.\n\nYou need to document how many clocks for each block.\n\n> +\n> +Optional properties:\n> +\n> +- reg:\tContain the registers base address and length. It must be configured only if no 'sprd,syscon' under the node.\n> +\n> +- sprd,syscon: phandle to the syscon which is in the same address area with the clock.\n> +\n> +Example:\n> +\n> +\tpmu_gate: pmu-gate {\n> +\t\tcompatible = \"sprd,sc9860-pmu-gate\";\n> +\t\tsprd,syscon = <&pmu_apb>;\n\nIdeally, the pmu-gate node would be a child of pmu_apb and use the reg \nproperty if clock registers are a contiguous range. Then you don't need \nthis phandle.\n\n> +\t\tclocks = <&ext_26m>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tpll: pll {\n> +\t\tcompatible = \"sprd,sc9860-pll\";\n> +\t\tsprd,syscon = <&ana_apb>;\n\nSame here.\n\n> +\t\tclocks = <&pmu_gate 0>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tap_clk: clock-controller@20000000 {\n> +\t\tcompatible = \"sprd,sc9860-ap-clk\";\n> +\t\treg = <0 0x20000000 0 0x400>;\n> +\t\tclocks = <&ext_26m>, <&pll 0>,\n> +\t\t\t <&pmu_gate 0>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"NNC8MrVs\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1800022,"web_url":"http://patchwork.ozlabs.org/comment/1800022/","msgid":"<20171106214335.qvuvcwahemnpwftt@rob-hp-laptop>","list_archive_url":null,"date":"2017-11-06T21:43:35","subject":"Re: [PATCH V3 09/11] clk: sprd: add clocks support for SC9860","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Nov 02, 2017 at 02:56:24PM +0800, Chunyan Zhang wrote:\n> This patch added the list of clocks for Spreadtrum's SC9860 SoC,\n> together with clock initialization code.\n> \n> Signed-off-by: Chunyan Zhang \n> ---\n> drivers/clk/sprd/Kconfig | 10 +\n> drivers/clk/sprd/Makefile | 3 +\n> drivers/clk/sprd/sc9860-clk.c | 1987 +++++++++++++++++++++++++++\n> include/dt-bindings/clock/sprd,sc9860-clk.h | 408 ++++++\n\nThis belongs in the binding doc patch.\n\nRob","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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\n\tMon, 06 Nov 2017 13:43:36 -0800 (PST)","Date":"Mon, 6 Nov 2017 15:43:35 -0600","From":"Rob Herring ","To":"Chunyan Zhang ","Subject":"Re: [PATCH V3 09/11] clk: sprd: add clocks support for SC9860","Message-ID":"<20171106214335.qvuvcwahemnpwftt@rob-hp-laptop>","References":"<20171102065626.21835-1-chunyan.zhang@spreadtrum.com>\n\t<20171102065626.21835-10-chunyan.zhang@spreadtrum.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20171102065626.21835-10-chunyan.zhang@spreadtrum.com>","User-Agent":"NeoMutt/20170609 (1.8.3)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171106_134358_035723_B257F8A5 ","X-CRM114-Status":"GOOD ( 10.43 )","X-Spam-Score":"-1.0 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t0.5 RCVD_IN_SORBS_SPAM RBL: SORBS: sender is a spam source\n\t[209.85.218.66 listed in dnsbl.sorbs.net]\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [209.85.218.66 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[209.85.218.66 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.2 FREEMAIL_ENVFROM_END_DIGIT Envelope-from freemail username ends\n\tin digit (robherring2[at]gmail.com)\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (robherring2[at]gmail.com)\n\t0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level\n\tmail domains are different\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders\n\t0.2 FREEMAIL_FORGED_FROMDOMAIN 2nd level domains in From and\n\tEnvelopeFrom freemail headers are different","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , devicetree@vger.kernel.org,\n\tOrson Zhai , Arnd Bergmann ,\n\tCatalin Marinas ,\n\tMichael Turquette ,\n\tBen Li , \n\tStephen Boyd , linux-kernel@vger.kernel.org,\n\tWill Deacon , Mark Brown ,\n\tChunyan Zhang , linux-clk@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tXiaolong Zhang ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1800263,"web_url":"http://patchwork.ozlabs.org/comment/1800263/","msgid":"","list_archive_url":null,"date":"2017-11-07T07:01:09","subject":"Re: [PATCH V3 02/11] dt-bindings: Add Spreadtrum clock binding\n\tdocumentation","submitter":{"id":64876,"url":"http://patchwork.ozlabs.org/api/people/64876/","name":"Chunyan Zhang","email":"zhang.lyra@gmail.com"},"content":"Hi Rob,\n\nOn 7 November 2017 at 01:15, Rob Herring wrote:\n> On Thu, Nov 02, 2017 at 02:56:17PM +0800, Chunyan Zhang wrote:\n>> Introduce a new binding with its documentation for Spreadtrum clock\n>> sub-framework.\n>>\n>> Signed-off-by: Chunyan Zhang \n>> ---\n>> Documentation/devicetree/bindings/clock/sprd.txt | 55 ++++++++++++++++++++++++\n>> 1 file changed, 55 insertions(+)\n>> create mode 100644 Documentation/devicetree/bindings/clock/sprd.txt\n>>\n>> diff --git a/Documentation/devicetree/bindings/clock/sprd.txt b/Documentation/devicetree/bindings/clock/sprd.txt\n>> new file mode 100644\n>> index 0000000..5c09529\n>> --- /dev/null\n>> +++ b/Documentation/devicetree/bindings/clock/sprd.txt\n>> @@ -0,0 +1,55 @@\n>> +Spreadtrum Clock Binding\n>> +------------------------\n>> +\n>> +Required properties:\n>> +- compatible: should contain the following compatible strings:\n>> + - \"sprd,sc9860-pmu-gate\"\n>> + - \"sprd,sc9860-pll\"\n>> + - \"sprd,sc9860-ap-clk\"\n>> + - \"sprd,sc9860-aon-prediv\"\n>> + - \"sprd,sc9860-apahb-gate\"\n>> + - \"sprd,sc9860-aon-gate\"\n>> + - \"sprd,sc9860-aonsecure-clk\"\n>> + - \"sprd,sc9860-agcp-gate\"\n>> + - \"sprd,sc9860-gpu-clk\"\n>> + - \"sprd,sc9860-vsp-clk\"\n>> + - \"sprd,sc9860-vsp-gate\"\n>> + - \"sprd,sc9860-cam-clk\"\n>> + - \"sprd,sc9860-cam-gate\"\n>> + - \"sprd,sc9860-disp-clk\"\n>> + - \"sprd,sc9860-disp-gate\"\n>> + - \"sprd,sc9860-apapb-gate\"\n>> +\n>> +- #clock-cells: must be 1\n>> +\n>> +- clocks : shall be the input parent clock(s) phandle for the clock.\n>\n> You need to document how many clocks for each block.\n\nIt depends, \"clocks\" property here just simply shows which clock group\nthe clock's parents are in.\nThe detailed dependency relationship (i.e. how many parents and which\nare the parents) are implemented in driver code.\n\nOk, I should address more, will do in the next version.\n\n>\n>> +\n>> +Optional properties:\n>> +\n>> +- reg: Contain the registers base address and length. It must be configured only if no 'sprd,syscon' under the node.\n>> +\n>> +- sprd,syscon: phandle to the syscon which is in the same address area with the clock.\n>> +\n>> +Example:\n>> +\n>> + pmu_gate: pmu-gate {\n>> + compatible = \"sprd,sc9860-pmu-gate\";\n>> + sprd,syscon = <&pmu_apb>;\n>\n> Ideally, the pmu-gate node would be a child of pmu_apb and use the reg\n> property if clock registers are a contiguous range. Then you don't need\n> this phandle.\n\nThe pmu-gate is actually a clock independent from the 'pmu_apb' syscon\ndevice, using a reference to syscon node instead of a reg property is\njust to avoid mapping the same address areas repeatedly. Spreadtrum's\nclock h/w design is a little complicated, after discussing with Arnd\nand Stephen, I then chose to implement in this way.\n\nI guess the name of 'pmu_apb' might be confused, it's actually not a\nbus, but a global address area stored a lot of registers shared by a\nfew devices including some clocks. I think I'd better use another\nname instead of pmu_apb :)\n\nPlease let me know if I'm missing something here.\n\nThanks,\nChunyan\n\n>\n>> + clocks = <&ext_26m>;\n>> + #clock-cells = <1>;\n>> + };\n>> +\n>> + pll: pll {\n>> + compatible = \"sprd,sc9860-pll\";\n>> + sprd,syscon = <&ana_apb>;\n>\n> Same here.\n>\n>> + clocks = <&pmu_gate 0>;\n>> + #clock-cells = <1>;\n>> + };\n>> +\n>> + ap_clk: clock-controller@20000000 {\n>> + compatible = \"sprd,sc9860-ap-clk\";\n>> + reg = <0 0x20000000 0 0x400>;\n>> + clocks = <&ext_26m>, <&pll 0>,\n>> + <&pmu_gate 0>;\n>> + #clock-cells = <1>;\n>> + };\n>> --\n>> 2.7.4\n>>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1801963,"web_url":"http://patchwork.ozlabs.org/comment/1801963/","msgid":"","list_archive_url":null,"date":"2017-11-09T08:18:48","subject":"Re: [PATCH V3 09/11] clk: sprd: add clocks support for SC9860","submitter":{"id":64876,"url":"http://patchwork.ozlabs.org/api/people/64876/","name":"Chunyan Zhang","email":"zhang.lyra@gmail.com"},"content":"Hi Rob and Stephen,\n\nOn 7 November 2017 at 05:43, Rob Herring wrote:\n> On Thu, Nov 02, 2017 at 02:56:24PM +0800, Chunyan Zhang wrote:\n>> This patch added the list of clocks for Spreadtrum's SC9860 SoC,\n>> together with clock initialization code.\n>>\n>> Signed-off-by: Chunyan Zhang \n>> ---\n>> drivers/clk/sprd/Kconfig | 10 +\n>> drivers/clk/sprd/Makefile | 3 +\n>> drivers/clk/sprd/sc9860-clk.c | 1987 +++++++++++++++++++++++++++\n>> include/dt-bindings/clock/sprd,sc9860-clk.h | 408 ++++++\n>\n> This belongs in the binding doc patch.\n\nI noticed that this kind of files were submitted in driver patch\nbefore when adding a new driver, how about I just put it into a single\npatch in the next version?\n\nThanks,\nChunyan\n\n>\n> Rob","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1802958,"web_url":"http://patchwork.ozlabs.org/comment/1802958/","msgid":"","list_archive_url":null,"date":"2017-11-10T21:10:24","subject":"Re: [PATCH V3 09/11] clk: sprd: add clocks support for SC9860","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Nov 9, 2017 at 2:18 AM, Chunyan Zhang wrote:\n> Hi Rob and Stephen,\n>\n> On 7 November 2017 at 05:43, Rob Herring wrote:\n>> On Thu, Nov 02, 2017 at 02:56:24PM +0800, Chunyan Zhang wrote:\n>>> This patch added the list of clocks for Spreadtrum's SC9860 SoC,\n>>> together with clock initialization code.\n>>>\n>>> Signed-off-by: Chunyan Zhang \n>>> ---\n>>> drivers/clk/sprd/Kconfig | 10 +\n>>> drivers/clk/sprd/Makefile | 3 +\n>>> drivers/clk/sprd/sc9860-clk.c | 1987 +++++++++++++++++++++++++++\n>>> include/dt-bindings/clock/sprd,sc9860-clk.h | 408 ++++++\n>>\n>> This belongs in the binding doc patch.\n>\n> I noticed that this kind of files were submitted in driver patch\n> before when adding a new driver, how about I just put it into a single\n> patch in the next version?\n\nIt's been done all ways, but the correct way is as I told you. Binding\ndoc and header in one, driver in another patch.\n\nRob","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"YN68anIL\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=robh@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yYXlK4MmRz9t2Z\n\tfor ;\n\tSat, 11 Nov 2017 08:11:20 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1eDGZz-0002Ei-Ni; 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