[{"id":1794846,"web_url":"http://patchwork.ozlabs.org/comment/1794846/","msgid":"<20171027130504.l34y2u6l2e2rxlac@armageddon.cambridge.arm.com>","list_archive_url":null,"date":"2017-10-27T13:05:04","subject":"Re: [PATCH v4 25/28] arm64/sve: Detect SVE and activate runtime\n\tsupport","submitter":{"id":938,"url":"http://patchwork.ozlabs.org/api/people/938/","name":"Catalin Marinas","email":"catalin.marinas@arm.com"},"content":"On Fri, Oct 27, 2017 at 11:51:07AM +0100, Dave P Martin wrote:\n> This patch enables detection of hardware SVE support via the\n> cpufeatures framework, and reports its presence to the kernel and\n> userspace via the new ARM64_SVE cpucap and HWCAP_SVE hwcap\n> respectively.\n> \n> Userspace can also detect SVE using ID_AA64PFR0_EL1, using the\n> cpufeatures MRS emulation.\n> \n> When running on hardware that supports SVE, this enables runtime\n> kernel support for SVE, and allows user tasks to execute SVE\n> instructions and make of the of the SVE-specific user/kernel\n> interface extensions implemented by this series.\n> \n> Signed-off-by: Dave Martin \n> Reviewed-by: Suzuki K Poulose \n> Cc: Catalin Marinas \n\nReviewed-by: Catalin Marinas ","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"I11Yvorj\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yNkdh04Gmz9t2Q\n\tfor ;\n\tSat, 28 Oct 2017 00:05:59 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e84Kf-0002fz-2r; Fri, 27 Oct 2017 13:05:53 +0000","from foss.arm.com ([217.140.101.70])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e84KH-0001YI-DT for linux-arm-kernel@lists.infradead.org;\n\tFri, 27 Oct 2017 13:05:32 +0000","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 094561529;\n\tFri, 27 Oct 2017 06:05:09 -0700 (PDT)","from armageddon.cambridge.arm.com (armageddon.cambridge.arm.com\n\t[10.1.206.84])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t2C2503F246; Fri, 27 Oct 2017 06:05:07 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=OZNuHXgt2+u3KC99UH8hsbz/ITrp29n0u+j3gzWiXhw=;\n\tb=I11YvorjBnlPR5\n\t4QqA6JvmQYLOr90frcuCTrDSY6g+y0ndYNcfnb/QG8qDM8VKMfyvArgg1SkkNlvQ0Fe4POsj3F0h4\n\tTVFfrKg2/a0y/xDPc9k1v7Qlnijfs91Rbx7lJwXxq4zbAeCm9mnwKW6GPt5eD+e9/ZqFXBEh8IrYK\n\tHdzobBRAG6W1G/uhLEKQMAskMZufagwmn/iYLOYAPV/j8ITwN//4BDpwrfsWbH3fMOs5JImWp0nX6\n\toUom6tg/WbGNRbKz8G1Rm47XYAzgIpW5nnoIJqkEkTv6JdNL1Cu3erUtUfYXKbzJwrzkrgdTkTINX\n\totbqE5Rvznvem6lHqaIQ==;","Date":"Fri, 27 Oct 2017 14:05:04 +0100","From":"Catalin Marinas ","To":"Dave Martin ","Subject":"Re: [PATCH v4 25/28] arm64/sve: Detect SVE and activate runtime\n\tsupport","Message-ID":"<20171027130504.l34y2u6l2e2rxlac@armageddon.cambridge.arm.com>","References":"<1509101470-7881-1-git-send-email-Dave.Martin@arm.com>\n\t<1509101470-7881-26-git-send-email-Dave.Martin@arm.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1509101470-7881-26-git-send-email-Dave.Martin@arm.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171027_060529_496621_0C057E99 ","X-CRM114-Status":"UNSURE ( 9.21 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"linux-arch@vger.kernel.org, Okamoto Takayuki ,\n\tlibc-alpha@sourceware.org, Ard Biesheuvel , \n\tSzabolcs Nagy , Will Deacon ,\n\tAlex =?iso-8859-1?q?Benn=E9e?= ,\n\tkvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1796570,"web_url":"http://patchwork.ozlabs.org/comment/1796570/","msgid":"<874lqfinz7.fsf@linaro.org>","list_archive_url":null,"date":"2017-10-31T10:57:32","subject":"Re: [PATCH v4 02/28] arm64: KVM: Hide unsupported AArch64 CPU\n\tfeatures from guests","submitter":{"id":39532,"url":"http://patchwork.ozlabs.org/api/people/39532/","name":"Alex Bennée","email":"alex.bennee@linaro.org"},"content":"Dave Martin writes:\n\n> Currently, a guest kernel sees the true CPU feature registers\n> (ID_*_EL1) when it reads them using MRS instructions. This means\n> that the guest may observe features that are present in the\n> hardware but the host doesn't understand or doesn't provide support\n> for. A guest may legimitately try to use such a feature as per the\n> architecture, but use of the feature may trap instead of working\n> normally, triggering undef injection into the guest.\n>\n> This is not a problem for the host, but the guest may go wrong when\n> running on newer hardware than the host knows about.\n>\n> This patch hides from guest VMs any AArch64-specific CPU features\n> that the host doesn't support, by exposing to the guest the\n> sanitised versions of the registers computed by the cpufeatures\n> framework, instead of the true hardware registers. To achieve\n> this, HCR_EL2.TID3 is now set for AArch64 guests, and emulation\n> code is added to KVM to report the sanitised versions of the\n> affected registers in response to MRS and register reads from\n> userspace.\n>\n> The affected registers are removed from invariant_sys_regs[] (since\n> the invariant_sys_regs handling is no longer quite correct for\n> them) and added to sys_reg_desgs[], with appropriate access(),\n> get_user() and set_user() methods. No runtime vcpu storage is\n> allocated for the registers: instead, they are read on demand from\n> the cpufeatures framework. This may need modification in the\n> future if there is a need for userspace to customise the features\n> visible to the guest.\n>\n> Attempts by userspace to write the registers are handled similarly\n> to the current invariant_sys_regs handling: writes are permitted,\n> but only if they don't attempt to change the value. This is\n> sufficient to support VM snapshot/restore from userspace.\n>\n> Because of the additional registers, restoring a VM on an older\n> kernel may not work unless userspace knows how to handle the extra\n> VM registers exposed to the KVM user ABI by this patch.\n>\n> Under the principle of least damage, this patch makes no attempt to\n> handle any of the other registers currently in\n> invariant_sys_regs[], or to emulate registers for AArch32: however,\n> these could be handled in a similar way in future, as necessary.\n>\n> Signed-off-by: Dave Martin \n> Reviewed-by: Marc Zyngier \n> Acked-by: Catalin Marinas \n> Cc: Christoffer Dall \n\nReviewed-by: Alex Bennée \n\n> ---\n> arch/arm64/include/asm/sysreg.h | 3 +\n> arch/arm64/kvm/hyp/switch.c | 6 +\n> arch/arm64/kvm/sys_regs.c | 282 +++++++++++++++++++++++++++++++++-------\n> 3 files changed, 246 insertions(+), 45 deletions(-)\n>\n> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h\n> index 4dceb12..609d59af 100644\n> --- a/arch/arm64/include/asm/sysreg.h\n> +++ b/arch/arm64/include/asm/sysreg.h\n> @@ -149,6 +149,9 @@\n> #define SYS_ID_AA64DFR0_EL1\t\tsys_reg(3, 0, 0, 5, 0)\n> #define SYS_ID_AA64DFR1_EL1\t\tsys_reg(3, 0, 0, 5, 1)\n>\n> +#define SYS_ID_AA64AFR0_EL1\t\tsys_reg(3, 0, 0, 5, 4)\n> +#define SYS_ID_AA64AFR1_EL1\t\tsys_reg(3, 0, 0, 5, 5)\n> +\n> #define SYS_ID_AA64ISAR0_EL1\t\tsys_reg(3, 0, 0, 6, 0)\n> #define SYS_ID_AA64ISAR1_EL1\t\tsys_reg(3, 0, 0, 6, 1)\n>\n> diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c\n> index 945e79c..35a90b8 100644\n> --- a/arch/arm64/kvm/hyp/switch.c\n> +++ b/arch/arm64/kvm/hyp/switch.c\n> @@ -81,11 +81,17 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu)\n> \t * it will cause an exception.\n> \t */\n> \tval = vcpu->arch.hcr_el2;\n> +\n> \tif (!(val & HCR_RW) && system_supports_fpsimd()) {\n> \t\twrite_sysreg(1 << 30, fpexc32_el2);\n> \t\tisb();\n> \t}\n> +\n> +\tif (val & HCR_RW) /* for AArch64 only: */\n> +\t\tval |= HCR_TID3; /* TID3: trap feature register accesses */\n> +\n> \twrite_sysreg(val, hcr_el2);\n> +\n> \t/* Trap on AArch32 cp15 c15 accesses (EL1 or EL0) */\n> \twrite_sysreg(1 << 15, hstr_el2);\n> \t/*\n> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c\n> index 2e070d3..b1f7552 100644\n> --- a/arch/arm64/kvm/sys_regs.c\n> +++ b/arch/arm64/kvm/sys_regs.c\n> @@ -892,6 +892,137 @@ static bool access_cntp_cval(struct kvm_vcpu *vcpu,\n> \treturn true;\n> }\n>\n> +/* Read a sanitised cpufeature ID register by sys_reg_desc */\n> +static u64 read_id_reg(struct sys_reg_desc const *r, bool raz)\n> +{\n> +\tu32 id = sys_reg((u32)r->Op0, (u32)r->Op1,\n> +\t\t\t (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);\n> +\n> +\treturn raz ? 0 : read_sanitised_ftr_reg(id);\n> +}\n> +\n> +/* cpufeature ID register access trap handlers */\n> +\n> +static bool __access_id_reg(struct kvm_vcpu *vcpu,\n> +\t\t\t struct sys_reg_params *p,\n> +\t\t\t const struct sys_reg_desc *r,\n> +\t\t\t bool raz)\n> +{\n> +\tif (p->is_write)\n> +\t\treturn write_to_read_only(vcpu, p, r);\n> +\n> +\tp->regval = read_id_reg(r, raz);\n> +\treturn true;\n> +}\n> +\n> +static bool access_id_reg(struct kvm_vcpu *vcpu,\n> +\t\t\t struct sys_reg_params *p,\n> +\t\t\t const struct sys_reg_desc *r)\n> +{\n> +\treturn __access_id_reg(vcpu, p, r, false);\n> +}\n> +\n> +static bool access_raz_id_reg(struct kvm_vcpu *vcpu,\n> +\t\t\t struct sys_reg_params *p,\n> +\t\t\t const struct sys_reg_desc *r)\n> +{\n> +\treturn __access_id_reg(vcpu, p, r, true);\n> +}\n> +\n> +static int reg_from_user(u64 *val, const void __user *uaddr, u64 id);\n> +static int reg_to_user(void __user *uaddr, const u64 *val, u64 id);\n> +static u64 sys_reg_to_index(const struct sys_reg_desc *reg);\n> +\n> +/*\n> + * cpufeature ID register user accessors\n> + *\n> + * For now, these registers are immutable for userspace, so no values\n> + * are stored, and for set_id_reg() we don't allow the effective value\n> + * to be changed.\n> + */\n> +static int __get_id_reg(const struct sys_reg_desc *rd, void __user *uaddr,\n> +\t\t\tbool raz)\n> +{\n> +\tconst u64 id = sys_reg_to_index(rd);\n> +\tconst u64 val = read_id_reg(rd, raz);\n> +\n> +\treturn reg_to_user(uaddr, &val, id);\n> +}\n> +\n> +static int __set_id_reg(const struct sys_reg_desc *rd, void __user *uaddr,\n> +\t\t\tbool raz)\n> +{\n> +\tconst u64 id = sys_reg_to_index(rd);\n> +\tint err;\n> +\tu64 val;\n> +\n> +\terr = reg_from_user(&val, uaddr, id);\n> +\tif (err)\n> +\t\treturn err;\n> +\n> +\t/* This is what we mean by invariant: you can't change it. */\n> +\tif (val != read_id_reg(rd, raz))\n> +\t\treturn -EINVAL;\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,\n> +\t\t const struct kvm_one_reg *reg, void __user *uaddr)\n> +{\n> +\treturn __get_id_reg(rd, uaddr, false);\n> +}\n> +\n> +static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,\n> +\t\t const struct kvm_one_reg *reg, void __user *uaddr)\n> +{\n> +\treturn __set_id_reg(rd, uaddr, false);\n> +}\n> +\n> +static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,\n> +\t\t\t const struct kvm_one_reg *reg, void __user *uaddr)\n> +{\n> +\treturn __get_id_reg(rd, uaddr, true);\n> +}\n> +\n> +static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,\n> +\t\t\t const struct kvm_one_reg *reg, void __user *uaddr)\n> +{\n> +\treturn __set_id_reg(rd, uaddr, true);\n> +}\n> +\n> +/* sys_reg_desc initialiser for known cpufeature ID registers */\n> +#define ID_SANITISED(name) {\t\t\t\\\n> +\tSYS_DESC(SYS_##name),\t\t\t\\\n> +\t.access\t= access_id_reg,\t\t\\\n> +\t.get_user = get_id_reg,\t\t\t\\\n> +\t.set_user = set_id_reg,\t\t\t\\\n> +}\n> +\n> +/*\n> + * sys_reg_desc initialiser for architecturally unallocated cpufeature ID\n> + * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2\n> + * (1 <= crm < 8, 0 <= Op2 < 8).\n> + */\n> +#define ID_UNALLOCATED(crm, op2) {\t\t\t\\\n> +\tOp0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),\t\\\n> +\t.access = access_raz_id_reg,\t\t\t\\\n> +\t.get_user = get_raz_id_reg,\t\t\t\\\n> +\t.set_user = set_raz_id_reg,\t\t\t\\\n> +}\n> +\n> +/*\n> + * sys_reg_desc initialiser for known ID registers that we hide from guests.\n> + * For now, these are exposed just like unallocated ID regs: they appear\n> + * RAZ for the guest.\n> + */\n> +#define ID_HIDDEN(name) {\t\t\t\\\n> +\tSYS_DESC(SYS_##name),\t\t\t\\\n> +\t.access = access_raz_id_reg,\t\t\\\n> +\t.get_user = get_raz_id_reg,\t\t\\\n> +\t.set_user = set_raz_id_reg,\t\t\\\n> +}\n> +\n> /*\n> * Architected system registers.\n> * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2\n> @@ -944,6 +1075,84 @@ static const struct sys_reg_desc sys_reg_descs[] = {\n> \t{ SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },\n>\n> \t{ SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },\n> +\n> +\t/*\n> +\t * ID regs: all ID_SANITISED() entries here must have corresponding\n> +\t * entries in arm64_ftr_regs[].\n> +\t */\n> +\n> +\t/* AArch64 mappings of the AArch32 ID registers */\n> +\t/* CRm=1 */\n> +\tID_SANITISED(ID_PFR0_EL1),\n> +\tID_SANITISED(ID_PFR1_EL1),\n> +\tID_SANITISED(ID_DFR0_EL1),\n> +\tID_HIDDEN(ID_AFR0_EL1),\n> +\tID_SANITISED(ID_MMFR0_EL1),\n> +\tID_SANITISED(ID_MMFR1_EL1),\n> +\tID_SANITISED(ID_MMFR2_EL1),\n> +\tID_SANITISED(ID_MMFR3_EL1),\n> +\n> +\t/* CRm=2 */\n> +\tID_SANITISED(ID_ISAR0_EL1),\n> +\tID_SANITISED(ID_ISAR1_EL1),\n> +\tID_SANITISED(ID_ISAR2_EL1),\n> +\tID_SANITISED(ID_ISAR3_EL1),\n> +\tID_SANITISED(ID_ISAR4_EL1),\n> +\tID_SANITISED(ID_ISAR5_EL1),\n> +\tID_SANITISED(ID_MMFR4_EL1),\n> +\tID_UNALLOCATED(2,7),\n> +\n> +\t/* CRm=3 */\n> +\tID_SANITISED(MVFR0_EL1),\n> +\tID_SANITISED(MVFR1_EL1),\n> +\tID_SANITISED(MVFR2_EL1),\n> +\tID_UNALLOCATED(3,3),\n> +\tID_UNALLOCATED(3,4),\n> +\tID_UNALLOCATED(3,5),\n> +\tID_UNALLOCATED(3,6),\n> +\tID_UNALLOCATED(3,7),\n> +\n> +\t/* AArch64 ID registers */\n> +\t/* CRm=4 */\n> +\tID_SANITISED(ID_AA64PFR0_EL1),\n> +\tID_SANITISED(ID_AA64PFR1_EL1),\n> +\tID_UNALLOCATED(4,2),\n> +\tID_UNALLOCATED(4,3),\n> +\tID_UNALLOCATED(4,4),\n> +\tID_UNALLOCATED(4,5),\n> +\tID_UNALLOCATED(4,6),\n> +\tID_UNALLOCATED(4,7),\n> +\n> +\t/* CRm=5 */\n> +\tID_SANITISED(ID_AA64DFR0_EL1),\n> +\tID_SANITISED(ID_AA64DFR1_EL1),\n> +\tID_UNALLOCATED(5,2),\n> +\tID_UNALLOCATED(5,3),\n> +\tID_HIDDEN(ID_AA64AFR0_EL1),\n> +\tID_HIDDEN(ID_AA64AFR1_EL1),\n> +\tID_UNALLOCATED(5,6),\n> +\tID_UNALLOCATED(5,7),\n> +\n> +\t/* CRm=6 */\n> +\tID_SANITISED(ID_AA64ISAR0_EL1),\n> +\tID_SANITISED(ID_AA64ISAR1_EL1),\n> +\tID_UNALLOCATED(6,2),\n> +\tID_UNALLOCATED(6,3),\n> +\tID_UNALLOCATED(6,4),\n> +\tID_UNALLOCATED(6,5),\n> +\tID_UNALLOCATED(6,6),\n> +\tID_UNALLOCATED(6,7),\n> +\n> +\t/* CRm=7 */\n> +\tID_SANITISED(ID_AA64MMFR0_EL1),\n> +\tID_SANITISED(ID_AA64MMFR1_EL1),\n> +\tID_SANITISED(ID_AA64MMFR2_EL1),\n> +\tID_UNALLOCATED(7,3),\n> +\tID_UNALLOCATED(7,4),\n> +\tID_UNALLOCATED(7,5),\n> +\tID_UNALLOCATED(7,6),\n> +\tID_UNALLOCATED(7,7),\n> +\n> \t{ SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },\n> \t{ SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },\n> \t{ SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },\n> @@ -1790,8 +1999,8 @@ static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,\n> \tif (!r)\n> \t\tr = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));\n>\n> -\t/* Not saved in the sys_reg array? */\n> -\tif (r && !r->reg)\n> +\t/* Not saved in the sys_reg array and not otherwise accessible? */\n> +\tif (r && !(r->reg || r->get_user))\n> \t\tr = NULL;\n>\n> \treturn r;\n> @@ -1815,20 +2024,6 @@ static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,\n> FUNCTION_INVARIANT(midr_el1)\n> FUNCTION_INVARIANT(ctr_el0)\n> FUNCTION_INVARIANT(revidr_el1)\n> -FUNCTION_INVARIANT(id_pfr0_el1)\n> -FUNCTION_INVARIANT(id_pfr1_el1)\n> -FUNCTION_INVARIANT(id_dfr0_el1)\n> -FUNCTION_INVARIANT(id_afr0_el1)\n> -FUNCTION_INVARIANT(id_mmfr0_el1)\n> -FUNCTION_INVARIANT(id_mmfr1_el1)\n> -FUNCTION_INVARIANT(id_mmfr2_el1)\n> -FUNCTION_INVARIANT(id_mmfr3_el1)\n> -FUNCTION_INVARIANT(id_isar0_el1)\n> -FUNCTION_INVARIANT(id_isar1_el1)\n> -FUNCTION_INVARIANT(id_isar2_el1)\n> -FUNCTION_INVARIANT(id_isar3_el1)\n> -FUNCTION_INVARIANT(id_isar4_el1)\n> -FUNCTION_INVARIANT(id_isar5_el1)\n> FUNCTION_INVARIANT(clidr_el1)\n> FUNCTION_INVARIANT(aidr_el1)\n>\n> @@ -1836,20 +2031,6 @@ FUNCTION_INVARIANT(aidr_el1)\n> static struct sys_reg_desc invariant_sys_regs[] = {\n> \t{ SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },\n> \t{ SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },\n> -\t{ SYS_DESC(SYS_ID_PFR0_EL1), NULL, get_id_pfr0_el1 },\n> -\t{ SYS_DESC(SYS_ID_PFR1_EL1), NULL, get_id_pfr1_el1 },\n> -\t{ SYS_DESC(SYS_ID_DFR0_EL1), NULL, get_id_dfr0_el1 },\n> -\t{ SYS_DESC(SYS_ID_AFR0_EL1), NULL, get_id_afr0_el1 },\n> -\t{ SYS_DESC(SYS_ID_MMFR0_EL1), NULL, get_id_mmfr0_el1 },\n> -\t{ SYS_DESC(SYS_ID_MMFR1_EL1), NULL, get_id_mmfr1_el1 },\n> -\t{ SYS_DESC(SYS_ID_MMFR2_EL1), NULL, get_id_mmfr2_el1 },\n> -\t{ SYS_DESC(SYS_ID_MMFR3_EL1), NULL, get_id_mmfr3_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR0_EL1), NULL, get_id_isar0_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR1_EL1), NULL, get_id_isar1_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR2_EL1), NULL, get_id_isar2_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR3_EL1), NULL, get_id_isar3_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR4_EL1), NULL, get_id_isar4_el1 },\n> -\t{ SYS_DESC(SYS_ID_ISAR5_EL1), NULL, get_id_isar5_el1 },\n> \t{ SYS_DESC(SYS_CLIDR_EL1), NULL, get_clidr_el1 },\n> \t{ SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },\n> \t{ SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },\n> @@ -2079,12 +2260,31 @@ static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)\n> \treturn true;\n> }\n>\n> +static int walk_one_sys_reg(const struct sys_reg_desc *rd,\n> +\t\t\t u64 __user **uind,\n> +\t\t\t unsigned int *total)\n> +{\n> +\t/*\n> +\t * Ignore registers we trap but don't save,\n> +\t * and for which no custom user accessor is provided.\n> +\t */\n> +\tif (!(rd->reg || rd->get_user))\n> +\t\treturn 0;\n> +\n> +\tif (!copy_reg_to_user(rd, uind))\n> +\t\treturn -EFAULT;\n> +\n> +\t(*total)++;\n> +\treturn 0;\n> +}\n> +\n> /* Assumed ordered tables, see kvm_sys_reg_table_init. */\n> static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)\n> {\n> \tconst struct sys_reg_desc *i1, *i2, *end1, *end2;\n> \tunsigned int total = 0;\n> \tsize_t num;\n> +\tint err;\n>\n> \t/* We check for duplicates here, to allow arch-specific overrides. */\n> \ti1 = get_target_table(vcpu->arch.target, true, &num);\n> @@ -2098,21 +2298,13 @@ static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)\n> \twhile (i1 || i2) {\n> \t\tint cmp = cmp_sys_reg(i1, i2);\n> \t\t/* target-specific overrides generic entry. */\n> -\t\tif (cmp <= 0) {\n> -\t\t\t/* Ignore registers we trap but don't save. */\n> -\t\t\tif (i1->reg) {\n> -\t\t\t\tif (!copy_reg_to_user(i1, &uind))\n> -\t\t\t\t\treturn -EFAULT;\n> -\t\t\t\ttotal++;\n> -\t\t\t}\n> -\t\t} else {\n> -\t\t\t/* Ignore registers we trap but don't save. */\n> -\t\t\tif (i2->reg) {\n> -\t\t\t\tif (!copy_reg_to_user(i2, &uind))\n> -\t\t\t\t\treturn -EFAULT;\n> -\t\t\t\ttotal++;\n> -\t\t\t}\n> -\t\t}\n> +\t\tif (cmp <= 0)\n> +\t\t\terr = walk_one_sys_reg(i1, &uind, &total);\n> +\t\telse\n> +\t\t\terr = walk_one_sys_reg(i2, &uind, &total);\n> +\n> +\t\tif (err)\n> +\t\t\treturn err;\n>\n> \t\tif (cmp <= 0 && ++i1 == end1)\n> \t\t\ti1 = NULL;\n\n\n--\nAlex Bennée","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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