[{"id":1795230,"web_url":"http://patchwork.ozlabs.org/comment/1795230/","msgid":"<1872710.P2f02irZl9@aspire.rjw.lan>","list_archive_url":null,"date":"2017-10-28T09:07:30","subject":"Re: [RFC PATCH v10 0/7] PCI: rockchip: Move PCIe WAKE# handling\n\tinto pci core","submitter":{"id":26536,"url":"http://patchwork.ozlabs.org/api/people/26536/","name":"Rafael J. Wysocki","email":"rjw@rjwysocki.net"},"content":"On Friday, October 27, 2017 9:26:05 AM CEST Jeffy Chen wrote:\n> \n> Currently we are handling wake irq in mrvl wifi driver. Move it into\n> pci core.\n> \n> Tested on my chromebook bob(with cros 4.4 kernel and mrvl wifi).\n> \n> \n> Changes in v10:\n> Use device_set_wakeup_capable() instead of device_set_wakeup_enable(),\n> since dedicated wakeirq will be lost in device_set_wakeup_enable(false).\n> \n> Changes in v9:\n> Add section for PCI devices and rewrite the commit message.\n> Rewrite the commit message.\n> Fix check error in .cleanup().\n> Move dedicated wakeirq setup to setup() callback and use\n> device_set_wakeup_enable() to enable/disable.\n> \n> Changes in v8:\n> Add optional \"pci\", and rewrite commit message.\n> Rewrite the commit message.\n> Add pci-of.c and use platform_pm_ops to handle the PCIe WAKE# signal.\n> \n> Changes in v7:\n> Move PCIE_WAKE handling into pci core.\n> \n> Changes in v6:\n> Fix device_init_wake error handling, and add some comments.\n> \n> Changes in v5:\n> Move to pci.txt\n> Use \"wakeup\" instead of \"wake\"\n> Rebase.\n> \n> Changes in v3:\n> Fix error handling.\n> \n> Changes in v2:\n> Use dev_pm_set_dedicated_wake_irq.\n> \n> Jeffy Chen (7):\n>   dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq\n>   of/irq: Adjust of_pci_irq parsing for multiple interrupts\n>   mwifiex: Disable wakeup irq handling for pcie\n>   arm64: dts: rockchip: Move PCIe WAKE# irq to pcie driver for Gru\n>   PCI: Make pci_platform_pm_ops's callbacks optional\n>   PCI / PM: Move acpi wakeup code to pci core\n>   PCI / PM: Add support for the PCIe WAKE# signal for OF\n\nOverall, I don't quite like the direction this is going into, but I need to\nhave a deeper look.  Which may take some time, so please bear with me.\n\nThanks,\nRafael","headers":{"Return-Path":"<netdev-owner@vger.kernel.org>","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yPFJ76xMVz9t2x\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 28 Oct 2017 20:07:35 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751731AbdJ1JH2 (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tSat, 28 Oct 2017 05:07:28 -0400","from cloudserver094114.home.net.pl ([79.96.170.134]:63202 \"EHLO\n\tcloudserver094114.home.net.pl\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1751000AbdJ1JHZ (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Sat, 28 Oct 2017 05:07:25 -0400","from cheops.hbnet.cz (62.168.35.125) (HELO aspire.rjw.lan)\n\tby serwer1319399.home.pl (79.96.170.134) with SMTP (IdeaSmtpServer\n\t0.82) id e64a108ae5b6f28a; Sat, 28 Oct 2017 11:07:22 +0200"],"From":"\"Rafael J. Wysocki\" <rjw@rjwysocki.net>","To":"Jeffy Chen <jeffy.chen@rock-chips.com>","Cc":"linux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tlinux-pm@vger.kernel.org, tony@atomide.com,\n\tshawn.lin@rock-chips.com, briannorris@chromium.org,\n\tdianders@chromium.org, Xinming Hu <huxm@marvell.com>,\n\tlinux-pci@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,\n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tKalle Valo <kvalo@codeaurora.org>,\n\tHeiko Stuebner <heiko@sntech.de>, linux-acpi@vger.kernel.org,\n\tlinux-rockchip@lists.infradead.org,\n\tNishant Sarmukadam <nishants@marvell.com>,\n\tWill Deacon <will.deacon@arm.com>, Matthias Kaehlcke <mka@chromium.org>,\n\tdevicetree@vger.kernel.org, Ganapathi Bhat <gbhat@marvell.com>,\n\tFrank Rowand <frowand.list@gmail.com>, Len Brown <lenb@kernel.org>,\n\tAmitkumar Karwar <amitkarwar@gmail.com>,\n\tlinux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org,\n\tlinux-wireless@vger.kernel.org, Caesar Wang <wxt@rock-chips.com>,\n\tKlaus Goger <klaus.goger@theobroma-systems.com>,\n\tMark Rutland <mark.rutland@arm.com>","Subject":"Re: [RFC PATCH v10 0/7] PCI: rockchip: Move PCIe WAKE# handling\n\tinto pci core","Date":"Sat, 28 Oct 2017 11:07:30 +0200","Message-ID":"<1872710.P2f02irZl9@aspire.rjw.lan>","In-Reply-To":"<20171027072612.26565-1-jeffy.chen@rock-chips.com>","References":"<20171027072612.26565-1-jeffy.chen@rock-chips.com>","MIME-Version":"1.0","Content-Transfer-Encoding":"7Bit","Content-Type":"text/plain; charset=\"us-ascii\"","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<netdev.vger.kernel.org>","X-Mailing-List":"netdev@vger.kernel.org"}},{"id":1795589,"web_url":"http://patchwork.ozlabs.org/comment/1795589/","msgid":"<59F68B40.8050506@rock-chips.com>","list_archive_url":null,"date":"2017-10-30T02:15:28","subject":"Re: [RFC PATCH v10 0/7] PCI: rockchip: Move PCIe WAKE# handling into\n\tpci core","submitter":{"id":67754,"url":"http://patchwork.ozlabs.org/api/people/67754/","name":"Jeffy Chen","email":"jeffy.chen@rock-chips.com"},"content":"Hi Rafael,\n\nthanks for your reply.\n\nOn 10/28/2017 05:07 PM, Rafael J. Wysocki wrote:\n> Overall, I don't quite like the direction this is going into, but I need to\n> have a deeper look.  Which may take some time, so please bear with me.\n>\nok, i'll wait for your comments, thanks :)\n\n> Thanks,\n> Rafael","headers":{"Return-Path":"<netdev-owner@vger.kernel.org>","X-Original-To":"patchwork-incoming@ozlabs.org","Delivered-To":"patchwork-incoming@ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=netdev-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yQJ4M0x81z9t3v\n\tfor <patchwork-incoming@ozlabs.org>;\n\tMon, 30 Oct 2017 13:16:03 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752078AbdJ3CP7 (ORCPT <rfc822;patchwork-incoming@ozlabs.org>);\n\tSun, 29 Oct 2017 22:15:59 -0400","from regular1.263xmail.com ([211.150.99.136]:50339 \"EHLO\n\tregular1.263xmail.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751478AbdJ3CP4 (ORCPT\n\t<rfc822;netdev@vger.kernel.org>); Sun, 29 Oct 2017 22:15:56 -0400","from jeffy.chen?rock-chips.com (unknown [192.168.167.174])\n\tby regular1.263xmail.com (Postfix) with ESMTP id ED5F6E8;\n\tMon, 30 Oct 2017 10:15:52 +0800 (CST)","from [172.16.22.86] (localhost [127.0.0.1])\n\tby smtp.263.net (Postfix) with ESMTPA id 3C6893DB;\n\tMon, 30 Oct 2017 10:15:30 +0800 (CST)","from [172.16.22.86] (unknown [103.29.142.67])\n\tby smtp.263.net (Postfix) whith ESMTP id 9303ED87K9;\n\tMon, 30 Oct 2017 10:15:46 +0800 (CST)"],"X-263anti-spam":"KSV:0;","X-MAIL-GRAY":"0","X-MAIL-DELIVERY":"1","X-KSVirus-check":"0","X-ABS-CHECKED":"4","X-RL-SENDER":"jeffy.chen@rock-chips.com","X-FST-TO":"rjw@rjwysocki.net","X-SENDER-IP":"103.29.142.67","X-LOGIN-NAME":"jeffy.chen@rock-chips.com","X-UNIQUE-TAG":"<1ed3aa002205860a65eabeefa0be8c27>","X-ATTACHMENT-NUM":"0","X-SENDER":"cjf@rock-chips.com","X-DNS-TYPE":"0","Message-ID":"<59F68B40.8050506@rock-chips.com>","Date":"Mon, 30 Oct 2017 10:15:28 +0800","From":"jeffy <jeffy.chen@rock-chips.com>","User-Agent":"Mozilla/5.0 (X11; Linux x86_64;\n\trv:19.0) Gecko/20130126 Thunderbird/19.0","MIME-Version":"1.0","To":"\"Rafael J. Wysocki\" <rjw@rjwysocki.net>","CC":"linux-kernel@vger.kernel.org, bhelgaas@google.com,\n\tlinux-pm@vger.kernel.org, tony@atomide.com,\n\tshawn.lin@rock-chips.com, briannorris@chromium.org,\n\tdianders@chromium.org, Xinming Hu <huxm@marvell.com>,\n\tlinux-pci@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,\n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tKalle Valo <kvalo@codeaurora.org>,\n\tHeiko Stuebner <heiko@sntech.de>, linux-acpi@vger.kernel.org,\n\tlinux-rockchip@lists.infradead.org,\n\tNishant Sarmukadam <nishants@marvell.com>,\n\tWill Deacon <will.deacon@arm.com>, Matthias Kaehlcke <mka@chromium.org>,\n\tdevicetree@vger.kernel.org, Ganapathi Bhat <gbhat@marvell.com>,\n\tFrank Rowand <frowand.list@gmail.com>, Len Brown <lenb@kernel.org>,\n\tAmitkumar Karwar <amitkarwar@gmail.com>,\n\tlinux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org,\n\tlinux-wireless@vger.kernel.org, Caesar Wang <wxt@rock-chips.com>,\n\tKlaus Goger <klaus.goger@theobroma-systems.com>,\n\tMark Rutland <mark.rutland@arm.com>","Subject":"Re: [RFC PATCH v10 0/7] PCI: rockchip: Move PCIe WAKE# handling into\n\tpci core","References":"<20171027072612.26565-1-jeffy.chen@rock-chips.com>\n\t<1872710.P2f02irZl9@aspire.rjw.lan>","In-Reply-To":"<1872710.P2f02irZl9@aspire.rjw.lan>","Content-Type":"text/plain; charset=UTF-8; format=flowed","Content-Transfer-Encoding":"7bit","Sender":"netdev-owner@vger.kernel.org","Precedence":"bulk","List-ID":"<netdev.vger.kernel.org>","X-Mailing-List":"netdev@vger.kernel.org"}}]