[{"id":1777104,"web_url":"http://patchwork.ozlabs.org/comment/1777104/","msgid":"<20170928152646.jteewxaqqbkw777s@flea>","list_archive_url":null,"date":"2017-09-28T15:26:46","subject":"Re: [PATCH v4 00/11] dmaengine: sun6i: Fixes for H3/A83T, enable A64","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 28, 2017 at 01:49:17AM +0000, Stefan Brüns wrote:\n> Commit 3a03ea763a67 (\"dmaengine: sun6i: Add support for Allwinner A83T\n> (sun8i) variant\") and commit f008db8c00c1 (\"dmaengine: sun6i: Add support for\n> Allwinner H3 (sun8i) variant\") added support for the A83T resp. H3, but missed\n> some differences between the original A31 and A83T/H3.\n> \n> The first patch adds a callback to the controller config to set the clock\n> autogating register of different SoC generations, i.e. A31, A23+A83T, H3+later,\n> and uses it to for the correct clock autogating setting.\n> \n> The second patch adds a callback for the burst length setting in the channel\n> config register, which has different field offsets and new burst widths/lengths,\n> which differs between H3 and earlier generations\n> \n> The third patch restructures some code required for the fourth patch and adds the\n> burst lengths to the controller config.\n> \n> The fourth patch adds the burst widths to the config and adds the handling of the\n> H3 specific burst widths.\n> \n> Patch 5 restructures the code to decouple some controller details (e.g. channel\n> count) from the compatible string/the config.\n> \n> Patches 6, 7 and 8 introduce and use the \"dma-chans\" property for the A64. Although\n> register compatible to the H3, the channel count differs and thus it requires a\n> new compatible. To avoid introduction of new compatibles for each minor variation,\n> anything but the register model is moved to devicetree properties. There\n> is at least one SoC (R40) which can then reuse the A64 compatible, the same\n> would have worked for A83T+V3s.\n> \n> Patches 9 and 10 add the DMA controller node to the devicetree and add the DMA\n> controller reference to the SPI nodes.\n> \n> Patch 11 fixes a small error in the devicetree binding example.\n\nApplied patches 9-11, thanks!\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2z870tL2z9tX5\n\tfor ;\n\tFri, 29 Sep 2017 01:27:19 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753408AbdI1P1A (ORCPT\n\t);\n\tThu, 28 Sep 2017 11:27:00 -0400","from mail.free-electrons.com ([62.4.15.54]:49771 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753367AbdI1P06 (ORCPT\n\t); Thu, 28 Sep 2017 11:26:58 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid BA81D20933; Thu, 28 Sep 2017 17:26:55 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 9453120920;\n\tThu, 28 Sep 2017 17:26:45 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 28 Sep 2017 17:26:46 +0200","From":"Maxime Ripard ","To":"Stefan =?iso-8859-1?q?Br=FCns?= ","Cc":"linux-sunxi@googlegroups.com, devicetree@vger.kernel.org,\n\tChen-Yu Tsai , Andre Przywara ,\n\tlinux-kernel@vger.kernel.org, Dan Williams ,\n\tVinod Koul ,\n\tRob Herring , dmaengine@vger.kernel.org,\n\tCode Kipper ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tCatalin Marinas ,\n\tWill Deacon , Mark Rutland ","Subject":"Re: [PATCH v4 00/11] dmaengine: sun6i: Fixes for H3/A83T, enable A64","Message-ID":"<20170928152646.jteewxaqqbkw777s@flea>","References":"<3c78e966-2ece-4e67-94de-801aa569089f@rwthex-w2-a.rwth-ad.de>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"zmuabj2gnergbqcl\"","Content-Disposition":"inline","In-Reply-To":"<3c78e966-2ece-4e67-94de-801aa569089f@rwthex-w2-a.rwth-ad.de>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1786785,"web_url":"http://patchwork.ozlabs.org/comment/1786785/","msgid":"","list_archive_url":null,"date":"2017-10-14T03:21:51","subject":"Re: [linux-sunxi] Re: [PATCH v4 00/11] dmaengine: sun6i: Fixes for\n\tH3/A83T, enable A64","submitter":{"id":47154,"url":"http://patchwork.ozlabs.org/api/people/47154/","name":"Chen-Yu Tsai","email":"wens@csie.org"},"content":"Hi Vinod,\n\nOn Thu, Sep 28, 2017 at 11:26 PM, Maxime Ripard\n wrote:\n> On Thu, Sep 28, 2017 at 01:49:17AM +0000, Stefan Brüns wrote:\n>> Commit 3a03ea763a67 (\"dmaengine: sun6i: Add support for Allwinner A83T\n>> (sun8i) variant\") and commit f008db8c00c1 (\"dmaengine: sun6i: Add support for\n>> Allwinner H3 (sun8i) variant\") added support for the A83T resp. H3, but missed\n>> some differences between the original A31 and A83T/H3.\n>>\n>> The first patch adds a callback to the controller config to set the clock\n>> autogating register of different SoC generations, i.e. A31, A23+A83T, H3+later,\n>> and uses it to for the correct clock autogating setting.\n>>\n>> The second patch adds a callback for the burst length setting in the channel\n>> config register, which has different field offsets and new burst widths/lengths,\n>> which differs between H3 and earlier generations\n>>\n>> The third patch restructures some code required for the fourth patch and adds the\n>> burst lengths to the controller config.\n>>\n>> The fourth patch adds the burst widths to the config and adds the handling of the\n>> H3 specific burst widths.\n>>\n>> Patch 5 restructures the code to decouple some controller details (e.g. channel\n>> count) from the compatible string/the config.\n>>\n>> Patches 6, 7 and 8 introduce and use the \"dma-chans\" property for the A64. Although\n>> register compatible to the H3, the channel count differs and thus it requires a\n>> new compatible. To avoid introduction of new compatibles for each minor variation,\n>> anything but the register model is moved to devicetree properties. There\n>> is at least one SoC (R40) which can then reuse the A64 compatible, the same\n>> would have worked for A83T+V3s.\n>>\n>> Patches 9 and 10 add the DMA controller node to the devicetree and add the DMA\n>> controller reference to the SPI nodes.\n>>\n>> Patch 11 fixes a small error in the devicetree binding example.\n>\n> Applied patches 9-11, thanks!\n> Maxime\n\nCan you pick up patches 1-8?\n\nThanks!\nChenYu\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yDVJb3gnzz9sRV\n\tfor ;\n\tSat, 14 Oct 2017 14:22:39 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753393AbdJNDWZ convert rfc822-to-8bit (ORCPT\n\t);\n\tFri, 13 Oct 2017 23:22:25 -0400","from smtp.csie.ntu.edu.tw ([140.112.30.61]:58668 \"EHLO\n\tsmtp.csie.ntu.edu.tw\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751172AbdJNDWY (ORCPT\n\t); Fri, 13 Oct 2017 23:22:24 -0400","from mail-wr0-f172.google.com (mail-wr0-f172.google.com\n\t[209.85.128.172])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits))\n\t(No client certificate requested) (Authenticated sender: b93043)\n\tby smtp.csie.ntu.edu.tw (Postfix) with ESMTPSA id B9BDD27AFD;\n\tSat, 14 Oct 2017 11:22:14 +0800 (CST)","by mail-wr0-f172.google.com with SMTP id q42so2170866wrb.7;\n\tFri, 13 Oct 2017 20:22:14 -0700 (PDT)","by 10.223.138.138 with HTTP; Fri, 13 Oct 2017 20:21:51 -0700 (PDT)"],"X-Gm-Message-State":"AMCzsaWSMJg2DtmdBVMuMgKN0uyu9SqLtnckClG9s2nLVXuzZSJgjplk\n\tLjb9Y+W2jOyPkLFfCq++LBQ8sIl1N0dufQ199dM=","X-Google-Smtp-Source":"ABhQp+QN4PQZ2kal7DaXW6kagCFyRasLuMshicnyBSCuGSFUZTL62XOHCKPkA60JdrX1O9ra3pNvxA7+YALoHDmtA2Q=","X-Received":"by 10.223.171.241 with SMTP id\n\ts104mr3049184wrc.256.1507951331820; \n\tFri, 13 Oct 2017 20:22:11 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170928152646.jteewxaqqbkw777s@flea>","References":"<3c78e966-2ece-4e67-94de-801aa569089f@rwthex-w2-a.rwth-ad.de>\n\t<20170928152646.jteewxaqqbkw777s@flea>","From":"Chen-Yu Tsai ","Date":"Sat, 14 Oct 2017 11:21:51 +0800","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [linux-sunxi] Re: [PATCH v4 00/11] dmaengine: sun6i: Fixes for\n\tH3/A83T, enable A64","To":"Vinod Koul ","Cc":"=?utf-8?q?Stefan_Br=C3=BCns?= , linux-sunxi\n\t, devicetree ,\n\tChen-Yu Tsai , Andre Przywara ,\n\tlinux-kernel , \n\tDan Williams , Rob Herring\n\t, dmaengine@vger.kernel.org, Code Kipper\n\t, linux-arm-kernel\n\t, Catalin Marinas\n\t, Will Deacon ,\n\tMark Rutland , Maxime Ripard\n\t","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"8BIT","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1787172,"web_url":"http://patchwork.ozlabs.org/comment/1787172/","msgid":"<20171016070258.GP30097@localhost>","list_archive_url":null,"date":"2017-10-16T07:02:58","subject":"Re: [PATCH v4 00/11] dmaengine: sun6i: Fixes for H3/A83T, enable A64","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Thu, Sep 28, 2017 at 03:49:17AM +0200, Stefan Brüns wrote:\n> Commit 3a03ea763a67 (\"dmaengine: sun6i: Add support for Allwinner A83T\n> (sun8i) variant\") and commit f008db8c00c1 (\"dmaengine: sun6i: Add support for\n> Allwinner H3 (sun8i) variant\") added support for the A83T resp. H3, but missed\n> some differences between the original A31 and A83T/H3.\n\nApplied 1 thru 8, 7 didn't applied though!\n\nThanks","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yFq1475M7z9sRV\n\tfor ;\n\tMon, 16 Oct 2017 17:58:48 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751731AbdJPG6r (ORCPT\n\t);\n\tMon, 16 Oct 2017 02:58:47 -0400","from mga03.intel.com ([134.134.136.65]:25923 \"EHLO mga03.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750914AbdJPG6q (ORCPT );\n\tMon, 16 Oct 2017 02:58:46 -0400","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t15 Oct 2017 23:58:45 -0700","from vkoul-udesk7.iind.intel.com (HELO localhost) ([10.223.84.143])\n\tby fmsmga002.fm.intel.com with ESMTP; 15 Oct 2017 23:58:41 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos; i=\"5.43,385,1503385200\"; d=\"scan'208\";\n\ta=\"1231216348\"","Date":"Mon, 16 Oct 2017 12:32:58 +0530","From":"Vinod Koul ","To":"Stefan =?iso-8859-1?q?Br=FCns?= ","Cc":"linux-sunxi@googlegroups.com, devicetree@vger.kernel.org,\n\tChen-Yu Tsai , Andre Przywara ,\n\tlinux-kernel@vger.kernel.org, Dan Williams ,\n\tRob Herring , dmaengine@vger.kernel.org,\n\tCode Kipper ,\n\tMaxime Ripard ,\n\tlinux-arm-kernel@lists.infradead.org,\n\tCatalin Marinas ,\n\tWill Deacon , Mark Rutland ","Subject":"Re: [PATCH v4 00/11] dmaengine: sun6i: Fixes for H3/A83T, enable A64","Message-ID":"<20171016070258.GP30097@localhost>","References":"<3c78e966-2ece-4e67-94de-801aa569089f@rwthex-w2-a.rwth-ad.de>","MIME-Version":"1.0","Content-Type":"text/plain; charset=iso-8859-1","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"<3c78e966-2ece-4e67-94de-801aa569089f@rwthex-w2-a.rwth-ad.de>","User-Agent":"Mutt/1.5.24 (2015-08-30)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]