[{"id":1780348,"web_url":"http://patchwork.ozlabs.org/comment/1780348/","msgid":"<20171005094138.11b73a0e@xps13>","list_archive_url":null,"date":"2017-10-05T07:41:38","subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","submitter":{"id":71917,"url":"http://patchwork.ozlabs.org/api/people/71917/","name":"Miquel Raynal","email":"miquel.raynal@free-electrons.com"},"content":"Hello Kalyan,\n\nOn Thu, 28 Sep 2017 13:57:56 +1300\nKalyan Kinthada wrote:\n\n> When the arbitration between NOR and NAND flash is enabled\n> the field bit[21] in the Data Flash Control Register\n> needs to be set to 1 according to guidleine GL-5830741 mentioned\n\nTypo: guideline ^\n\n> in Marvell Errata document MV-S501377-00, Rev. D.\n\nThanks for that, I checked it.\n\n> \n> This commit sets the FORCE_CSX bit to 1 for all\n> ARMADA370 variants as the arbitration is always enabled by default.\n> This change does not apply for pxa3xx variants because the FORCE_CSX\n> bit does not exist/reserved on the NFCv1.\n\nSorry to bother you again but I am reworking the pxa3xx_nand driver and\nso I would like to deeply understand why this is needed because I will\nhave to integrate it in my work too.\n\nSo please tell me what is your setup, do you really use NAND/NOR\narbitration? Do you have not-Don't Care CS NAND chips? I have some\ndoubts because even if the spec precises in the NAND controller chapter\nthat arbitration is always enabled by default, the bit 27 (NfArbiterEn)\nin the SoC Device Multiplex Register at offset 0x00018208 is actually\nat 0 by default (disabled). Did you enable this bit manually ? I\nchecked with devmem on my setup and this bit was unset.\n\nThank you for your time,\nMiquèl\n\n> \n> The NDCR_ND_MODE conflicts with the new NDCR_FORCE_CSX but is unused\n> so remove it along with NDCR_NAND_MODE.\n> \n> Signed-off-by: Kalyan Kinthada \n> ---\n\n\n\n> drivers/mtd/nand/pxa3xx_nand.c | 9 +++++++--\n> 1 file changed, 7 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..a6a7a5af7bed\n> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n> @@ -67,8 +67,7 @@\n> #define NDCR_DWIDTH_M\t\t(0x1 << 26)\n> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n> #define NDCR_NCSX\t\t(0x1 << 23)\n> -#define NDCR_ND_MODE\t\t(0x3 << 21)\n> -#define NDCR_NAND_MODE \t(0x0)\n> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n> #define NFCV2_NDCR_STOP_ON_UNCOR\t(0x1 << 19)\n> @@ -1464,6 +1463,9 @@ static int pxa3xx_nand_config_ident(struct\n> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN :\n> 0;\n> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n> GL-5830741 */\n> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n> \n> @@ -1498,6 +1500,9 @@ static void pxa3xx_nand_detect_config(struct\n> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n> NDCR_ND_ARB_EN : 0;\n> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n> GL-5830741 */\n> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n> }","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y74Tg1q3Jz9t3h\n\tfor ;\n\tThu, 5 Oct 2017 18:41:43 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751335AbdJEHll convert rfc822-to-8bit (ORCPT\n\t);\n\tThu, 5 Oct 2017 03:41:41 -0400","from mail.free-electrons.com ([62.4.15.54]:34425 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751296AbdJEHlk (ORCPT\n\t); Thu, 5 Oct 2017 03:41:40 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 8D4772094A; Thu, 5 Oct 2017 09:41:38 +0200 (CEST)","from xps13 (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 2BD2820939;\n\tThu, 5 Oct 2017 09:41:38 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 5 Oct 2017 09:41:38 +0200","From":"Miquel RAYNAL ","To":"Kalyan Kinthada ","Cc":"dwmw2@infradead.org, computersforpeace@gmail.com,\n\tboris.brezillon@free-electrons.com, marek.vasut@gmail.com,\n\trichard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,\n\tmark.rutland@arm.com, ezequiel.garcia@free-electrons.com,\n\tdevicetree@vger.kernel.org, chris.packham@alliedtelesis.co.nz,\n\tlinux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","Message-ID":"<20171005094138.11b73a0e@xps13>","In-Reply-To":"<20170928005756.3938-2-kalyan.kinthada@alliedtelesis.co.nz>","References":"<20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170928005756.3938-2-kalyan.kinthada@alliedtelesis.co.nz>","Organization":"Free Electrons","X-Mailer":"Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8BIT","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1782386,"web_url":"http://patchwork.ozlabs.org/comment/1782386/","msgid":"","list_archive_url":null,"date":"2017-10-09T02:31:30","subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370\n\tvariants.","submitter":{"id":72417,"url":"http://patchwork.ozlabs.org/api/people/72417/","name":"Kalyan Kinthada","email":"kalyan.kinthada@alliedtelesis.co.nz"},"content":"On 05/10/17 20:41, Miquel RAYNAL wrote:\r\n> Hello Kalyan,\r\n>\r\n> On Thu, 28 Sep 2017 13:57:56 +1300\r\n> Kalyan Kinthada wrote:\r\n>\r\n>> When the arbitration between NOR and NAND flash is enabled\r\n>> the field bit[21] in the Data Flash Control Register\r\n>> needs to be set to 1 according to guidleine GL-5830741 mentioned\r\n> Typo: guideline ^\r\nI will correct this typo in the next patch version.\r\n>> in Marvell Errata document MV-S501377-00, Rev. D.\r\n> Thanks for that, I checked it.\r\n>\r\n>> This commit sets the FORCE_CSX bit to 1 for all\r\n>> ARMADA370 variants as the arbitration is always enabled by default.\r\n>> This change does not apply for pxa3xx variants because the FORCE_CSX\r\n>> bit does not exist/reserved on the NFCv1.\r\n> Sorry to bother you again but I am reworking the pxa3xx_nand driver and\r\n> so I would like to deeply understand why this is needed because I will\r\n> have to integrate it in my work too.\r\n>\r\n> So please tell me what is your setup, do you really use NAND/NOR\r\n> arbitration? Do you have not-Don't Care CS NAND chips? I have some\r\n> doubts because even if the spec precises in the NAND controller chapter\r\n> that arbitration is always enabled by default, the bit 27 (NfArbiterEn)\r\n> in the SoC Device Multiplex Register at offset 0x00018208 is actually\r\n> at 0 by default (disabled). Did you enable this bit manually ? I\r\n> checked with devmem on my setup and this bit was unset.\r\nYes, my setup use NAND/NOR arbitration and use a Don't\r\ncare CS Nand Chip. The bit 27 at offset 0x00018208 is set to 1\r\nby default in my case. I did not manually set the bit 27 to 1.\r\n\r\nPlease let me now if you have any other question or do you want me\r\nto send the updated patch version with the typo fixed.\r\n\r\nThank You,\r\nKalyan\r\n\r\n>\r\n> Thank you for your time,\r\n> Miquèl\r\n>\r\n>> The NDCR_ND_MODE conflicts with the new NDCR_FORCE_CSX but is unused\r\n>> so remove it along with NDCR_NAND_MODE.\r\n>>\r\n>> Signed-off-by: Kalyan Kinthada \r\n>> ---\r\n>\r\n>\r\n>> drivers/mtd/nand/pxa3xx_nand.c | 9 +++++++--\r\n>> 1 file changed, 7 insertions(+), 2 deletions(-)\r\n>>\r\n>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\r\n>> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..a6a7a5af7bed\r\n>> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\r\n>> +++ b/drivers/mtd/nand/pxa3xx_nand.c\r\n>> @@ -67,8 +67,7 @@\r\n>> #define NDCR_DWIDTH_M\t\t(0x1 << 26)\r\n>> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\r\n>> #define NDCR_NCSX\t\t(0x1 << 23)\r\n>> -#define NDCR_ND_MODE\t\t(0x3 << 21)\r\n>> -#define NDCR_NAND_MODE \t(0x0)\r\n>> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\r\n>> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\r\n>> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\r\n>> #define NFCV2_NDCR_STOP_ON_UNCOR\t(0x1 << 19)\r\n>> @@ -1464,6 +1463,9 @@ static int pxa3xx_nand_config_ident(struct\r\n>> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\r\n>> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\r\n>> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN :\r\n>> 0;\r\n>> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\r\n>> GL-5830741 */\r\n>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\r\n>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\r\n>> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\r\n>> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\r\n>> \r\n>> @@ -1498,6 +1500,9 @@ static void pxa3xx_nand_detect_config(struct\r\n>> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\r\n>> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\r\n>> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\r\n>> NDCR_ND_ARB_EN : 0;\r\n>> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\r\n>> GL-5830741 */\r\n>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\r\n>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\r\n>> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\r\n>> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\r\n>> }\r\n>\r\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=alliedtelesis.co.nz\n\theader.i=@alliedtelesis.co.nz\n\theader.b=\"dKwxuL1H\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y9PQ11L8rz9t3Z\n\tfor ;\n\tMon, 9 Oct 2017 13:31:36 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753408AbdJICbf (ORCPT\n\t);\n\tSun, 8 Oct 2017 22:31:35 -0400","from gate2.alliedtelesis.co.nz ([202.36.163.20]:41198 \"EHLO\n\tgate2.alliedtelesis.co.nz\" rhost-flags-OK-OK-OK-OK) by\n\tvger.kernel.org with ESMTP id S1751397AbdJICbe (ORCPT\n\t); Sun, 8 Oct 2017 22:31:34 -0400","from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (Client did not present a certificate)\n\tby gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 8860B8365D;\n\tMon, 9 Oct 2017 15:31:31 +1300 (NZDT)","from svr-chch-ex1.atlnz.lc (Not Verified[10.32.16.77]) by\n\tmmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 8, 10121)\n\tid ; Mon, 09 Oct 2017 15:31:31 +1300","from svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8::77) by\n\tsvr-chch-ex1.atlnz.lc (2001:df5:b000:bc8::77) with Microsoft SMTP\n\tServer (TLS) id 15.0.1156.6; Mon, 9 Oct 2017 15:31:31 +1300","from svr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8]) by\n\tsvr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8%12]) with mapi id\n\t15.00.1156.000; Mon, 9 Oct 2017 15:31:31 +1300"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; \n\ts=mail; t=1507516291;\n\tbh=4PvFuoNz7ESISVjnHmEUmb/R9hdOBTbHA1P9vMw6EwA=;\n\th=From:To:CC:Subject:Date:References:In-Reply-To;\n\tb=dKwxuL1HsNi8/HGNlhDMlrY/RFOBBS0uIoeYbPi9InvxApLAytSOwcdlAT4DN18kB\n\tvH9AwDaEGt+iC1hFeDNUEscWvRNALKjNXg0HYBpBkWpAKCK6L4ZkoZBJbOLe2tXIhp\n\tsIYD996byMRsrRhqUKlQAe/GKxYAodw2ZrK0XlKE=","From":"Kalyan Kinthada ","To":"Miquel RAYNAL ","CC":"\"dwmw2@infradead.org\" ,\n\t\"computersforpeace@gmail.com\" ,\n\t\"boris.brezillon@free-electrons.com\"\n\t, \n\t\"marek.vasut@gmail.com\" ,\n\t\"richard@nod.at\" ,\n\t\"cyrille.pitchen@wedev4u.fr\" ,\n\t\"robh+dt@kernel.org\" ,\n\t\"mark.rutland@arm.com\" ,\n\t\"ezequiel.garcia@free-electrons.com\"\n\t, \n\t\"devicetree@vger.kernel.org\" ,\n\tChris Packham ,\n\t\"linux-mtd@lists.infradead.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ","Subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370\n\tvariants.","Thread-Topic":"[PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","Thread-Index":"AQHTN/TV84NhrKrRv0aGyA/oHIy1raLUEOkAgAXypQA=","Date":"Mon, 9 Oct 2017 02:31:30 +0000","Message-ID":"","References":"<20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170928005756.3938-2-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20171005094138.11b73a0e@xps13>","In-Reply-To":"<20171005094138.11b73a0e@xps13>","Accept-Language":"en-NZ, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-ms-exchange-messagesentrepresentingtype":"1","x-ms-exchange-transport-fromentityheader":"Hosted","x-originating-ip":"[10.32.16.78]","Content-Type":"text/plain; charset=\"utf-8\"","Content-ID":"","Content-Transfer-Encoding":"base64","MIME-Version":"1.0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1782525,"web_url":"http://patchwork.ozlabs.org/comment/1782525/","msgid":"<20171009081848.49681975@xps13>","list_archive_url":null,"date":"2017-10-09T06:18:48","subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","submitter":{"id":71917,"url":"http://patchwork.ozlabs.org/api/people/71917/","name":"Miquel Raynal","email":"miquel.raynal@free-electrons.com"},"content":"Hello Kalyan,\n\nOn Mon, 9 Oct 2017 02:31:30 +0000\nKalyan Kinthada wrote:\n\n> On 05/10/17 20:41, Miquel RAYNAL wrote:\n> > Hello Kalyan,\n> >\n> > On Thu, 28 Sep 2017 13:57:56 +1300\n> > Kalyan Kinthada wrote:\n> > \n> >> When the arbitration between NOR and NAND flash is enabled\n> >> the field bit[21] in the Data Flash Control Register\n> >> needs to be set to 1 according to guidleine GL-5830741 mentioned \n> > Typo: guideline ^ \n> I will correct this typo in the next patch version.\n> >> in Marvell Errata document MV-S501377-00, Rev. D. \n> > Thanks for that, I checked it.\n> > \n> >> This commit sets the FORCE_CSX bit to 1 for all\n> >> ARMADA370 variants as the arbitration is always enabled by default.\n> >> This change does not apply for pxa3xx variants because the\n> >> FORCE_CSX bit does not exist/reserved on the NFCv1. \n> > Sorry to bother you again but I am reworking the pxa3xx_nand driver\n> > and so I would like to deeply understand why this is needed because\n> > I will have to integrate it in my work too.\n> >\n> > So please tell me what is your setup, do you really use NAND/NOR\n> > arbitration? Do you have not-Don't Care CS NAND chips? I have some\n> > doubts because even if the spec precises in the NAND controller\n> > chapter that arbitration is always enabled by default, the bit 27\n> > (NfArbiterEn) in the SoC Device Multiplex Register at offset\n> > 0x00018208 is actually at 0 by default (disabled). Did you enable\n> > this bit manually ? I checked with devmem on my setup and this bit\n> > was unset. \n> Yes, my setup use NAND/NOR arbitration and use a Don't\n> care CS Nand Chip. The bit 27 at offset 0x00018208 is set to 1\n> by default in my case. I did not manually set the bit 27 to 1.\n\nActually if you use Don't Care CS NAND chips you should not need the\nforce CS bit, as it is mentioned in the guidelines you pointed, this\nbit is only useful for *not* don't care CS NAND chips (and the name\n\"force CS\" is pretty straight forward too!).\n\nOtherwise what bootloader and kernel do you use to have this\nbit set by default? You may also want to check if this bit is set by\nyour bootloader by stopping it before it loads Linux and check manually\nthe value of this bit with 'md' (on U-Boot).\n\nThank you,\nMiquèl\n\n> \n> Please let me now if you have any other question or do you want me\n> to send the updated patch version with the typo fixed.\n> \n> Thank You,\n> Kalyan\n> \n> >\n> > Thank you for your time,\n> > Miquèl\n> > \n> >> The NDCR_ND_MODE conflicts with the new NDCR_FORCE_CSX but is\n> >> unused so remove it along with NDCR_NAND_MODE.\n> >>\n> >> Signed-off-by: Kalyan Kinthada\n> >> --- \n> >\n> > \n> >> drivers/mtd/nand/pxa3xx_nand.c | 9 +++++++--\n> >> 1 file changed, 7 insertions(+), 2 deletions(-)\n> >>\n> >> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n> >> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..a6a7a5af7bed\n> >> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n> >> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n> >> @@ -67,8 +67,7 @@\n> >> #define NDCR_DWIDTH_M\t\t(0x1 << 26)\n> >> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n> >> #define NDCR_NCSX\t\t(0x1 << 23)\n> >> -#define NDCR_ND_MODE\t\t(0x3 << 21)\n> >> -#define NDCR_NAND_MODE \t(0x0)\n> >> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n> >> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n> >> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n> >> #define NFCV2_NDCR_STOP_ON_UNCOR\t(0x1 << 19)\n> >> @@ -1464,6 +1463,9 @@ static int pxa3xx_nand_config_ident(struct\n> >> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n> >> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n> >> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ?\n> >> NDCR_ND_ARB_EN : 0;\n> >> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n> >> GL-5830741 */\n> >> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> >> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> >> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n> >> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n> >> \n> >> @@ -1498,6 +1500,9 @@ static void pxa3xx_nand_detect_config(struct\n> >> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n> >> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n> >> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n> >> NDCR_ND_ARB_EN : 0;\n> >> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n> >> GL-5830741 */\n> >> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> >> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> >> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n> >> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n> >> } \n> >\n> >","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y9VSH2ywXz9tY0\n\tfor ;\n\tMon, 9 Oct 2017 17:18:55 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751530AbdJIGSw convert rfc822-to-8bit (ORCPT\n\t);\n\tMon, 9 Oct 2017 02:18:52 -0400","from mail.free-electrons.com ([62.4.15.54]:44603 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751361AbdJIGSv (ORCPT\n\t); Mon, 9 Oct 2017 02:18:51 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 57363208B9; Mon, 9 Oct 2017 08:18:49 +0200 (CEST)","from xps13 (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id EF87A208A9;\n\tMon, 9 Oct 2017 08:18:48 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 9 Oct 2017 08:18:48 +0200","From":"Miquel RAYNAL ","To":"Kalyan Kinthada ","Cc":"\"dwmw2@infradead.org\" ,\n\t\"computersforpeace@gmail.com\" ,\n\t\"boris.brezillon@free-electrons.com\"\n\t, \n\t\"marek.vasut@gmail.com\" ,\n\t\"richard@nod.at\" ,\n\t\"cyrille.pitchen@wedev4u.fr\" ,\n\t\"robh+dt@kernel.org\" ,\n\t\"mark.rutland@arm.com\" ,\n\t\"ezequiel.garcia@free-electrons.com\"\n\t, \n\t\"devicetree@vger.kernel.org\" ,\n\tChris Packham ,\n\t\"linux-mtd@lists.infradead.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ","Subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","Message-ID":"<20171009081848.49681975@xps13>","In-Reply-To":"","References":"<20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170928005756.3938-2-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20171005094138.11b73a0e@xps13>\n\t","Organization":"Free Electrons","X-Mailer":"Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8BIT","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1786831,"web_url":"http://patchwork.ozlabs.org/comment/1786831/","msgid":"<20171014151233.4e9ff319@bbrezillon>","list_archive_url":null,"date":"2017-10-14T13:12:33","subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","submitter":{"id":63120,"url":"http://patchwork.ozlabs.org/api/people/63120/","name":"Boris Brezillon","email":"boris.brezillon@free-electrons.com"},"content":"Hi Kalyan,\n\nOn Thu, 28 Sep 2017 13:57:56 +1300\nKalyan Kinthada wrote:\n\n> When the arbitration between NOR and NAND flash is enabled\n> the field bit[21] in the Data Flash Control Register\n> needs to be set to 1 according to guidleine GL-5830741 mentioned\n> in Marvell Errata document MV-S501377-00, Rev. D.\n\nThe real question is, is this patch fixing a real bug or are you just\nsetting this bit because a guideline says it should be set? As far as I\nunderstand, noone fully understands what this bit does and why it needs\nto be set, so if you're not fixing a real bug, I'd prefer keeping the\ncode unchanged code until someone complains for a good reason.\n\nRegards,\n\nBoris\n\n> \n> This commit sets the FORCE_CSX bit to 1 for all\n> ARMADA370 variants as the arbitration is always enabled by default.\n> This change does not apply for pxa3xx variants because the FORCE_CSX\n> bit does not exist/reserved on the NFCv1.\n> \n> The NDCR_ND_MODE conflicts with the new NDCR_FORCE_CSX but is unused so\n> remove it along with NDCR_NAND_MODE.\n> \n> Signed-off-by: Kalyan Kinthada \n> ---\n> drivers/mtd/nand/pxa3xx_nand.c | 9 +++++++--\n> 1 file changed, 7 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c\n> index 85cff68643e0..a6a7a5af7bed 100644\n> --- a/drivers/mtd/nand/pxa3xx_nand.c\n> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n> @@ -67,8 +67,7 @@\n> #define NDCR_DWIDTH_M\t\t(0x1 << 26)\n> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n> #define NDCR_NCSX\t\t(0x1 << 23)\n> -#define NDCR_ND_MODE\t\t(0x3 << 21)\n> -#define NDCR_NAND_MODE \t(0x0)\n> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n> #define NFCV2_NDCR_STOP_ON_UNCOR\t(0x1 << 19)\n> @@ -1464,6 +1463,9 @@ static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)\n> \tinfo->chunk_size = PAGE_CHUNK_SIZE;\n> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;\n> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#: GL-5830741 */\n> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n> \n> @@ -1498,6 +1500,9 @@ static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)\n> \tinfo->reg_ndcr = ndcr &\n> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);\n> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;\n> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#: GL-5830741 */\n> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n> }\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yDlPc4dS4z9t3h\n\tfor ;\n\tSun, 15 Oct 2017 00:12:52 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752803AbdJNNMt (ORCPT\n\t);\n\tSat, 14 Oct 2017 09:12:49 -0400","from mail.free-electrons.com ([62.4.15.54]:48288 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751550AbdJNNMt (ORCPT\n\t); Sat, 14 Oct 2017 09:12:49 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 3A0E820417; Sat, 14 Oct 2017 15:12:46 +0200 (CEST)","from bbrezillon (91-160-177-164.subs.proxad.net [91.160.177.164])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id DFF1B203B3;\n\tSat, 14 Oct 2017 15:12:35 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Sat, 14 Oct 2017 15:12:33 +0200","From":"Boris Brezillon ","To":"Kalyan Kinthada ","Cc":"dwmw2@infradead.org, computersforpeace@gmail.com,\n\tmarek.vasut@gmail.com, richard@nod.at, cyrille.pitchen@wedev4u.fr,\n\trobh+dt@kernel.org, mark.rutland@arm.com,\n\tezequiel.garcia@free-electrons.com,\n\tmiquel.raynal@free-electrons.com, devicetree@vger.kernel.org,\n\tlinux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tchris.packham@alliedtelesis.co.nz","Subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","Message-ID":"<20171014151233.4e9ff319@bbrezillon>","In-Reply-To":"<20170928005756.3938-2-kalyan.kinthada@alliedtelesis.co.nz>","References":"<20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170928005756.3938-2-kalyan.kinthada@alliedtelesis.co.nz>","X-Mailer":"Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1787075,"web_url":"http://patchwork.ozlabs.org/comment/1787075/","msgid":"<5d708701612f48cf958da5feeb68365f@svr-chch-ex1.atlnz.lc>","list_archive_url":null,"date":"2017-10-15T20:55:43","subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370\n\tvariants.","submitter":{"id":27499,"url":"http://patchwork.ozlabs.org/api/people/27499/","name":"Chris Packham","email":"chris.packham@alliedtelesis.co.nz"},"content":"Hi Boris,\n\nOn 15/10/17 02:13, Boris Brezillon wrote:\n> Hi Kalyan,\n> \n> On Thu, 28 Sep 2017 13:57:56 +1300\n> Kalyan Kinthada wrote:\n> \n>> When the arbitration between NOR and NAND flash is enabled\n>> the field bit[21] in the Data Flash Control Register\n>> needs to be set to 1 according to guidleine GL-5830741 mentioned\n>> in Marvell Errata document MV-S501377-00, Rev. D.\n> \n> The real question is, is this patch fixing a real bug or are you just\n> setting this bit because a guideline says it should be set?\n\nYes that's a fair summary. It is in a document called \"Functional \nErrata\" so there is some feeling here that we (allied telesis) should \nfollow up things in these kinds of documents.\n\n> As far as I\n> understand, noone fully understands what this bit does and why it needs\n> to be set, so if you're not fixing a real bug, I'd prefer keeping the\n> code unchanged code until someone complains for a good reason.\n\nAgreed. We've certainly not noticed a change in behaviour on our boards. \nI've requested more information from Marvell through their support \nchannels. I'll share what I can if/when they come back with something \nuseful.\n\n> \n> Regards,\n> \n> Boris\n> \n>>\n>> This commit sets the FORCE_CSX bit to 1 for all\n>> ARMADA370 variants as the arbitration is always enabled by default.\n>> This change does not apply for pxa3xx variants because the FORCE_CSX\n>> bit does not exist/reserved on the NFCv1.\n>>\n>> The NDCR_ND_MODE conflicts with the new NDCR_FORCE_CSX but is unused so\n>> remove it along with NDCR_NAND_MODE.\n>>\n>> Signed-off-by: Kalyan Kinthada \n>> ---\n>> drivers/mtd/nand/pxa3xx_nand.c | 9 +++++++--\n>> 1 file changed, 7 insertions(+), 2 deletions(-)\n>>\n>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c\n>> index 85cff68643e0..a6a7a5af7bed 100644\n>> --- a/drivers/mtd/nand/pxa3xx_nand.c\n>> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n>> @@ -67,8 +67,7 @@\n>> #define NDCR_DWIDTH_M\t\t(0x1 << 26)\n>> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n>> #define NDCR_NCSX\t\t(0x1 << 23)\n>> -#define NDCR_ND_MODE\t\t(0x3 << 21)\n>> -#define NDCR_NAND_MODE \t(0x0)\n>> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n>> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n>> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n>> #define NFCV2_NDCR_STOP_ON_UNCOR\t(0x1 << 19)\n>> @@ -1464,6 +1463,9 @@ static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)\n>> \tinfo->chunk_size = PAGE_CHUNK_SIZE;\n>> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n>> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;\n>> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#: GL-5830741 */\n>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n>> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n>> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n>> \n>> @@ -1498,6 +1500,9 @@ static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)\n>> \tinfo->reg_ndcr = ndcr &\n>> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);\n>> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;\n>> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#: GL-5830741 */\n>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n>> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n>> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n>> }\n> \n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=alliedtelesis.co.nz\n\theader.i=@alliedtelesis.co.nz\n\theader.b=\"aVXIYL99\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yFYdK3QwQz9sNx\n\tfor ;\n\tMon, 16 Oct 2017 07:55:49 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751356AbdJOUzr (ORCPT\n\t);\n\tSun, 15 Oct 2017 16:55:47 -0400","from gate2.alliedtelesis.co.nz ([202.36.163.20]:51996 \"EHLO\n\tgate2.alliedtelesis.co.nz\" rhost-flags-OK-OK-OK-OK) by\n\tvger.kernel.org with ESMTP id S1751343AbdJOUzq (ORCPT\n\t); Sun, 15 Oct 2017 16:55:46 -0400","from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (Client did not present a certificate)\n\tby gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 181668365B;\n\tMon, 16 Oct 2017 09:55:44 +1300 (NZDT)","from svr-chch-ex1.atlnz.lc (Not Verified[10.32.16.77]) by\n\tmmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 8, 10121)\n\tid ; Mon, 16 Oct 2017 09:55:42 +1300","from svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8::77) by\n\tsvr-chch-ex1.atlnz.lc (2001:df5:b000:bc8::77) with Microsoft SMTP\n\tServer (TLS) id 15.0.1156.6; Mon, 16 Oct 2017 09:55:43 +1300","from svr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8]) by\n\tsvr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8%12]) with mapi id\n\t15.00.1156.000; Mon, 16 Oct 2017 09:55:43 +1300"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; \n\ts=mail; t=1508100944;\n\tbh=YRnkvgBZ3iIPFeeqhotInaFFdrTmaigAeZMMDjz+8u4=;\n\th=From:To:CC:Subject:Date:References;\n\tb=aVXIYL99R5Pl23TQtK2yT+s/jSZT0MTnCkg5D800F7dvE8tsnynHn2mqJtPvP7769\n\teVdcSIl4BnJhZidEAmZE8TG51VJKoGzzvPB7WQv6AyDm6QDSQedlMp5PqfuU2nZtD5\n\trK8nKgLacSLqVH8Fyoah90PsOMEfdLorb3nXialg=","From":"Chris Packham ","To":"Boris Brezillon ,\n\tKalyan Kinthada ","CC":"\"dwmw2@infradead.org\" ,\n\t\"computersforpeace@gmail.com\" ,\n\t\"marek.vasut@gmail.com\" ,\n\t\"richard@nod.at\" ,\n\t\"cyrille.pitchen@wedev4u.fr\" ,\n\t\"robh+dt@kernel.org\" ,\n\t\"mark.rutland@arm.com\" ,\n\t\"ezequiel.garcia@free-electrons.com\"\n\t, \n\t\"miquel.raynal@free-electrons.com\" ,\n\t\"devicetree@vger.kernel.org\" ,\n\t\"linux-mtd@lists.infradead.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ","Subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370\n\tvariants.","Thread-Topic":"[PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","Thread-Index":"AQHTN/TV5c3BTkMJ8EyjaCc6GEyjZw==","Date":"Sun, 15 Oct 2017 20:55:43 +0000","Message-ID":"<5d708701612f48cf958da5feeb68365f@svr-chch-ex1.atlnz.lc>","References":"<20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170928005756.3938-2-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20171014151233.4e9ff319@bbrezillon>","Accept-Language":"en-NZ, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-ms-exchange-transport-fromentityheader":"Hosted","x-originating-ip":"[2001:df5:b000:22:3a2c:4aff:fe70:2b02]","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1796382,"web_url":"http://patchwork.ozlabs.org/comment/1796382/","msgid":"","list_archive_url":null,"date":"2017-10-31T03:15:01","subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370\n\tvariants.","submitter":{"id":27499,"url":"http://patchwork.ozlabs.org/api/people/27499/","name":"Chris Packham","email":"chris.packham@alliedtelesis.co.nz"},"content":"Hi Miquel,\n\nOn 09/10/17 19:19, Miquel RAYNAL wrote:\n> Hello Kalyan,\n> \n> On Mon, 9 Oct 2017 02:31:30 +0000\n> Kalyan Kinthada wrote:\n> \n>> On 05/10/17 20:41, Miquel RAYNAL wrote:\n>>> Hello Kalyan,\n>>>\n>>> On Thu, 28 Sep 2017 13:57:56 +1300\n>>> Kalyan Kinthada wrote:\n>>> \n>>>> When the arbitration between NOR and NAND flash is enabled\n>>>> the field bit[21] in the Data Flash Control Register\n>>>> needs to be set to 1 according to guidleine GL-5830741 mentioned\n>>> Typo: guideline ^\n>> I will correct this typo in the next patch version.\n>>>> in Marvell Errata document MV-S501377-00, Rev. D.\n>>> Thanks for that, I checked it.\n>>> \n>>>> This commit sets the FORCE_CSX bit to 1 for all\n>>>> ARMADA370 variants as the arbitration is always enabled by default.\n>>>> This change does not apply for pxa3xx variants because the\n>>>> FORCE_CSX bit does not exist/reserved on the NFCv1.\n>>> Sorry to bother you again but I am reworking the pxa3xx_nand driver\n>>> and so I would like to deeply understand why this is needed because\n>>> I will have to integrate it in my work too.\n>>>\n>>> So please tell me what is your setup, do you really use NAND/NOR\n>>> arbitration? Do you have not-Don't Care CS NAND chips? I have some\n>>> doubts because even if the spec precises in the NAND controller\n>>> chapter that arbitration is always enabled by default, the bit 27\n>>> (NfArbiterEn) in the SoC Device Multiplex Register at offset\n>>> 0x00018208 is actually at 0 by default (disabled). Did you enable\n>>> this bit manually ? I checked with devmem on my setup and this bit\n>>> was unset.\n>> Yes, my setup use NAND/NOR arbitration and use a Don't\n>> care CS Nand Chip. The bit 27 at offset 0x00018208 is set to 1\n>> by default in my case. I did not manually set the bit 27 to 1.\n> \n> Actually if you use Don't Care CS NAND chips you should not need the\n> force CS bit, as it is mentioned in the guidelines you pointed, this\n> bit is only useful for *not* don't care CS NAND chips (and the name\n> \"force CS\" is pretty straight forward too!).\n\nIt's less straight forward than you think. It's FORCE_CSX (the X is \nimportant) which is defined as \"force chip select false on busy\". What \nit means is that the NF_CSn is de-asserted if the interface is \narbitrated away from the NAND flash controller. I think that means you \nwon't end up with the chip-select for the dev-bus/NOR firing immediately \nwhen that device is arbitrated.\n\n> Otherwise what bootloader and kernel do you use to have this\n> bit set by default? You may also want to check if this bit is set by\n> your bootloader by stopping it before it loads Linux and check manually\n> the value of this bit with 'md' (on U-Boot).\n> \n> Thank you,\n> Miquèl\n> \n>>\n>> Please let me now if you have any other question or do you want me\n>> to send the updated patch version with the typo fixed.\n>>\n>> Thank You,\n>> Kalyan\n>>\n>>>\n>>> Thank you for your time,\n>>> Miquèl\n>>> \n>>>> The NDCR_ND_MODE conflicts with the new NDCR_FORCE_CSX but is\n>>>> unused so remove it along with NDCR_NAND_MODE.\n>>>>\n>>>> Signed-off-by: Kalyan Kinthada\n>>>> ---\n>>>\n>>> \n>>>> drivers/mtd/nand/pxa3xx_nand.c | 9 +++++++--\n>>>> 1 file changed, 7 insertions(+), 2 deletions(-)\n>>>>\n>>>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n>>>> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..a6a7a5af7bed\n>>>> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n>>>> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n>>>> @@ -67,8 +67,7 @@\n>>>> #define NDCR_DWIDTH_M\t\t(0x1 << 26)\n>>>> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n>>>> #define NDCR_NCSX\t\t(0x1 << 23)\n>>>> -#define NDCR_ND_MODE\t\t(0x3 << 21)\n>>>> -#define NDCR_NAND_MODE \t(0x0)\n>>>> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n>>>> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n>>>> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n>>>> #define NFCV2_NDCR_STOP_ON_UNCOR\t(0x1 << 19)\n>>>> @@ -1464,6 +1463,9 @@ static int pxa3xx_nand_config_ident(struct\n>>>> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n>>>> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n>>>> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ?\n>>>> NDCR_ND_ARB_EN : 0;\n>>>> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n>>>> GL-5830741 */\n>>>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n>>>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n>>>> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n>>>> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n>>>> \n>>>> @@ -1498,6 +1500,9 @@ static void pxa3xx_nand_detect_config(struct\n>>>> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n>>>> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n>>>> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n>>>> NDCR_ND_ARB_EN : 0;\n>>>> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n>>>> GL-5830741 */\n>>>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n>>>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n>>>> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n>>>> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n>>>> }\n>>>\n>>> \n> \n> \n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=alliedtelesis.co.nz\n\theader.i=@alliedtelesis.co.nz\n\theader.b=\"b7Ga01Ho\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yQxL76vcyz9t3C\n\tfor ;\n\tTue, 31 Oct 2017 14:15:11 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752231AbdJaDPK (ORCPT\n\t);\n\tMon, 30 Oct 2017 23:15:10 -0400","from gate2.alliedtelesis.co.nz ([202.36.163.20]:53299 \"EHLO\n\tgate2.alliedtelesis.co.nz\" rhost-flags-OK-OK-OK-OK) by\n\tvger.kernel.org with ESMTP id S1751742AbdJaDPJ (ORCPT\n\t); Mon, 30 Oct 2017 23:15:09 -0400","from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (Client did not present a certificate)\n\tby gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 96DC784482;\n\tTue, 31 Oct 2017 16:15:06 +1300 (NZDT)","from svr-chch-ex1.atlnz.lc (Not Verified[10.32.16.77]) by\n\tmmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 8, 10121)\n\tid ; Tue, 31 Oct 2017 16:15:06 +1300","from svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8:409d:36f5:8899:92e8)\n\tby svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8:409d:36f5:8899:92e8)\n\twith Microsoft SMTP Server (TLS) id 15.0.1156.6;\n\tTue, 31 Oct 2017 16:15:01 +1300","from svr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8]) by\n\tsvr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8%12]) with mapi id\n\t15.00.1156.000; Tue, 31 Oct 2017 16:15:01 +1300"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; \n\ts=mail; t=1509419706;\n\tbh=lqYCFKb5U1q+gynoEJ5wRCl8n6nYTc++g7pt0AruuR8=;\n\th=From:To:CC:Subject:Date:References;\n\tb=b7Ga01HoLM1FA4+t2TPqWIevNCAavRRRlPdzhNSpV+Nil3UjQc44V9d2BYUkiMmg9\n\ta1hq/XSXNzYNr5zmSCUQX4xye0iAwDApuUXIlrAKLKt1Qlz/roxvyWD0GyKl0a+Sm+\n\t3YMVztgCS5RZwv7wv2qf8rEUYgtQ81qgsbwQTskk=","From":"Chris Packham ","To":"Miquel RAYNAL ,\n\tKalyan Kinthada ","CC":"\"dwmw2@infradead.org\" ,\n\t\"computersforpeace@gmail.com\" ,\n\t\"boris.brezillon@free-electrons.com\"\n\t, \n\t\"marek.vasut@gmail.com\" ,\n\t\"richard@nod.at\" ,\n\t\"cyrille.pitchen@wedev4u.fr\" ,\n\t\"robh+dt@kernel.org\" ,\n\t\"mark.rutland@arm.com\" ,\n\t\"ezequiel.garcia@free-electrons.com\"\n\t, \n\t\"devicetree@vger.kernel.org\" ,\n\t\"linux-mtd@lists.infradead.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ","Subject":"Re: [PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370\n\tvariants.","Thread-Topic":"[PATCH v3 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","Thread-Index":"AQHTN/TV5c3BTkMJ8EyjaCc6GEyjZw==","Date":"Tue, 31 Oct 2017 03:15:01 +0000","Message-ID":"","References":"<20170928005756.3938-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170928005756.3938-2-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20171005094138.11b73a0e@xps13>\n\t\n\t<20171009081848.49681975@xps13>","Accept-Language":"en-NZ, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-ms-exchange-transport-fromentityheader":"Hosted","x-originating-ip":"[2001:df5:b000:22:3a2c:4aff:fe70:2b02]","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]