[{"id":1788703,"web_url":"http://patchwork.ozlabs.org/comment/1788703/","msgid":"<20171017173740.GF5641@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-10-17T17:37:40","subject":"Re: [PATCH V2 0/4] Add Tegra186 PCIe support","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Wed, Sep 27, 2017 at 05:28:33PM +0530, Manikanta Maddireddy wrote:\n> Tegra186 has three PCIe controllers which can be operated\n> in 401, 211 or 111 lane configurations. Tegra TX2 platform\n> has x4 and M.2 Key E PCIe slots, these patches enables\n> x4 slot. BPMP programs UPHY lane0 ownership to USB,\n> so M.2 Key E PCIe will not work.\n> \n> Testing: x4 slot is verified with PCIe based USB3.1 card.\n> PCIe link up, usb flash drive mounting and file copy are\n> verified. These patches are also verified by\n> Mikko Perttunen with an Intel 82574L\n> ethernet card.\n> \n> Patch V2 adds soc->program_uphy check for phy_exit call.\n> \n> Pasting PCIe link up logs below.\n> \n> [ 1.452512] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n> [ 1.452723] tegra-pcie 10003000.pcie: Failed to get supply 'dvdd-pex': -517\n> [ 1.561824] ehci-pci: EHCI PCI platform driver\n> [ 1.591587] ohci-pci: OHCI PCI platform driver\n> [ 3.072464] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n> [ 3.078989] tegra-pcie 10003000.pcie: probing port 0, using 4 lanes\n> [ 3.087272] tegra-pcie 10003000.pcie: Slot present pin change, signature: 00000018\n> [ 3.128818] tegra-pcie 10003000.pcie: PCI host bridge to bus 0000:00\n> [ 3.135174] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\n> [ 3.141352] pci_bus 0000:00: root bus resource [mem 0x50100000-0x57ffffff]\n> [ 3.148221] pci_bus 0000:00: root bus resource [mem 0x58000000-0x7fffffff pref]\n> [ 3.155542] pci_bus 0000:00: root bus resource [bus 00-ff]\n> [ 3.161173] pci 0000:00:01.0: [10de:10e5] type 01 class 0x060400\n> [ 3.161188] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n> [ 3.170838] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n> [ 3.180532] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x52 may corrupt adjacent RW1C bits\n> [ 3.190305] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold\n> [ 3.190312] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4c may corrupt adjacent RW1C bits\n> [ 3.200158] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring\n> [ 3.208158] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n> [ 3.217918] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n> [ 3.227649] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n> [ 3.237382] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x6 may corrupt adjacent RW1C bits\n> [ 3.247135] pci 0000:01:00.0: [1b21:1242] type 00 class 0x0c0330\n> [ 3.247157] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n> [ 3.256807] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n> [ 3.266477] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]\n> [ 3.266544] pci 0000:01:00.0: enabling Extended Tags\n> [ 3.271622] pci 0000:01:00.0: PME# supported from D3hot D3cold\n> [ 3.271775] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01\n> [ 3.271798] pci 0000:00:01.0: BAR 14: assigned [mem 0x50100000-0x501fffff]\n> [ 3.278671] pci 0000:01:00.0: BAR 0: assigned [mem 0x50100000-0x50107fff 64bit]\n> [ 3.285993] pci 0000:00:01.0: PCI bridge to [bus 01]\n> [ 3.290959] pci 0000:00:01.0: bridge window [mem 0x50100000-0x501fffff]\n> [ 3.297763] pci 0000:00:01.0: nv_msi_ht_cap_quirk didn't locate host bridge\n> [ 3.304784] pcieport 0000:00:01.0: enabling device (0000 -> 0002)\n> [ 3.311014] pcieport 0000:00:01.0: Signaling PME with IRQ 57\n> [ 3.316768] pci 0000:01:00.0: enabling device (0000 -> 0002)\n> \n> \n> Manikanta Maddireddy (4):\n> dt-bindings: pci: tegra: Document Tegra186 PCIe DT\n> PCI: tegra: Add Tegra186 PCIe support\n\nI applied these two with Thierry's tested-by and acks to\npci/host-tegra for v4.15, thanks! If you have a changelog update for\nthe pm_domain question, I can fold that in.\n\n> arm64: tegra: Add PCIe node for Tegra186\n> arm64: tegra: Enable PCIe on Jetson TX2\n> \n> .../bindings/pci/nvidia,tegra20-pcie.txt | 134 ++++++++++++++++++++-\n> arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 24 ++++\n> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 82 +++++++++++++\n> drivers/pci/host/pci-tegra.c | 132 ++++++++++++++++----\n> 4 files changed, 344 insertions(+), 28 deletions(-)","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yGj7v3zD4z9t39\n\tfor ;\n\tWed, 18 Oct 2017 04:37:47 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1763569AbdJQRho (ORCPT );\n\tTue, 17 Oct 2017 13:37:44 -0400","from mail.kernel.org ([198.145.29.99]:34250 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1763517AbdJQRhm (ORCPT );\n\tTue, 17 Oct 2017 13:37:42 -0400","from localhost (unknown [69.55.156.165])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 6AB4721868;\n\tTue, 17 Oct 2017 17:37:41 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 6AB4721868","Date":"Tue, 17 Oct 2017 12:37:40 -0500","From":"Bjorn Helgaas ","To":"Manikanta Maddireddy ","Cc":"bhelgaas@google.com, thierry.reding@gmail.com,\n\tjonathanh@nvidia.com, linux-tegra@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, mperttunen@nvidia.com","Subject":"Re: [PATCH V2 0/4] Add Tegra186 PCIe support","Message-ID":"<20171017173740.GF5641@bhelgaas-glaptop.roam.corp.google.com>","References":"<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1788845,"web_url":"http://patchwork.ozlabs.org/comment/1788845/","msgid":"<20171017202814.GC10482@ulmo>","list_archive_url":null,"date":"2017-10-17T20:28:14","subject":"Re: [PATCH V2 0/4] Add Tegra186 PCIe support","submitter":{"id":26234,"url":"http://patchwork.ozlabs.org/api/people/26234/","name":"Thierry Reding","email":"thierry.reding@gmail.com"},"content":"On Tue, Oct 17, 2017 at 12:37:40PM -0500, Bjorn Helgaas wrote:\n> On Wed, Sep 27, 2017 at 05:28:33PM +0530, Manikanta Maddireddy wrote:\n> > Tegra186 has three PCIe controllers which can be operated\n> > in 401, 211 or 111 lane configurations. Tegra TX2 platform\n> > has x4 and M.2 Key E PCIe slots, these patches enables\n> > x4 slot. BPMP programs UPHY lane0 ownership to USB,\n> > so M.2 Key E PCIe will not work.\n> > \n> > Testing: x4 slot is verified with PCIe based USB3.1 card.\n> > PCIe link up, usb flash drive mounting and file copy are\n> > verified. These patches are also verified by\n> > Mikko Perttunen with an Intel 82574L\n> > ethernet card.\n> > \n> > Patch V2 adds soc->program_uphy check for phy_exit call.\n> > \n> > Pasting PCIe link up logs below.\n> > \n> > [ 1.452512] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n> > [ 1.452723] tegra-pcie 10003000.pcie: Failed to get supply 'dvdd-pex': -517\n> > [ 1.561824] ehci-pci: EHCI PCI platform driver\n> > [ 1.591587] ohci-pci: OHCI PCI platform driver\n> > [ 3.072464] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n> > [ 3.078989] tegra-pcie 10003000.pcie: probing port 0, using 4 lanes\n> > [ 3.087272] tegra-pcie 10003000.pcie: Slot present pin change, signature: 00000018\n> > [ 3.128818] tegra-pcie 10003000.pcie: PCI host bridge to bus 0000:00\n> > [ 3.135174] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\n> > [ 3.141352] pci_bus 0000:00: root bus resource [mem 0x50100000-0x57ffffff]\n> > [ 3.148221] pci_bus 0000:00: root bus resource [mem 0x58000000-0x7fffffff pref]\n> > [ 3.155542] pci_bus 0000:00: root bus resource [bus 00-ff]\n> > [ 3.161173] pci 0000:00:01.0: [10de:10e5] type 01 class 0x060400\n> > [ 3.161188] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n> > [ 3.170838] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n> > [ 3.180532] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x52 may corrupt adjacent RW1C bits\n> > [ 3.190305] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold\n> > [ 3.190312] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4c may corrupt adjacent RW1C bits\n> > [ 3.200158] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring\n> > [ 3.208158] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n> > [ 3.217918] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n> > [ 3.227649] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n> > [ 3.237382] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x6 may corrupt adjacent RW1C bits\n> > [ 3.247135] pci 0000:01:00.0: [1b21:1242] type 00 class 0x0c0330\n> > [ 3.247157] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n> > [ 3.256807] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n> > [ 3.266477] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]\n> > [ 3.266544] pci 0000:01:00.0: enabling Extended Tags\n> > [ 3.271622] pci 0000:01:00.0: PME# supported from D3hot D3cold\n> > [ 3.271775] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01\n> > [ 3.271798] pci 0000:00:01.0: BAR 14: assigned [mem 0x50100000-0x501fffff]\n> > [ 3.278671] pci 0000:01:00.0: BAR 0: assigned [mem 0x50100000-0x50107fff 64bit]\n> > [ 3.285993] pci 0000:00:01.0: PCI bridge to [bus 01]\n> > [ 3.290959] pci 0000:00:01.0: bridge window [mem 0x50100000-0x501fffff]\n> > [ 3.297763] pci 0000:00:01.0: nv_msi_ht_cap_quirk didn't locate host bridge\n> > [ 3.304784] pcieport 0000:00:01.0: enabling device (0000 -> 0002)\n> > [ 3.311014] pcieport 0000:00:01.0: Signaling PME with IRQ 57\n> > [ 3.316768] pci 0000:01:00.0: enabling device (0000 -> 0002)\n> > \n> > \n> > Manikanta Maddireddy (4):\n> > dt-bindings: pci: tegra: Document Tegra186 PCIe DT\n> > PCI: tegra: Add Tegra186 PCIe support\n> \n> I applied these two with Thierry's tested-by and acks to\n> pci/host-tegra for v4.15, thanks! If you have a changelog update for\n> the pm_domain question, I can fold that in.\n\nThanks!\n\nThierry","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"efD2fGPV\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yGmwj43n8z9t38\n\tfor ;\n\tWed, 18 Oct 2017 07:28:21 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1764266AbdJQU2T (ORCPT );\n\tTue, 17 Oct 2017 16:28:19 -0400","from mail-qk0-f170.google.com ([209.85.220.170]:56724 \"EHLO\n\tmail-qk0-f170.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1760471AbdJQU2S (ORCPT\n\t); Tue, 17 Oct 2017 16:28:18 -0400","by mail-qk0-f170.google.com with SMTP id l194so3690298qke.13;\n\tTue, 17 Oct 2017 13:28:18 -0700 (PDT)","from localhost\n\t(p200300E41BE4FD00CEAD5B94E1CFD280.dip0.t-ipconnect.de.\n\t[2003:e4:1be4:fd00:cead:5b94:e1cf:d280])\n\tby smtp.gmail.com with ESMTPSA id\n\tc64sm6473448qkd.70.2017.10.17.13.28.16\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 17 Oct 2017 13:28:16 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=date:from:to:cc:subject:message-id:references:mime-version\n\t:content-disposition:in-reply-to:user-agent;\n\tbh=BYh78NqlBVTTmSnB4x1QnluOAiNGCDkxIjf3/kFZTW4=;\n\tb=efD2fGPVkshq/wNlNHEhjhxLjxT25rxl3kopZ+9SuO453C71u358VIcQQ+2kBFm46o\n\tM1BJ5tifEIts5N5gFCn0sWnWYpwfMVwPEInbPnoF6pcbxDfqnainYAlvUwz4bzTprwlj\n\tg6C7UQFQpK6H58MzQXjmpumyYo8t2X7gHcYbQxO2caYQYd/+ayr3ISXfCLHJ/7X3vFuZ\n\t36XIrE/W3KGjv1PgmONG/syze+dpWVmVKo7Oi1WMtitHOFcWRl1td84jrJmmolYzS+9c\n\t3NzPuUVoHR4KR0pn8LyZtw7BJ0uVvf+T2ub1XIc4DCa4uXP+8eGyfWf4wlFx8Snusq1k\n\tVbUA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=BYh78NqlBVTTmSnB4x1QnluOAiNGCDkxIjf3/kFZTW4=;\n\tb=A3+fhEAdn0oELLv1yvG737jMxLbixTBZfO8M6LCRssu6/i7qKmNjEK0+9Au+yunOu9\n\tqtVC7LjFgc4S2pbLDOIzOLV/m5dLbCVHeHOLtlBHt7TB1/E77Z6fj+fHVWaufKGcSnSR\n\tIgztnxlmlq/2BmlP7EXKNqO+m4685A2doxdU2R8SwF5RFUHj1aEL/Ji9/Kso2xk1aJdu\n\t/OerQdF4IzTyRKoiDlwu/sQmJXjS8/XzXrE1uABTyaBuhkfJ1uSPA1O6n2NrVC+42GAs\n\trB33pM7h0TSK7sBY57LQpODJXWe8I8WoRdBTmYDvsHrlFIszHuA3VOPIdwKBFv4mNv9k\n\tym/Q==","X-Gm-Message-State":"AMCzsaWCLNsxOYhemwjsGw7UneMlKS2YCh3TTd3Rnh8OqvLuhYVD4Bi9\n\tz3V4T0fOjtmFVCDZG3AfdrE=","X-Google-Smtp-Source":"ABhQp+TigcZAhyb+HuKx6NYWETFT82WzgIV7GeTM9Unv0bCeKXANy0xKQlAlAdPUv1eawlGo/3DqUA==","X-Received":"by 10.55.148.70 with SMTP id w67mr12224869qkd.102.1508272097429; \n\tTue, 17 Oct 2017 13:28:17 -0700 (PDT)","Date":"Tue, 17 Oct 2017 22:28:14 +0200","From":"Thierry Reding ","To":"Bjorn Helgaas ","Cc":"Manikanta Maddireddy , bhelgaas@google.com,\n\tjonathanh@nvidia.com, linux-tegra@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, mperttunen@nvidia.com","Subject":"Re: [PATCH V2 0/4] Add Tegra186 PCIe support","Message-ID":"<20171017202814.GC10482@ulmo>","References":"<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>\n\t<20171017173740.GF5641@bhelgaas-glaptop.roam.corp.google.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha256;\n\tprotocol=\"application/pgp-signature\"; boundary=\"/Uq4LBwYP4y1W6pO\"","Content-Disposition":"inline","In-Reply-To":"<20171017173740.GF5641@bhelgaas-glaptop.roam.corp.google.com>","User-Agent":"Mutt/1.9.1 (2017-09-22)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}},{"id":1789134,"web_url":"http://patchwork.ozlabs.org/comment/1789134/","msgid":"","list_archive_url":null,"date":"2017-10-18T05:07:30","subject":"Re: [PATCH V2 0/4] Add Tegra186 PCIe support","submitter":{"id":72399,"url":"http://patchwork.ozlabs.org/api/people/72399/","name":"Manikanta Maddireddy","email":"mmaddireddy@nvidia.com"},"content":"On 18-Oct-17 1:58 AM, Thierry Reding wrote:\n> On Tue, Oct 17, 2017 at 12:37:40PM -0500, Bjorn Helgaas wrote:\n>> On Wed, Sep 27, 2017 at 05:28:33PM +0530, Manikanta Maddireddy wrote:\n>>> Tegra186 has three PCIe controllers which can be operated\n>>> in 401, 211 or 111 lane configurations. Tegra TX2 platform\n>>> has x4 and M.2 Key E PCIe slots, these patches enables\n>>> x4 slot. BPMP programs UPHY lane0 ownership to USB,\n>>> so M.2 Key E PCIe will not work.\n>>>\n>>> Testing: x4 slot is verified with PCIe based USB3.1 card.\n>>> PCIe link up, usb flash drive mounting and file copy are\n>>> verified. These patches are also verified by\n>>> Mikko Perttunen with an Intel 82574L\n>>> ethernet card.\n>>>\n>>> Patch V2 adds soc->program_uphy check for phy_exit call.\n>>>\n>>> Pasting PCIe link up logs below.\n>>>\n>>> [ 1.452512] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n>>> [ 1.452723] tegra-pcie 10003000.pcie: Failed to get supply 'dvdd-pex': -517\n>>> [ 1.561824] ehci-pci: EHCI PCI platform driver\n>>> [ 1.591587] ohci-pci: OHCI PCI platform driver\n>>> [ 3.072464] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n>>> [ 3.078989] tegra-pcie 10003000.pcie: probing port 0, using 4 lanes\n>>> [ 3.087272] tegra-pcie 10003000.pcie: Slot present pin change, signature: 00000018\n>>> [ 3.128818] tegra-pcie 10003000.pcie: PCI host bridge to bus 0000:00\n>>> [ 3.135174] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\n>>> [ 3.141352] pci_bus 0000:00: root bus resource [mem 0x50100000-0x57ffffff]\n>>> [ 3.148221] pci_bus 0000:00: root bus resource [mem 0x58000000-0x7fffffff pref]\n>>> [ 3.155542] pci_bus 0000:00: root bus resource [bus 00-ff]\n>>> [ 3.161173] pci 0000:00:01.0: [10de:10e5] type 01 class 0x060400\n>>> [ 3.161188] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n>>> [ 3.170838] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n>>> [ 3.180532] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x52 may corrupt adjacent RW1C bits\n>>> [ 3.190305] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold\n>>> [ 3.190312] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4c may corrupt adjacent RW1C bits\n>>> [ 3.200158] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring\n>>> [ 3.208158] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n>>> [ 3.217918] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n>>> [ 3.227649] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n>>> [ 3.237382] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x6 may corrupt adjacent RW1C bits\n>>> [ 3.247135] pci 0000:01:00.0: [1b21:1242] type 00 class 0x0c0330\n>>> [ 3.247157] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n>>> [ 3.256807] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n>>> [ 3.266477] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]\n>>> [ 3.266544] pci 0000:01:00.0: enabling Extended Tags\n>>> [ 3.271622] pci 0000:01:00.0: PME# supported from D3hot D3cold\n>>> [ 3.271775] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01\n>>> [ 3.271798] pci 0000:00:01.0: BAR 14: assigned [mem 0x50100000-0x501fffff]\n>>> [ 3.278671] pci 0000:01:00.0: BAR 0: assigned [mem 0x50100000-0x50107fff 64bit]\n>>> [ 3.285993] pci 0000:00:01.0: PCI bridge to [bus 01]\n>>> [ 3.290959] pci 0000:00:01.0: bridge window [mem 0x50100000-0x501fffff]\n>>> [ 3.297763] pci 0000:00:01.0: nv_msi_ht_cap_quirk didn't locate host bridge\n>>> [ 3.304784] pcieport 0000:00:01.0: enabling device (0000 -> 0002)\n>>> [ 3.311014] pcieport 0000:00:01.0: Signaling PME with IRQ 57\n>>> [ 3.316768] pci 0000:01:00.0: enabling device (0000 -> 0002)\n>>>\n>>>\n>>> Manikanta Maddireddy (4):\n>>> dt-bindings: pci: tegra: Document Tegra186 PCIe DT\n>>> PCI: tegra: Add Tegra186 PCIe support\n>>\n>> I applied these two with Thierry's tested-by and acks to\n>> pci/host-tegra for v4.15, thanks! If you have a changelog update for\n>> the pm_domain question, I can fold that in.\n> \n> Thanks!\n> \n> Thierry\n> \n\nThank you Mikko, Thierry and Bjorn for testing and reviewing these patches.\n\nBjorn,\n\nPlease let me know if Thierry's elaborate changelog update in [PATCH V2 2/4] clarified the pm_domain question or not?\nIf that helps, please take that into changelog.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yH0TC2shKz9t39\n\tfor ;\n\tWed, 18 Oct 2017 16:08:47 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S933086AbdJRFIp (ORCPT );\n\tWed, 18 Oct 2017 01:08:45 -0400","from hqemgate14.nvidia.com ([216.228.121.143]:18210 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1757344AbdJRFIo (ORCPT\n\t); Wed, 18 Oct 2017 01:08:44 -0400","from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com\n\tid ; Tue, 17 Oct 2017 22:07:57 -0700","from HQMAIL107.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tTue, 17 Oct 2017 22:08:16 -0700","from BGMAIL102.nvidia.com (10.25.59.11) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 18 Oct 2017 05:07:40 +0000","from [10.24.71.190] (10.24.71.190) by bgmail102.nvidia.com\n\t(10.25.59.11) with Microsoft SMTP Server (TLS) id 15.0.1293.2;\n\tWed, 18 Oct 2017 05:07:36 +0000"],"X-PGP-Universal":"processed;\n\tby hqpgpgate102.nvidia.com on Tue, 17 Oct 2017 22:08:16 -0700","Subject":"Re: [PATCH V2 0/4] Add Tegra186 PCIe support","To":"Thierry Reding ,\n\tBjorn Helgaas ","CC":", ,\n\t, ,\n\t","References":"<1506513517-25870-1-git-send-email-mmaddireddy@nvidia.com>\n\t<20171017173740.GF5641@bhelgaas-glaptop.roam.corp.google.com>\n\t<20171017202814.GC10482@ulmo>","From":"Manikanta Maddireddy ","X-Nvconfidentiality":"public","Message-ID":"","Date":"Wed, 18 Oct 2017 10:37:30 +0530","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"<20171017202814.GC10482@ulmo>","X-Originating-IP":"[10.24.71.190]","X-ClientProxiedBy":"BGMAIL104.nvidia.com (10.25.59.13) To bgmail102.nvidia.com\n\t(10.25.59.11)","Content-Type":"text/plain; charset=\"windows-1252\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]