[{"id":1778859,"web_url":"http://patchwork.ozlabs.org/comment/1778859/","msgid":"<3ebe9c45-f338-87ef-1513-7255124902b1@intel.com>","list_archive_url":null,"date":"2017-10-03T11:44:23","subject":"Re: [PATCH v2 1/4] mmc: sdhci-msm: fix issue with power irq","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 27/09/17 08:34, Vijay Viswanath wrote:\n> From: Subhash Jadavani \n> \n> SDCC controller reset (SW_RST) during probe may trigger power irq if\n> previous status of PWRCTL was either BUS_ON or IO_HIGH_V. So before we\n> enable the power irq interrupt in GIC (by registering the interrupt\n> handler), we need to ensure that any pending power irq interrupt status\n> is acknowledged otherwise power irq interrupt handler would be fired\n> prematurely.\n> \n> Signed-off-by: Subhash Jadavani \n> Signed-off-by: Vijay Viswanath \n\nI already acked v1, nevertheless:\n\nAcked-by: Adrian Hunter \n\n> ---\n> drivers/mmc/host/sdhci-msm.c | 18 ++++++++++++++++++\n> 1 file changed, 18 insertions(+)\n> \n> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> index 9d601dc..d636251 100644\n> --- a/drivers/mmc/host/sdhci-msm.c\n> +++ b/drivers/mmc/host/sdhci-msm.c\n> @@ -1250,6 +1250,21 @@ static int sdhci_msm_probe(struct platform_device *pdev)\n> \t\t\t CORE_VENDOR_SPEC_CAPABILITIES0);\n> \t}\n> \n> +\t/*\n> +\t * Power on reset state may trigger power irq if previous status of\n> +\t * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq\n> +\t * interrupt in GIC, any pending power irq interrupt should be\n> +\t * acknowledged. Otherwise power irq interrupt handler would be\n> +\t * fired prematurely.\n> +\t */\n> +\tsdhci_msm_voltage_switch(host);\n> +\n> +\t/*\n> +\t * Ensure that above writes are propogated before interrupt enablement\n> +\t * in GIC.\n> +\t */\n> +\tmb();\n> +\n> \t/* Setup IRQ for handling power/voltage tasks with PMIC */\n> \tmsm_host->pwr_irq = platform_get_irq_byname(pdev, \"pwr_irq\");\n> \tif (msm_host->pwr_irq < 0) {\n> @@ -1259,6 +1274,9 @@ static int sdhci_msm_probe(struct platform_device *pdev)\n> \t\tgoto clk_disable;\n> \t}\n> \n> +\t/* Enable pwr irq interrupts */\n> +\twritel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);\n> +\n> \tret = devm_request_threaded_irq(&pdev->dev, msm_host->pwr_irq, NULL,\n> \t\t\t\t\tsdhci_msm_pwr_irq, IRQF_ONESHOT,\n> \t\t\t\t\tdev_name(&pdev->dev), host);\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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d=\"scan'208\";a=\"906207578\"","Subject":"Re: [PATCH v2 1/4] mmc: sdhci-msm: fix issue with power irq","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1506490483-46871-1-git-send-email-vviswana@codeaurora.org>\n\t<1506490483-46871-2-git-send-email-vviswana@codeaurora.org>","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"<3ebe9c45-f338-87ef-1513-7255124902b1@intel.com>","Date":"Tue, 3 Oct 2017 14:44:23 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506490483-46871-2-git-send-email-vviswana@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171003_045131_972330_7F794597 ","X-CRM114-Status":"GOOD ( 12.77 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.134.136.100 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778861,"web_url":"http://patchwork.ozlabs.org/comment/1778861/","msgid":"<12eeb19a-e9eb-731c-4918-64a0bfb7ceb5@intel.com>","list_archive_url":null,"date":"2017-10-03T11:44:28","subject":"Re: [PATCH v2 2/4] mmc: sdhci-msm: Fix HW issue with power IRQ\n\thandling during reset","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 27/09/17 08:34, Vijay Viswanath wrote:\n> From: Sahitya Tummala \n> \n> There is a rare scenario in HW, where the first clear pulse could\n> be lost when the actual reset and clear/read of status register\n> are happening at the same time. Fix this by retrying upto 10 times\n> to ensure the status register gets cleared. Otherwise, this will\n> lead to a spurious power IRQ which results in system instability.\n> \n> Signed-off-by: Sahitya Tummala \n> Signed-off-by: Vijay Viswanath \n\nI already acked v1, nevertheless:\n\nAcked-by: Adrian Hunter \n\n> ---\n> drivers/mmc/host/sdhci-msm.c | 46 ++++++++++++++++++++++++++++++++++++++++----\n> 1 file changed, 42 insertions(+), 4 deletions(-)\n> \n> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> index d636251..42a65ab 100644\n> --- a/drivers/mmc/host/sdhci-msm.c\n> +++ b/drivers/mmc/host/sdhci-msm.c\n> @@ -995,17 +995,52 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,\n> \t\tsdhci_msm_hs400(host, &mmc->ios);\n> }\n> \n> -static void sdhci_msm_voltage_switch(struct sdhci_host *host)\n> +static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)\n> +{\n> +\tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> +\tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> +\n> +\tpr_err(\"%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\\n\",\n> +\t\t\tmmc_hostname(host->mmc),\n> +\t\t\treadl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS),\n> +\t\t\treadl_relaxed(msm_host->core_mem + CORE_PWRCTL_MASK),\n> +\t\t\treadl_relaxed(msm_host->core_mem + CORE_PWRCTL_CTL));\n> +}\n> +\n> +static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> {\n> \tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> \tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> \tu32 irq_status, irq_ack = 0;\n> +\tint retry = 10;\n> \n> \tirq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);\n> \tirq_status &= INT_MASK;\n> \n> \twritel_relaxed(irq_status, msm_host->core_mem + CORE_PWRCTL_CLEAR);\n> \n> +\t/*\n> +\t * There is a rare HW scenario where the first clear pulse could be\n> +\t * lost when actual reset and clear/read of status register is\n> +\t * happening at a time. Hence, retry for at least 10 times to make\n> +\t * sure status register is cleared. Otherwise, this will result in\n> +\t * a spurious power IRQ resulting in system instability.\n> +\t */\n> +\twhile (irq_status & readl_relaxed(msm_host->core_mem +\n> +\t\t\t\tCORE_PWRCTL_STATUS)) {\n> +\t\tif (retry == 0) {\n> +\t\t\tpr_err(\"%s: Timedout clearing (0x%x) pwrctl status register\\n\",\n> +\t\t\t\t\tmmc_hostname(host->mmc), irq_status);\n> +\t\t\tsdhci_msm_dump_pwr_ctrl_regs(host);\n> +\t\t\tWARN_ON(1);\n> +\t\t\tbreak;\n> +\t\t}\n> +\t\twritel_relaxed(irq_status,\n> +\t\t\t\tmsm_host->core_mem + CORE_PWRCTL_CLEAR);\n> +\t\tretry--;\n> +\t\tudelay(10);\n> +\t}\n> +\n> \tif (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))\n> \t\tirq_ack |= CORE_PWRCTL_BUS_SUCCESS;\n> \tif (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))\n> @@ -1017,13 +1052,17 @@ static void sdhci_msm_voltage_switch(struct sdhci_host *host)\n> \t * switches are handled by the sdhci core, so just report success.\n> \t */\n> \twritel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);\n> +\n> +\tpr_debug(\"%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\\n\",\n> +\t\tmmc_hostname(msm_host->mmc), __func__, irq, irq_status,\n> +\t\tirq_ack);\n> }\n> \n> static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)\n> {\n> \tstruct sdhci_host *host = (struct sdhci_host *)data;\n> \n> -\tsdhci_msm_voltage_switch(host);\n> +\tsdhci_msm_handle_pwr_irq(host, irq);\n> \n> \treturn IRQ_HANDLED;\n> }\n> @@ -1106,7 +1145,6 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)\n> \t.get_max_clock = sdhci_msm_get_max_clock,\n> \t.set_bus_width = sdhci_set_bus_width,\n> \t.set_uhs_signaling = sdhci_msm_set_uhs_signaling,\n> -\t.voltage_switch = sdhci_msm_voltage_switch,\n> };\n> \n> static const struct sdhci_pltfm_data sdhci_msm_pdata = {\n> @@ -1257,7 +1295,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)\n> \t * acknowledged. Otherwise power irq interrupt handler would be\n> \t * fired prematurely.\n> \t */\n> -\tsdhci_msm_voltage_switch(host);\n> +\tsdhci_msm_handle_pwr_irq(host, 0);\n> \n> \t/*\n> \t * Ensure that above writes are propogated before interrupt enablement\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"RN7tp2fg\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y5y7N3kv8z9t2Z\n\tfor ;\n\tTue, 3 Oct 2017 22:52:00 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dzLjt-0007xB-Bg; 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d=\"scan'208\";a=\"906207586\"","Subject":"Re: [PATCH v2 2/4] mmc: sdhci-msm: Fix HW issue with power IRQ\n\thandling during reset","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1506490483-46871-1-git-send-email-vviswana@codeaurora.org>\n\t<1506490483-46871-3-git-send-email-vviswana@codeaurora.org>","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"<12eeb19a-e9eb-731c-4918-64a0bfb7ceb5@intel.com>","Date":"Tue, 3 Oct 2017 14:44:28 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506490483-46871-3-git-send-email-vviswana@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171003_045132_324195_69DD33EA ","X-CRM114-Status":"GOOD ( 20.14 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [134.134.136.100 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778862,"web_url":"http://patchwork.ozlabs.org/comment/1778862/","msgid":"<8952698b-62d1-33fc-e9ed-50b9ad87c52a@intel.com>","list_archive_url":null,"date":"2017-10-03T11:44:38","subject":"Re: [PATCH v2 4/4] mmc: sdhci-msm: Add sdhci msm register write APIs\n\twhich wait for pwr irq","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 27/09/17 08:34, Vijay Viswanath wrote:\n> Register writes which change voltage of IO lines or turn the IO bus\n> on/off require controller to be ready before progressing further. When\n> the controller is ready, it will generate a power irq which needs to be\n> handled. The thread which initiated the register write should wait for\n> power irq to complete. This will be done through the new sdhc msm write\n> APIs which will check whether the particular write can trigger a power\n> irq and wait for it with a timeout if it is expected.\n> The SDHC core power control IRQ gets triggered when -\n> * There is a state change in power control bit (bit 0)\n> of SDHCI_POWER_CONTROL register.\n> * There is a state change in 1.8V enable bit (bit 3) of\n> SDHCI_HOST_CONTROL2 register.\n> * Bit 1 of SDHCI_SOFTWARE_RESET is set.\n> \n> Also add support APIs which are used by sdhc msm write APIs to check\n> if power irq is expected to be generated and wait for the power irq\n> to come and complete if the irq is expected.\n> \n> This patch requires CONFIG_MMC_SDHCI_IO_ACCESSORS to be enabled.\n> \n> Signed-off-by: Sahitya Tummala \n> Signed-off-by: Vijay Viswanath \n\nAcked-by: Adrian Hunter \n\n> ---\n> drivers/mmc/host/sdhci-msm.c | 173 ++++++++++++++++++++++++++++++++++++++++++-\n> 1 file changed, 171 insertions(+), 2 deletions(-)\n> \n> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> index 42a65ab..b72a487 100644\n> --- a/drivers/mmc/host/sdhci-msm.c\n> +++ b/drivers/mmc/host/sdhci-msm.c\n> @@ -123,6 +123,10 @@\n> #define CMUX_SHIFT_PHASE_MASK\t(7 << CMUX_SHIFT_PHASE_SHIFT)\n> \n> #define MSM_MMC_AUTOSUSPEND_DELAY_MS\t50\n> +\n> +/* Timeout value to avoid infinite waiting for pwr_irq */\n> +#define MSM_PWR_IRQ_TIMEOUT_MS 5000\n> +\n> struct sdhci_msm_host {\n> \tstruct platform_device *pdev;\n> \tvoid __iomem *core_mem;\t/* MSM SDCC mapped address */\n> @@ -138,6 +142,10 @@ struct sdhci_msm_host {\n> \tbool calibration_done;\n> \tu8 saved_tuning_phase;\n> \tbool use_cdclp533;\n> +\tu32 curr_pwr_state;\n> +\tu32 curr_io_level;\n> +\twait_queue_head_t pwr_irq_wait;\n> +\tbool pwr_irq_flag;\n> };\n> \n> static unsigned int msm_get_clock_rate_for_bus_mode(struct sdhci_host *host,\n> @@ -995,6 +1003,73 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,\n> \t\tsdhci_msm_hs400(host, &mmc->ios);\n> }\n> \n> +static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host)\n> +{\n> +\tinit_waitqueue_head(&msm_host->pwr_irq_wait);\n> +}\n> +\n> +static inline void sdhci_msm_complete_pwr_irq_wait(\n> +\t\tstruct sdhci_msm_host *msm_host)\n> +{\n> +\twake_up(&msm_host->pwr_irq_wait);\n> +}\n> +\n> +/*\n> + * sdhci_msm_check_power_status API should be called when registers writes\n> + * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.\n> + * To what state the register writes will change the IO lines should be passed\n> + * as the argument req_type. This API will check whether the IO line's state\n> + * is already the expected state and will wait for power irq only if\n> + * power irq is expected to be trigerred based on the current IO line state\n> + * and expected IO line state.\n> + */\n> +static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)\n> +{\n> +\tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> +\tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> +\tbool done = false;\n> +\n> +\tpr_debug(\"%s: %s: request %d curr_pwr_state %x curr_io_level %x\\n\",\n> +\t\t\tmmc_hostname(host->mmc), __func__, req_type,\n> +\t\t\tmsm_host->curr_pwr_state, msm_host->curr_io_level);\n> +\n> +\t/*\n> +\t * The IRQ for request type IO High/LOW will be generated when -\n> +\t * there is a state change in 1.8V enable bit (bit 3) of\n> +\t * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0\n> +\t * which indicates 3.3V IO voltage. So, when MMC core layer tries\n> +\t * to set it to 3.3V before card detection happens, the\n> +\t * IRQ doesn't get triggered as there is no state change in this bit.\n> +\t * The driver already handles this case by changing the IO voltage\n> +\t * level to high as part of controller power up sequence. Hence, check\n> +\t * for host->pwr to handle a case where IO voltage high request is\n> +\t * issued even before controller power up.\n> +\t */\n> +\tif ((req_type & REQ_IO_HIGH) && !host->pwr) {\n> +\t\tpr_debug(\"%s: do not wait for power IRQ that never comes, req_type: %d\\n\",\n> +\t\t\t\tmmc_hostname(host->mmc), req_type);\n> +\t\treturn;\n> +\t}\n> +\tif ((req_type & msm_host->curr_pwr_state) ||\n> +\t\t\t(req_type & msm_host->curr_io_level))\n> +\t\tdone = true;\n> +\t/*\n> +\t * This is needed here to handle cases where register writes will\n> +\t * not change the current bus state or io level of the controller.\n> +\t * In this case, no power irq will be triggerred and we should\n> +\t * not wait.\n> +\t */\n> +\tif (!done) {\n> +\t\tif (!wait_event_timeout(msm_host->pwr_irq_wait,\n> +\t\t\t\tmsm_host->pwr_irq_flag,\n> +\t\t\t\tmsecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))\n> +\t\t\t__WARN_printf(\"%s: pwr_irq for req: (%d) timed out\\n\",\n> +\t\t\t\t\tmmc_hostname(host->mmc), req_type);\n> +\t}\n> +\tpr_debug(\"%s: %s: request %d done\\n\", mmc_hostname(host->mmc),\n> +\t\t\t__func__, req_type);\n> +}\n> +\n> static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host *host)\n> {\n> \tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> @@ -1013,6 +1088,8 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> \tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> \tu32 irq_status, irq_ack = 0;\n> \tint retry = 10;\n> +\tint pwr_state = 0, io_level = 0;\n> +\n> \n> \tirq_status = readl_relaxed(msm_host->core_mem + CORE_PWRCTL_STATUS);\n> \tirq_status &= INT_MASK;\n> @@ -1041,10 +1118,26 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> \t\tudelay(10);\n> \t}\n> \n> -\tif (irq_status & (CORE_PWRCTL_BUS_ON | CORE_PWRCTL_BUS_OFF))\n> +\t/* Handle BUS ON/OFF*/\n> +\tif (irq_status & CORE_PWRCTL_BUS_ON) {\n> +\t\tpwr_state = REQ_BUS_ON;\n> +\t\tio_level = REQ_IO_HIGH;\n> +\t\tirq_ack |= CORE_PWRCTL_BUS_SUCCESS;\n> +\t}\n> +\tif (irq_status & CORE_PWRCTL_BUS_OFF) {\n> +\t\tpwr_state = REQ_BUS_OFF;\n> +\t\tio_level = REQ_IO_LOW;\n> \t\tirq_ack |= CORE_PWRCTL_BUS_SUCCESS;\n> -\tif (irq_status & (CORE_PWRCTL_IO_LOW | CORE_PWRCTL_IO_HIGH))\n> +\t}\n> +\t/* Handle IO LOW/HIGH */\n> +\tif (irq_status & CORE_PWRCTL_IO_LOW) {\n> +\t\tio_level = REQ_IO_LOW;\n> \t\tirq_ack |= CORE_PWRCTL_IO_SUCCESS;\n> +\t}\n> +\tif (irq_status & CORE_PWRCTL_IO_HIGH) {\n> +\t\tio_level = REQ_IO_HIGH;\n> +\t\tirq_ack |= CORE_PWRCTL_IO_SUCCESS;\n> +\t}\n> \n> \t/*\n> \t * The driver has to acknowledge the interrupt, switch voltages and\n> @@ -1053,6 +1146,11 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> \t */\n> \twritel_relaxed(irq_ack, msm_host->core_mem + CORE_PWRCTL_CTL);\n> \n> +\tif (pwr_state)\n> +\t\tmsm_host->curr_pwr_state = pwr_state;\n> +\tif (io_level)\n> +\t\tmsm_host->curr_io_level = io_level;\n> +\n> \tpr_debug(\"%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\\n\",\n> \t\tmmc_hostname(msm_host->mmc), __func__, irq, irq_status,\n> \t\tirq_ack);\n> @@ -1061,8 +1159,13 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq)\n> static irqreturn_t sdhci_msm_pwr_irq(int irq, void *data)\n> {\n> \tstruct sdhci_host *host = (struct sdhci_host *)data;\n> +\tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> +\tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> \n> \tsdhci_msm_handle_pwr_irq(host, irq);\n> +\tmsm_host->pwr_irq_flag = 1;\n> +\tsdhci_msm_complete_pwr_irq_wait(msm_host);\n> +\n> \n> \treturn IRQ_HANDLED;\n> }\n> @@ -1131,6 +1234,69 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)\n> \t__sdhci_msm_set_clock(host, clock);\n> }\n> \n> +/*\n> + * Platform specific register write functions. This is so that, if any\n> + * register write needs to be followed up by platform specific actions,\n> + * they can be added here. These functions can go to sleep when writes\n> + * to certain registers are done.\n> + * These functions are relying on sdhci_set_ios not using spinlock.\n> + */\n> +static int __sdhci_msm_check_write(struct sdhci_host *host, u16 val, int reg)\n> +{\n> +\tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n> +\tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n> +\tu32 req_type = 0;\n> +\n> +\tswitch (reg) {\n> +\tcase SDHCI_HOST_CONTROL2:\n> +\t\treq_type = (val & SDHCI_CTRL_VDD_180) ? REQ_IO_LOW :\n> +\t\t\tREQ_IO_HIGH;\n> +\t\tbreak;\n> +\tcase SDHCI_SOFTWARE_RESET:\n> +\t\tif (host->pwr && (val & SDHCI_RESET_ALL))\n> +\t\t\treq_type = REQ_BUS_OFF;\n> +\t\tbreak;\n> +\tcase SDHCI_POWER_CONTROL:\n> +\t\treq_type = !val ? REQ_BUS_OFF : REQ_BUS_ON;\n> +\t\tbreak;\n> +\t}\n> +\n> +\tif (req_type) {\n> +\t\tmsm_host->pwr_irq_flag = 0;\n> +\t\t/*\n> +\t\t * Since this register write may trigger a power irq, ensure\n> +\t\t * all previous register writes are complete by this point.\n> +\t\t */\n> +\t\tmb();\n> +\t}\n> +\treturn req_type;\n> +}\n> +\n> +/* This function may sleep*/\n> +static void sdhci_msm_writew(struct sdhci_host *host, u16 val, int reg)\n> +{\n> +\tu32 req_type = 0;\n> +\n> +\treq_type = __sdhci_msm_check_write(host, val, reg);\n> +\twritew_relaxed(val, host->ioaddr + reg);\n> +\n> +\tif (req_type)\n> +\t\tsdhci_msm_check_power_status(host, req_type);\n> +}\n> +\n> +/* This function may sleep*/\n> +static void sdhci_msm_writeb(struct sdhci_host *host, u8 val, int reg)\n> +{\n> +\tu32 req_type = 0;\n> +\n> +\treq_type = __sdhci_msm_check_write(host, val, reg);\n> +\n> +\twriteb_relaxed(val, host->ioaddr + reg);\n> +\n> +\tif (req_type)\n> +\t\tsdhci_msm_check_power_status(host, req_type);\n> +}\n> +\n> static const struct of_device_id sdhci_msm_dt_match[] = {\n> \t{ .compatible = \"qcom,sdhci-msm-v4\" },\n> \t{},\n> @@ -1145,6 +1311,8 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)\n> \t.get_max_clock = sdhci_msm_get_max_clock,\n> \t.set_bus_width = sdhci_set_bus_width,\n> \t.set_uhs_signaling = sdhci_msm_set_uhs_signaling,\n> +\t.write_w = sdhci_msm_writew,\n> +\t.write_b = sdhci_msm_writeb,\n> };\n> \n> static const struct sdhci_pltfm_data sdhci_msm_pdata = {\n> @@ -1312,6 +1480,7 @@ static int sdhci_msm_probe(struct platform_device *pdev)\n> \t\tgoto clk_disable;\n> \t}\n> \n> +\tsdhci_msm_init_pwr_irq_wait(msm_host);\n> \t/* Enable pwr irq interrupts */\n> \twritel_relaxed(INT_MASK, msm_host->core_mem + CORE_PWRCTL_MASK);\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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03 Oct 2017 04:51:22 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:\n\tMessage-ID:From:References:To:Subject:Reply-To:Content-ID:Content-Description\n\t:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=Jx6ns5QxDFjTMwpVPvrw3sCEed6ZqbRXw0AatZZUTe8=;\n\tb=q8GVwQ/JjBJLTl\n\tH0iJYGWuOBWspeiaC6RW7XQO9RKTzvtIjDgiLjkCGKy4bGa6x19mYuJ6G+Kemm6go2ZXJPfKymc2l\n\tt1ckPSAiVFTKQouAc/44Wi0c4k5/MIwfvU4n0hyaFNC44Lxpi6tZ3X8ao33EYdq9h2Hs1z0Z3Ohid\n\tx6ZkqEHCBeb94+tpaj/yfbinz6dDDZHazgdLVlIm75/lhP/cpFwmA/agUIntect6CKF9uhCsnmfdW\n\tib53RC++n9wDmP6CFYjg1zIKRDyKkFDnWgpKyawVcQQ6K3rd6KhSs9etNiiIEvxDRz319Nm66Z8Uf\n\tft9DiMa+6PG+pJJHIpzg==;","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,474,1500966000\"; d=\"scan'208\";a=\"906207636\"","Subject":"Re: [PATCH v2 4/4] mmc: sdhci-msm: Add sdhci msm register write APIs\n\twhich wait for pwr irq","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1506490483-46871-1-git-send-email-vviswana@codeaurora.org>\n\t<1506490483-46871-5-git-send-email-vviswana@codeaurora.org>","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"<8952698b-62d1-33fc-e9ed-50b9ad87c52a@intel.com>","Date":"Tue, 3 Oct 2017 14:44:38 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506490483-46871-5-git-send-email-vviswana@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171003_045143_253579_02256B4E ","X-CRM114-Status":"GOOD ( 31.16 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [192.55.52.120 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778866,"web_url":"http://patchwork.ozlabs.org/comment/1778866/","msgid":"<35266316-e199-30a7-dc7d-bb31f173e018@intel.com>","list_archive_url":null,"date":"2017-10-03T11:44:34","subject":"Re: [PATCH v2 3/4] mmc: Kconfig: Enable\n\tCONFIG_MMC_SDHCI_IO_ACCESSORS","submitter":{"id":11091,"url":"http://patchwork.ozlabs.org/api/people/11091/","name":"Adrian Hunter","email":"adrian.hunter@intel.com"},"content":"On 27/09/17 08:34, Vijay Viswanath wrote:\n> Enable CONFIG_MMC_SDHCI_IO_ACCESSORS so that SDHC controller specific\n> register read and write APIs, if registered, can be used.\n> \n> Signed-off-by: Vijay Viswanath \n\nAcked-by: Adrian Hunter \n\n> ---\n> drivers/mmc/host/Kconfig | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig\n> index 2db84dd..11bfb82 100644\n> --- a/drivers/mmc/host/Kconfig\n> +++ b/drivers/mmc/host/Kconfig\n> @@ -420,6 +420,7 @@ config MMC_SDHCI_MSM\n> \ttristate \"Qualcomm SDHCI Controller Support\"\n> \tdepends on ARCH_QCOM || (ARM && COMPILE_TEST)\n> \tdepends on MMC_SDHCI_PLTFM\n> +\tselect MMC_SDHCI_IO_ACCESSORS\n> \thelp\n> \t This selects the Secure Digital Host Controller Interface (SDHCI)\n> \t support present in Qualcomm SOCs. The controller supports\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"YnKH+d0Y\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y5yJ660JYz9s0g\n\tfor ;\n\tTue, 3 Oct 2017 22:59:34 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dzLrJ-0003NZ-9t; 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d=\"scan'208\";a=\"906207619\"","Subject":"Re: [PATCH v2 3/4] mmc: Kconfig: Enable\n\tCONFIG_MMC_SDHCI_IO_ACCESSORS","To":"Vijay Viswanath , ulf.hansson@linaro.org,\n\twill.deacon@arm.com","References":"<1506490483-46871-1-git-send-email-vviswana@codeaurora.org>\n\t<1506490483-46871-4-git-send-email-vviswana@codeaurora.org>","From":"Adrian Hunter ","Organization":"Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, \n\tBusiness Identity Code: 0357606 - 4, Domiciled in Helsinki","Message-ID":"<35266316-e199-30a7-dc7d-bb31f173e018@intel.com>","Date":"Tue, 3 Oct 2017 14:44:34 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1506490483-46871-4-git-send-email-vviswana@codeaurora.org>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171003_045143_431597_9E415AF3 ","X-CRM114-Status":"GOOD ( 10.67 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [192.55.52.120 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, linux-arm-msm@vger.kernel.org,\n\tlinux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tstummala@codeaurora.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1779542,"web_url":"http://patchwork.ozlabs.org/comment/1779542/","msgid":"","list_archive_url":null,"date":"2017-10-04T08:59:24","subject":"Re: [PATCH v2 0/4] mmc: sdhci-msm: Corrections to implementation of\n\tpower irq","submitter":{"id":21036,"url":"http://patchwork.ozlabs.org/api/people/21036/","name":"Ulf Hansson","email":"ulf.hansson@linaro.org"},"content":"On 27 September 2017 at 07:34, Vijay Viswanath wrote:\n> Register writes which change voltage of IO lines or turn the IO bus on/off\n> require sdhc controller to be ready before progressing further. Once a\n> register write which affects IO lines is done, the driver should wait for\n> power irq from controller. Once the irq comes, the driver should acknowledge\n> the irq by writing to power control register. If the acknowledgement is not\n> given to controller, the controller may not complete the corresponding\n> register write action and this can mess up the controller if drivers proceeds\n> without power irq completing.\n>\n> Changes since v1:\n> Patch enabling MMC_IO_ACCESSORS in Kconfig moved up the patch list.\n> Also corrected a mistake in the patch.\n> Removed all ifdef CONFIG_MMC_IO_ACCESSORS since the patches using it\n> will come after MMC_IO_ACCESSORS are enabled.\n> Merged the patches 3 & 4 of earlier series into 1 patch (patch 4 in\n> current series).\n> Corrected a mistake in a comment text in patch 3 of previous series.\n>\n> Changes since RFC:\n> wait_for_completion_timeout replaced with wait_event_timeout when\n> waiting for power irq.\n> Removed the spinlock within power irq handler and API which waits\n> for power irq.\n> Added comments to sdhci msm register write functions, warning that they\n> can sleep.\n> Sdhci msm register write functions will do a memory barrier before\n> writing to the register if the particular register can trigger\n> power irq.\n> Instead of enabling SDHCI IO ACCESSORS config in arm64/defconfig, it\n> will be selected in mmc/host/Kconfig if the platform is MMC_SDHCI_MSM.\n>\n> Sahitya Tummala (1):\n> mmc: sdhci-msm: Fix HW issue with power IRQ handling during reset\n>\n> Subhash Jadavani (1):\n> mmc: sdhci-msm: fix issue with power irq\n>\n> Vijay Viswanath (2):\n> mmc: Kconfig: Enable CONFIG_MMC_SDHCI_IO_ACCESSORS\n> mmc: sdhci-msm: Add sdhci msm register write APIs which wait for pwr\n> irq\n>\n> drivers/mmc/host/Kconfig | 1 +\n> drivers/mmc/host/sdhci-msm.c | 235 ++++++++++++++++++++++++++++++++++++++++++-\n> 2 files changed, 231 insertions(+), 5 deletions(-)\n>\n\nThanks, applied for next!\n\nKind regards\nUffe","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Wed, 4 Oct 2017 01:59:24 -0700 (PDT)"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:To:Subject:Message-ID:Date:From:\n\tReferences:In-Reply-To:MIME-Version:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=WNHL+5IqjfY74YDXdxFdZ7uXGM4R0rTE6IUvKXshFg4=;\n\tb=tjWCRJILvYqziK\n\tIKl9iTj+6FrMdIx0eRH4b8qMFfkAmt0Y9KzdvuE43wwLUW6T2Wipldvi3pH5Ig3vNpOiW+eeQbWEB\n\ti5y6CGcdgA04MHNMCcSJmCONpT4qMEogBCc72WaduSXOEu2kRxJ3krMK2tiu/xKm9TBGcCuBWJAkk\n\t0Pdi0AsOQcjp795HMQp8aJwJzFEaZBT7pZdOv0J9WZFJ0JJNMmY4v1iH6ZS1hpwgD3URSQs9EJFpp\n\tsZkbYYGpPIHZJKVVdn5+W/3j0l/8CIxDWjecUFpqnhY2ifgMbslZusxVza/1lPrF7XTGLMXpVkIUE\n\ttXHIMJq8cmtPJLTrF38w==;","v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1786796,"web_url":"http://patchwork.ozlabs.org/comment/1786796/","msgid":"<20171014073118.GD1575@tuxbook>","list_archive_url":null,"date":"2017-10-14T07:31:18","subject":"Re: [PATCH v2 4/4] mmc: sdhci-msm: Add sdhci msm register write APIs\n\twhich wait for pwr irq","submitter":{"id":68398,"url":"http://patchwork.ozlabs.org/api/people/68398/","name":"Bjorn Andersson","email":"bjorn.andersson@linaro.org"},"content":"On Tue 26 Sep 22:34 PDT 2017, Vijay Viswanath wrote:\n\n> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n[..]\n> +\tif (!done) {\n> +\t\tif (!wait_event_timeout(msm_host->pwr_irq_wait,\n> +\t\t\t\tmsm_host->pwr_irq_flag,\n> +\t\t\t\tmsecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))\n> +\t\t\t__WARN_printf(\"%s: pwr_irq for req: (%d) timed out\\n\",\n> +\t\t\t\t\tmmc_hostname(host->mmc), req_type);\n\nBumped my MSM8974AB device to latest linux-next and found this patch; I\nsee this print every five seconds during boot and the eMMC never comes\nup.\n\nRegards,\nBjorn","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Q5v4YxIL\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"SIUazVWv\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yDbr736lvz9sNr\n\tfor ;\n\tSat, 14 Oct 2017 18:31:51 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e3GvD-0005Dw-Qf; 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\n\tSat, 14 Oct 2017 00:31:21 -0700 (PDT)","Date":"Sat, 14 Oct 2017 00:31:18 -0700","From":"Bjorn Andersson ","To":"Vijay Viswanath ","Subject":"Re: [PATCH v2 4/4] mmc: sdhci-msm: Add sdhci msm register write APIs\n\twhich wait for pwr irq","Message-ID":"<20171014073118.GD1575@tuxbook>","References":"<1506490483-46871-1-git-send-email-vviswana@codeaurora.org>\n\t<1506490483-46871-5-git-send-email-vviswana@codeaurora.org>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1506490483-46871-5-git-send-email-vviswana@codeaurora.org>","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171014_003142_952666_65C20B2B ","X-CRM114-Status":"UNSURE ( 8.11 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2607:f8b0:400e:c00:0:0:0:236 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, ulf.hansson@linaro.org, will.deacon@arm.com,\n\tlinux-mmc@vger.kernel.org, adrian.hunter@intel.com,\n\tlinux-kernel@vger.kernel.org, stummala@codeaurora.org,\n\tlinux-arm-msm@vger.kernel.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1791353,"web_url":"http://patchwork.ozlabs.org/comment/1791353/","msgid":"","list_archive_url":null,"date":"2017-10-20T10:54:39","subject":"Re: [PATCH v2 4/4] mmc: sdhci-msm: Add sdhci msm register write APIs\n\twhich wait for pwr irq","submitter":{"id":72258,"url":"http://patchwork.ozlabs.org/api/people/72258/","name":"Vijay Viswanath","email":"vviswana@codeaurora.org"},"content":"On 10/14/2017 1:01 PM, Bjorn Andersson wrote:\n> On Tue 26 Sep 22:34 PDT 2017, Vijay Viswanath wrote:\n> \n>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> [..]\n>> +\tif (!done) {\n>> +\t\tif (!wait_event_timeout(msm_host->pwr_irq_wait,\n>> +\t\t\t\tmsm_host->pwr_irq_flag,\n>> +\t\t\t\tmsecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))\n>> +\t\t\t__WARN_printf(\"%s: pwr_irq for req: (%d) timed out\\n\",\n>> +\t\t\t\t\tmmc_hostname(host->mmc), req_type);\n> \n> Bumped my MSM8974AB device to latest linux-next and found this patch; I\n> see this print every five seconds during boot and the eMMC never comes\n> up.\n> \n> Regards,\n> Bjorn\n> --\n> To unsubscribe from this list: send the line \"unsubscribe linux-mmc\" in\n> the body of a message to majordomo@vger.kernel.org\n> More majordomo info at http://vger.kernel.org/majordomo-info.html\n> \n\nHi Bjorn,\n\nI couldn't get one 8974 device. I tested the latest linux-next on db410c \nand its not showing any issue. 8974 is an older msm and has some \ndifferences in the controller like your \"mmc: sdhci-msm: Enable delay \ncircuit calibration clocks\" patch.\n\nI am currently going through the programming guide to see what could be \nthe reason. Can you please share the full logs from the device with me \nso that I can focus my search?\n\nThanks,\nVijay","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"g2XM1ncH\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=infradead.org header.i=@infradead.org\n\theader.b=\"qcvNECXf\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"cTN1UKZ8\"; \n\tdkim=neutral (0-bit key) header.d=codeaurora.org\n\theader.i=@codeaurora.org\n\theader.b=\"BsPO/DMx\"; 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WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"<20171014073118.GD1575@tuxbook>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171020_115508_851193_306D29B3 ","X-CRM114-Status":"GOOD ( 19.41 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on casper.infradead.org summary:\n\tContent analysis details: (-4.3 points, 5.0 required)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [198.145.29.96 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, ulf.hansson@linaro.org, will.deacon@arm.com,\n\tlinux-mmc@vger.kernel.org, adrian.hunter@intel.com,\n\tlinux-kernel@vger.kernel.org, stummala@codeaurora.org,\n\tlinux-arm-msm@vger.kernel.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1791655,"web_url":"http://patchwork.ozlabs.org/comment/1791655/","msgid":"<20171020180529.GC1165@minitux>","list_archive_url":null,"date":"2017-10-20T18:05:29","subject":"Re: [PATCH v2 4/4] mmc: sdhci-msm: Add sdhci msm register write APIs\n\twhich wait for pwr irq","submitter":{"id":68398,"url":"http://patchwork.ozlabs.org/api/people/68398/","name":"Bjorn Andersson","email":"bjorn.andersson@linaro.org"},"content":"On Fri 20 Oct 03:54 PDT 2017, Vijay Viswanath wrote:\n\n> On 10/14/2017 1:01 PM, Bjorn Andersson wrote:\n> > On Tue 26 Sep 22:34 PDT 2017, Vijay Viswanath wrote:\n> > \n> > > diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> > [..]\n> > > +\tif (!done) {\n> > > +\t\tif (!wait_event_timeout(msm_host->pwr_irq_wait,\n> > > +\t\t\t\tmsm_host->pwr_irq_flag,\n> > > +\t\t\t\tmsecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))\n> > > +\t\t\t__WARN_printf(\"%s: pwr_irq for req: (%d) timed out\\n\",\n> > > +\t\t\t\t\tmmc_hostname(host->mmc), req_type);\n> > \n> > Bumped my MSM8974AB device to latest linux-next and found this patch; I\n> > see this print every five seconds during boot and the eMMC never comes\n> > up.\n> > \n> > Regards,\n> > Bjorn\n> > --\n> > To unsubscribe from this list: send the line \"unsubscribe linux-mmc\" in\n> > the body of a message to majordomo@vger.kernel.org\n> > More majordomo info at http://vger.kernel.org/majordomo-info.html\n> > \n> \n> Hi Bjorn,\n> \n\nHi Vijay,\n\n> I couldn't get one 8974 device. I tested the latest linux-next on db410c and\n> its not showing any issue. 8974 is an older msm and has some differences in\n> the controller like your \"mmc: sdhci-msm: Enable delay circuit calibration\n> clocks\" patch.\n> \n\nIn particular there seems to be some quirks that appeared in 8974pro\n(which this is).\n\n> I am currently going through the programming guide to see what could be the\n> reason. Can you please share the full logs from the device with me so that I\n> can focus my search?\n> \n\nOf course, sorry for the drive-by report without much to go on. I did\nsome more testing and you can find an extract of the kernel log below.\nI was apparently not patient enough before, after 124 seconds we're\nthrough all the timeouts and my eMMC is \"functional\" - so things are\nworking, but we're getting stuck waiting for the timeout every time\nwe're waiting for the pwr irq.\n\n\nAs you can see below we get sdhci_msm_handle_pwr_irq() with status\nBUS_ON, so we set io-level HIGH. Then we don't get any more pwr\ninterrupts, so the io_level remains \"high\" - although I believe we're\nactually low (vqmmc is always 1.8V on this board).\n\nWorth noting is the large comment in sdhci_msm_check_power_status()\nrelated to !host->pwr, host->pwr is always 0 on this board.\n\n# dmesg |grep mmc0\n[ 1.734573] mmc0: sdhci_msm_handle_pwr_irq: Handled IRQ(0), irq_status=0x0, ack=0x0\n[ 1.857611] mmc0: sdhci_msm_handle_pwr_irq: Handled IRQ(0), irq_status=0x0, ack=0x0\n[ 1.889400] mmc0: sdhci_msm_handle_pwr_irq: Handled IRQ(0), irq_status=0x0, ack=0x0\n[ 2.141634] mmc0: sdhci_msm_handle_pwr_irq: Handled IRQ(0), irq_status=0x0, ack=0x0\n[ 2.163023] mmc0: sdhci_msm_handle_pwr_irq: Handled IRQ(0), irq_status=0x0, ack=0x0\n[ 2.238875] mmc0: sdhci_msm_handle_pwr_irq: Handled IRQ(0), irq_status=0x0, ack=0x0\n[ 2.509617] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 0 curr_io_level 0\n[ 2.509710] mmc0: sdhci_msm_pwr_irq()\n[ 2.509723] mmc0: sdhci_msm_handle_pwr_irq: Handled IRQ(30), irq_status=0x2, ack=0x1\n[ 2.536468] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 2.546363] mmc0: sdhci_msm_check_power_status: request 8 curr_pwr_state 2 curr_io_level 8\n[ 2.551220] mmc0: do not wait for power IRQ that never comes, req_type: 8\n[ 2.559502] sdhci_msm f9824900.sdhci: mmc0: clock=0 uhs=0 ctrl_2=0x0\n[ 2.572777] mmc0: sdhci_msm_check_power_status: request 8 curr_pwr_state 2 curr_io_level 8\n[ 2.577353] mmc0: do not wait for power IRQ that never comes, req_type: 8\n[ 2.592564] mmc0: sdhci_msm_check_power_status: request 8 curr_pwr_state 2 curr_io_level 8\n[ 2.597230] mmc0: do not wait for power IRQ that never comes, req_type: 8\n[ 2.605589] mmc0: Switching to 3.3V signalling voltage failed\n[ 2.618172] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 7.687764] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 7.687795] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 7.717799] mmc0: Setting clock at rate 400000 at timing 0\n[ 7.717887] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 7.722170] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 7.736229] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 12.807757] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 12.807785] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 12.813531] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=0 ctrl_2=0x8\n[ 12.826189] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 17.847757] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 17.847784] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 17.853520] mmc0: Setting clock at rate 400000 at timing 0\n[ 17.887757] mmc0: SDHCI controller on f9824900.sdhci [f9824900.sdhci] using ADMA 64-bit\n[ 17.897018] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 17.902821] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 17.916694] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 22.967759] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 22.967787] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 22.973533] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=0 ctrl_2=0x8\n[ 22.986192] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 28.007753] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 28.007777] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 28.013515] mmc0: Setting clock at rate 400000 at timing 0\n[ 28.021738] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 28.024798] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 28.038879] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 33.047769] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 33.047793] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 33.053536] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=0 ctrl_2=0x8\n[ 33.066199] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 38.087755] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 38.087779] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 38.093514] mmc0: Setting clock at rate 400000 at timing 0\n[ 38.105722] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 38.105748] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 38.118881] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 43.127756] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 43.127780] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 43.133523] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=0 ctrl_2=0x8\n[ 43.146184] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 48.167756] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 48.167780] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 48.173515] mmc0: Setting clock at rate 400000 at timing 0\n[ 48.179810] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 48.184800] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 48.198880] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 53.207753] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 53.207777] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 53.213518] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=0 ctrl_2=0x8\n[ 53.226181] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 58.247754] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 58.247777] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 58.253513] mmc0: Setting clock at rate 400000 at timing 0\n[ 58.259414] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 58.264797] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 58.278877] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 63.287754] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 63.287779] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 63.293521] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=0 ctrl_2=0x8\n[ 63.306184] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 68.327764] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 68.327792] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 68.333530] mmc0: Setting clock at rate 400000 at timing 0\n[ 68.341746] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 68.344812] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 68.358891] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 73.367756] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 73.367783] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 73.373525] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=0 ctrl_2=0x8\n[ 73.386186] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 78.407759] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 78.407786] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 78.413521] mmc0: Setting clock at rate 400000 at timing 0\n[ 78.449337] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 78.449363] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 78.462325] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 83.527756] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 83.527781] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 83.533524] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=0 ctrl_2=0x8\n[ 83.546187] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 88.567758] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 88.567786] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 88.573522] mmc0: Setting clock at rate 400000 at timing 0\n[ 88.611069] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 93.687759] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 93.687788] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 93.694461] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 93.699369] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 93.713422] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 98.727752] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 98.727779] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 98.733523] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=0 ctrl_2=0x8\n[ 98.746184] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 103.767770] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 103.767795] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 103.773531] mmc0: Setting clock at rate 400000 at timing 0\n[ 103.799563] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 103.799589] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 103.812552] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 108.887755] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 108.887779] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 108.893522] sdhci_msm f9824900.sdhci: mmc0: clock=400000 uhs=9 ctrl_2=0x8\n[ 108.906185] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 113.927755] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 113.927778] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 113.933513] mmc0: Setting clock at rate 400000 at timing 9\n[ 113.939901] mmc0: Setting clock at rate 200000000 at timing 9\n[ 113.944801] mmc0: sdhci_msm_check_power_status: request 2 curr_pwr_state 2 curr_io_level 8\n[ 113.950642] mmc0: sdhci_msm_check_power_status: request 2 done\n[ 113.964587] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 119.047754] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 119.047778] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 119.053513] sdhci_msm f9824900.sdhci: mmc0: clock=200000000 uhs=9 ctrl_2=0xb\n[ 119.066531] mmc0: sdhci_msm_check_power_status: request 4 curr_pwr_state 2 curr_io_level 8\n[ 124.087755] sdhci_msm f9824900.sdhci: mmc0: pwr_irq for req: (4) timed out\n[ 124.087779] mmc0: sdhci_msm_check_power_status: request 4 done\n[ 124.093514] mmc0: Setting clock at rate 200000000 at timing 9\n[ 124.099657] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 0\n[ 124.105439] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 1\n[ 124.111537] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 2\n[ 124.117501] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 3\n[ 124.123514] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 4\n[ 124.129501] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 5\n[ 124.135411] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 6\n[ 124.141423] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 7\n[ 124.147389] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 8\n[ 124.153403] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 9\n[ 124.159448] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 10\n[ 124.165417] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 11\n[ 124.171433] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 12\n[ 124.177483] sdhci_msm f9824900.sdhci: mmc0: Found good phase = 13\n[ 124.183709] sdhci_msm f9824900.sdhci: mmc0: Setting the tuning phase to 9\n[ 124.189943] mmc0: new HS200 MMC card at address 0001\n[ 124.198091] mmcblk0: mmc0:0001 MAG2GC 14.6 GiB \n[ 124.201538] mmcblk0boot0: mmc0:0001 MAG2GC partition 1 4.00 MiB\n[ 124.205695] mmcblk0boot1: mmc0:0001 MAG2GC partition 2 4.00 MiB\n[ 124.211637] mmcblk0rpmb: mmc0:0001 MAG2GC partition 3 4.00 MiB, chardev (247:0)\n\n\nPlease let me know if I can assist you with anything additional!\n\nRegards,\nBjorn","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"jCz9u/bR\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) 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\n\tFri, 20 Oct 2017 11:05:32 -0700 (PDT)","Date":"Fri, 20 Oct 2017 11:05:29 -0700","From":"Bjorn Andersson ","To":"Vijay Viswanath ","Subject":"Re: [PATCH v2 4/4] mmc: sdhci-msm: Add sdhci msm register write APIs\n\twhich wait for pwr irq","Message-ID":"<20171020180529.GC1165@minitux>","References":"<1506490483-46871-1-git-send-email-vviswana@codeaurora.org>\n\t<1506490483-46871-5-git-send-email-vviswana@codeaurora.org>\n\t<20171014073118.GD1575@tuxbook>\n\t","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.8.3 (2017-05-23)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171020_110554_530346_3A87EE75 ","X-CRM114-Status":"GOOD ( 20.19 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2607:f8b0:400e:c00:0:0:0:241 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"riteshh@codeaurora.org, ulf.hansson@linaro.org, will.deacon@arm.com,\n\tlinux-mmc@vger.kernel.org, adrian.hunter@intel.com,\n\tlinux-kernel@vger.kernel.org, stummala@codeaurora.org,\n\tlinux-arm-msm@vger.kernel.org, subhashj@codeaurora.org,\n\tlinux-arm-kernel@lists.infradead.org, asutoshd@codeaurora.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1923578,"web_url":"http://patchwork.ozlabs.org/comment/1923578/","msgid":"<6c84f6fc-270c-d826-6d87-7f9f6fc5015f@codeaurora.org>","list_archive_url":null,"date":"2018-05-30T07:11:00","subject":"Re: [PATCH v2 4/4] mmc: sdhci-msm: Add sdhci msm register write APIs\n\twhich wait for pwr irq","submitter":{"id":72258,"url":"http://patchwork.ozlabs.org/api/people/72258/","name":"Vijay Viswanath","email":"vviswana@codeaurora.org"},"content":"Hi Georgi,\n\nThanks for testing the patch on 8096 and pointing out this issue.\nThe issue is coming because, when card is removed, the HOST_CONTROL2 \nregister is retaining the 1.8V Signalling enable bit till SDHCI reset \nhappens after a new card is inserted.\n\nAdding the change you suggested can avoid this wait, but I feel a better \nsolution is to clear the 1.8V signalling bit when the card is removed. \nWhen a new card is inserted, we shouldn't be keeping the 1.8V bit set \nuntil we send cmd11 to the SD card. A new SD card should start with 3V.\n\nOne solution is to explicitly clear the HOST_CONTROL2 register when card \nis removed.\n\nOther way is to revert the commit: \n9718f84b85396e090ca42fafa730410d286d61e3 \"mmc: sdhci-msm: Do not reset \nthe controller if no card in the slot\"\n\nThe sdhci-msm doesn't require \"SDHCI_QUIRK_NO_CARD_NO_RESET\". The issue \nwhich above commit is trying to avoid is fixed by the pwr-irq patches. \nResetting the controller will clear the HOST_CONTROL2 register and avoid \nthis issue.\n\nCan you please try this ? I tested reverting the QUIRK on two platforms: \ndb410c(8916) and sdm845. SD card insert/remove worked fine after that \nand I didn't get any \"Reset 0x1 never completed\" error during card \ninsert/remove or shutdown.\n\nThanks,\nVijay\n\nOn 5/29/2018 5:49 PM, Georgi Djakov wrote:\n> Hello Vijay,\n> \n> On 09/27/2017 08:34 AM, Vijay Viswanath wrote:\n>> Register writes which change voltage of IO lines or turn the IO bus\n>> on/off require controller to be ready before progressing further. When\n>> the controller is ready, it will generate a power irq which needs to be\n>> handled. The thread which initiated the register write should wait for\n>> power irq to complete. This will be done through the new sdhc msm write\n>> APIs which will check whether the particular write can trigger a power\n>> irq and wait for it with a timeout if it is expected.\n>> The SDHC core power control IRQ gets triggered when -\n>> * There is a state change in power control bit (bit 0)\n>> of SDHCI_POWER_CONTROL register.\n>> * There is a state change in 1.8V enable bit (bit 3) of\n>> SDHCI_HOST_CONTROL2 register.\n>> * Bit 1 of SDHCI_SOFTWARE_RESET is set.\n>>\n>> Also add support APIs which are used by sdhc msm write APIs to check\n>> if power irq is expected to be generated and wait for the power irq\n>> to come and complete if the irq is expected.\n>>\n>> This patch requires CONFIG_MMC_SDHCI_IO_ACCESSORS to be enabled.\n>>\n>> Signed-off-by: Sahitya Tummala \n>> Signed-off-by: Vijay Viswanath \n>> ---\n>> drivers/mmc/host/sdhci-msm.c | 173 ++++++++++++++++++++++++++++++++++++++++++-\n>> 1 file changed, 171 insertions(+), 2 deletions(-)\n>>\n>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> \n> [..]\n> \n>> +/*\n>> + * sdhci_msm_check_power_status API should be called when registers writes\n>> + * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.\n>> + * To what state the register writes will change the IO lines should be passed\n>> + * as the argument req_type. This API will check whether the IO line's state\n>> + * is already the expected state and will wait for power irq only if\n>> + * power irq is expected to be trigerred based on the current IO line state\n>> + * and expected IO line state.\n>> + */\n>> +static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)\n>> +{\n>> +\tstruct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);\n>> +\tstruct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);\n>> +\tbool done = false;\n>> +\n>> +\tpr_debug(\"%s: %s: request %d curr_pwr_state %x curr_io_level %x\\n\",\n>> +\t\t\tmmc_hostname(host->mmc), __func__, req_type,\n>> +\t\t\tmsm_host->curr_pwr_state, msm_host->curr_io_level);\n>> +\n>> +\t/*\n>> +\t * The IRQ for request type IO High/LOW will be generated when -\n>> +\t * there is a state change in 1.8V enable bit (bit 3) of\n>> +\t * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0\n>> +\t * which indicates 3.3V IO voltage. So, when MMC core layer tries\n>> +\t * to set it to 3.3V before card detection happens, the\n>> +\t * IRQ doesn't get triggered as there is no state change in this bit.\n>> +\t * The driver already handles this case by changing the IO voltage\n>> +\t * level to high as part of controller power up sequence. Hence, check\n>> +\t * for host->pwr to handle a case where IO voltage high request is\n>> +\t * issued even before controller power up.\n>> +\t */\n>> +\tif ((req_type & REQ_IO_HIGH) && !host->pwr) {\n>> +\t\tpr_debug(\"%s: do not wait for power IRQ that never comes, req_type: %d\\n\",\n>> +\t\t\t\tmmc_hostname(host->mmc), req_type);\n>> +\t\treturn;\n>> +\t}\n>> +\tif ((req_type & msm_host->curr_pwr_state) ||\n>> +\t\t\t(req_type & msm_host->curr_io_level))\n>> +\t\tdone = true;\n>> +\t/*\n>> +\t * This is needed here to handle cases where register writes will\n>> +\t * not change the current bus state or io level of the controller.\n>> +\t * In this case, no power irq will be triggerred and we should\n>> +\t * not wait.\n>> +\t */\n>> +\tif (!done) {\n>> +\t\tif (!wait_event_timeout(msm_host->pwr_irq_wait,\n>> +\t\t\t\tmsm_host->pwr_irq_flag,\n>> +\t\t\t\tmsecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS)))\n>> +\t\t\t__WARN_printf(\"%s: pwr_irq for req: (%d) timed out\\n\",\n>> +\t\t\t\t\tmmc_hostname(host->mmc), req_type);\n> \n> I am seeing the above error message on a db820c device (apq8096). When i\n> unplug the SD card and then plug it back in, there is a 5 sec card\n> detection delay and a timeout. Here is a log:\n> \n> [ 50.253997] mmc0: card 59b4 removed\n> [ 50.381874] mmc0: sdhci_msm_check_power_status: request 1\n> curr_pwr_state 2 curr_io_level 4 sdhci_host_ctrl2 b\n> [ 50.382656] mmc0: sdhci_msm_check_power_status: request 1 done\n> [ 50.392493] mmc0: sdhci_msm_check_power_status: request 4\n> curr_pwr_state 1 curr_io_level 4 sdhci_host_ctrl2 b\n> [ 50.398258] mmc0: sdhci_msm_check_power_status: request 4 done\n> [ 50.408728] mmc0: sdhci_msm_check_power_status: request 4\n> curr_pwr_state 1 curr_io_level 4 sdhci_host_ctrl2 8\n> [ 50.413865] mmc0: sdhci_msm_check_power_status: request 4 done\n> [ 54.966316] mmc0: sdhci_msm_check_power_status: request 2\n> curr_pwr_state 1 curr_io_level 4 sdhci_host_ctrl2 8 <-- card is plugged\n> [ 54.967756] mmc0: sdhci_msm_check_power_status: request 2 done\n> [ 54.976822] mmc0: sdhci_msm_check_power_status: request 4\n> curr_pwr_state 2 curr_io_level 8 sdhci_host_ctrl2 8\n> [ 60.132253] sdhci_msm 74a4900.sdhci: mmc0: pwr_irq for req: (4) timed out\n> [ 60.132782] mmc0: sdhci_msm_check_power_status: request 4 done\n> [ 60.139888] mmc0: sdhci_msm_check_power_status: request 4\n> curr_pwr_state 2 curr_io_level 8 sdhci_host_ctrl2 8\n> [ 65.252497] sdhci_msm 74a4900.sdhci: mmc0: pwr_irq for req: (4) timed out\n> \n> The following patch seem to \"fix\" it.\n> \n> -- >8 --\n> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c\n> index b2d875afae5f..ca8ad4edcf80 100644\n> --- a/drivers/mmc/host/sdhci-msm.c\n> +++ b/drivers/mmc/host/sdhci-msm.c\n> @@ -1049,6 +1049,11 @@ static void sdhci_msm_check_power_status(struct\n> sdhci_host *host, u32 req_type)\n> return;\n> }\n> \n> + if (req_type & REQ_IO_LOW &&\n> + msm_host->curr_pwr_state & REQ_BUS_ON &&\n> + msm_host->curr_io_level & REQ_IO_HIGH &&\n> + !host->pwr)\n> + done = true;\n> /*\n> * The IRQ for request type IO High/LOW will be generated when -\n> * there is a state change in 1.8V enable bit (bit 3) of\n> -- >8 --\n> \n> Reverting this patch series or applying the above patch makes the issue\n> go away. According to the log, there is no change in the\n> sdhci_host_ctrl2 register. What do you think?\n> \n> Thanks,\n> Georgi\n> --\n> To unsubscribe from this list: send the line \"unsubscribe linux-mmc\" in\n> the body of a message to majordomo@vger.kernel.org\n> More majordomo info at http://vger.kernel.org/majordomo-info.html\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=codeaurora.org","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"sShIU8Wc\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"LjmDUxlu\"; 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charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1923984,"web_url":"http://patchwork.ozlabs.org/comment/1923984/","msgid":"<06d8c601-3d9f-c08e-3cfa-b33df91486f6@linaro.org>","list_archive_url":null,"date":"2018-05-30T15:57:56","subject":"Re: [PATCH v2 4/4] mmc: sdhci-msm: Add sdhci msm register write APIs\n\twhich wait for pwr irq","submitter":{"id":70295,"url":"http://patchwork.ozlabs.org/api/people/70295/","name":"Georgi Djakov","email":"georgi.djakov@linaro.org"},"content":"Hi Vijay,\n\nOn 05/30/2018 10:11 AM, Vijay Viswanath wrote:\n> Hi Georgi,\n> \n> Thanks for testing the patch on 8096 and pointing out this issue.\n> The issue is coming because, when card is removed, the HOST_CONTROL2\n> register is retaining the 1.8V Signalling enable bit till SDHCI reset\n> happens after a new card is inserted.\n> \n> Adding the change you suggested can avoid this wait, but I feel a better\n> solution is to clear the 1.8V signalling bit when the card is removed.\n> When a new card is inserted, we shouldn't be keeping the 1.8V bit set\n> until we send cmd11 to the SD card. A new SD card should start with 3V.\n> \n> One solution is to explicitly clear the HOST_CONTROL2 register when card\n> is removed.\n> \n> Other way is to revert the commit:\n> 9718f84b85396e090ca42fafa730410d286d61e3 \"mmc: sdhci-msm: Do not reset\n> the controller if no card in the slot\"\n> \n> The sdhci-msm doesn't require \"SDHCI_QUIRK_NO_CARD_NO_RESET\". The issue\n> which above commit is trying to avoid is fixed by the pwr-irq patches.\n> Resetting the controller will clear the HOST_CONTROL2 register and avoid\n> this issue.\n> \n> Can you please try this ? I tested reverting the QUIRK on two platforms:\n> db410c(8916) and sdm845. SD card insert/remove worked fine after that\n> and I didn't get any \"Reset 0x1 never completed\" error during card\n> insert/remove or shutdown.\n\nThank you! I have submitted a patch to remove the quirk and tested it on\ndb410c and db820c.\n\nBR,\nGeorgi","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=linaro.org","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"ec2nrlaW\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"B1+t0chE\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[IPv6:2607:7c80:54:e::133])\n\t(using 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sdhci msm register write APIs\n\twhich wait for pwr irq","To":"Vijay Viswanath ","References":"<1506490483-46871-1-git-send-email-vviswana@codeaurora.org>\n\t<1506490483-46871-5-git-send-email-vviswana@codeaurora.org>\n\t<74a4fe0e-7ae8-9f49-5614-1e01ae977475@linaro.org>\n\t<6c84f6fc-270c-d826-6d87-7f9f6fc5015f@codeaurora.org>","From":"Georgi Djakov ","Openpgp":"preference=signencrypt","Autocrypt":"addr=georgi.djakov@linaro.org; prefer-encrypt=mutual; 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