[{"id":1784401,"web_url":"http://patchwork.ozlabs.org/comment/1784401/","msgid":"","list_archive_url":null,"date":"2017-10-11T08:40:58","subject":"Re: [PATCH v6 2/2] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","submitter":{"id":7055,"url":"http://patchwork.ozlabs.org/api/people/7055/","name":"Linus Walleij","email":"linus.walleij@linaro.org"},"content":"On Wed, Sep 27, 2017 at 4:40 AM, Masahiro Yamada\n wrote:\n\n> This GPIO controller is used on UniPhier SoC family.\n>\n> It also serves as an interrupt controller, but interrupt signals are\n> just delivered to the parent irqchip without any latching or OR'ing.\n> This type of hardware can be well described with hierarchy IRQ domain.\n>\n> One unfortunate thing for this device is that the interrupt mapping to\n> the interrupt parent is not contiguous.\n>\n> I asked how DT can describe interrupt mapping between two irqchips [1],\n> but I could not find a good solution (at least in the framework level).\n> In fact, irqchip drivers using hierarchy domain generally hard-code the\n> DT binding of their parent.\n>\n> After tackling on several approaches such as hard-code of hwirqs,\n> irq_domain_push_irq(), I ended up with a vendor specific property.\n> If we come up with a good idea to support this in the framework, we\n> can migrate over to it, but we can live with a driver-level solution\n> for now.\n>\n> [1] https://lkml.org/lkml/2017/7/6/758\n>\n> Signed-off-by: Masahiro Yamada \n\nMostly happy with this.\n\n> @@ -2036,6 +2036,7 @@ F: arch/arm/mm/cache-uniphier.c\n> F: arch/arm64/boot/dts/socionext/\n> F: drivers/bus/uniphier-system-bus.c\n> F: drivers/clk/uniphier/\n> +F: drivers/gpio/gpio-uniphier.c\n\nAlso add an entry for the device tree bindings please.\n\n> +++ b/include/dt-bindings/gpio/uniphier-gpio.h\n> @@ -0,0 +1,18 @@\n> +/*\n> + * Copyright (C) 2017 Socionext Inc.\n> + * Author: Masahiro Yamada \n> + */\n> +\n> +#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H\n> +#define _DT_BINDINGS_GPIO_UNIPHIER_H\n> +\n> +#define UNIPHIER_GPIO_LINES_PER_BANK 8\n> +\n> +#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15)\n> +\n> +#define UNIPHIER_GPIO_PORT(bank, line) \\\n> + ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))\n> +\n> +#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n))\n> +\n> +#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */\n\nI do not understand what some of these things are doing in the\ndevice tree header file.\n\nIt just looks creepingly similar to some of the magic I've seen\nin board files.\n\nIt makes much more sense that the device trees either:\n\n- Use the interrupts as a flat array 0...N across all banks\n\n- Model each bank as a separate GPIO chip\n\nThis is somewhere inbetween, you are modeling it as a single\ngpiochip but still not, becuase the device tree author still need\nto address banking, that is confusing.\n\nYours,\nLinus Walleij\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"EZU+edcC\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yBnWM4mDYz9t3Z\n\tfor ;\n\tWed, 11 Oct 2017 19:41:03 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755552AbdJKIlB (ORCPT\n\t);\n\tWed, 11 Oct 2017 04:41:01 -0400","from mail-it0-f54.google.com ([209.85.214.54]:56326 \"EHLO\n\tmail-it0-f54.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1756608AbdJKIk7 (ORCPT\n\t); Wed, 11 Oct 2017 04:40:59 -0400","by mail-it0-f54.google.com with SMTP id g18so1908461itg.5\n\tfor ;\n\tWed, 11 Oct 2017 01:40:59 -0700 (PDT)","by 10.79.14.140 with HTTP; Wed, 11 Oct 2017 01:40:58 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=k13pRs5Gvip2qOm3hStA9+jcxWybhsKEcjpG3PmfHc0=;\n\tb=EZU+edcCm4K2OoHW1YZtwTgZST+pLKgdSgIcLGxR/mspXXoFQyT0udwe0uMGLR5Qx4\n\tmTf+Z74K44xQWJxeGtCLr06gsRe9KLZUCbEGDHtRVkLE60KrYL47gZxigVuIHApCKp1G\n\tprZGBRAXSdkBEATOFKMPs1CJuxXn+b+0Qk9es=","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=k13pRs5Gvip2qOm3hStA9+jcxWybhsKEcjpG3PmfHc0=;\n\tb=iWeZcq9geUBqRv/WvHv9A557EweaDh4fLprjpveCzxQEnTRtlxuK9Mss+brPrubI56\n\tzD5/CqxFF9Z4D3qwjWMag92KD7p932GoEsRPz34WabLo1jJ0k7zIglBobjkP3/efGPtk\n\tokdb502jSNV+bsNU5HpylgrcBvk4t5mzgO0tsfSYcuQHJP0RcnuUp3Lm7JDWk/UYywOU\n\t25GZv7tLRLY1KgOitR8KZTjaLPkzA+k+9Y2QbyhcvLeXkM+JKOuY9WSu449KJlqitjiT\n\tqoO1VjQdV/kQT2VbfJCnIhyGwTZbjweMC4mtLt1oxLuWjEhSEUzuPl6gzJuebPG5mQjH\n\tB2+Q==","X-Gm-Message-State":"AMCzsaUzNdKRcziEpEBW09eUYWl6vaTK2JAV1ZJjSJEgsuvSCymcVYot\n\t8Gij8bdqV1+vMQExyHOnAw/q5PD05rjnwzT7l8/eJA==","X-Google-Smtp-Source":"AOwi7QCcnv9AdL3hyGKbVSE1CjpdwoGpvgCpCZ5nuX4jMduPDq40TibmGhHJgcTgYgc6qJE5dI/XZA035dGO/ifT4wI=","X-Received":"by 10.36.160.136 with SMTP id o130mr9505580ite.36.1507711258630; \n\tWed, 11 Oct 2017 01:40:58 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1506480022-8995-3-git-send-email-yamada.masahiro@socionext.com>","References":"<1506480022-8995-1-git-send-email-yamada.masahiro@socionext.com>\n\t<1506480022-8995-3-git-send-email-yamada.masahiro@socionext.com>","From":"Linus Walleij ","Date":"Wed, 11 Oct 2017 10:40:58 +0200","Message-ID":"","Subject":"Re: [PATCH v6 2/2] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","To":"Masahiro Yamada ","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"devicetree@vger.kernel.org\" ,\n\tRob Herring , Masami Hiramatsu ,\n\tJassi Brar ,\n\tMauro Carvalho Chehab ,\n\tRandy Dunlap ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\t\"David S. Miller\" ,\n\tRob Herring , \n\tGreg Kroah-Hartman ,\n\tMark Rutland ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1784451,"web_url":"http://patchwork.ozlabs.org/comment/1784451/","msgid":"","list_archive_url":null,"date":"2017-10-11T09:38:48","subject":"Re: [PATCH v6 2/2] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","submitter":{"id":65882,"url":"http://patchwork.ozlabs.org/api/people/65882/","name":"Masahiro Yamada","email":"yamada.masahiro@socionext.com"},"content":"2017-10-11 17:40 GMT+09:00 Linus Walleij :\n\n>\n>> +++ b/include/dt-bindings/gpio/uniphier-gpio.h\n>> @@ -0,0 +1,18 @@\n>> +/*\n>> + * Copyright (C) 2017 Socionext Inc.\n>> + * Author: Masahiro Yamada \n>> + */\n>> +\n>> +#ifndef _DT_BINDINGS_GPIO_UNIPHIER_H\n>> +#define _DT_BINDINGS_GPIO_UNIPHIER_H\n>> +\n>> +#define UNIPHIER_GPIO_LINES_PER_BANK 8\n>> +\n>> +#define UNIPHIER_GPIO_IRQ_OFFSET ((UNIPHIER_GPIO_LINES_PER_BANK) * 15)\n>> +\n>> +#define UNIPHIER_GPIO_PORT(bank, line) \\\n>> + ((UNIPHIER_GPIO_LINES_PER_BANK) * (bank) + (line))\n>> +\n>> +#define UNIPHIER_GPIO_IRQ(n) ((UNIPHIER_GPIO_IRQ_OFFSET) + (n))\n>> +\n>> +#endif /* _DT_BINDINGS_GPIO_UNIPHIER_H */\n>\n> I do not understand what some of these things are doing in the\n> device tree header file.\n> It just looks creepingly similar to some of the magic I've seen\n> in board files.\n\nBecause this hardware design is crazy crap.\n\nOnly the one's place of the GPIO labels is octal.\nThe other places are decimal.\n\n\n\n> It makes much more sense that the device trees either:\n>\n> - Use the interrupts as a flat array 0...N across all banks\n\nI think I did so.\n\nBut, please note only bank 15, 16, 17 can support irq.\n(and bank 15, 16, 17 share the same irq control register)\n\nNo irq support for bank 0-14, 18-31.\n\nNo symmetry in the hardware structure.\n\n\n> - Model each bank as a separate GPIO chip\n\nNo, no, never.\nI had already tried per-bank splitting approach,\nbut it was a horrible disaster.\n\nPlease note there would end up 31 banks if it were split.\n(31 nodes in DT)\n\nWhat is worse, registers from different banks interleave,\nand, in some places, share the same registers.\n\n\n\n> This is somewhere inbetween, you are modeling it as a single\n> gpiochip but still not, becuase the device tree author still need\n> to address banking, that is confusing.\n\nThis is the best solution I found.\n\n\n\nUnfortunately, the hardware specification adopts weird GPIO pin labeling.\nThe ports are named as\n PORT00, PORT01, PORT02, ..., PORT07,\n PORT10, PORT11, PORT12, ..., PORT17,\n PORT20, PORT21, PORT22, ..., PORT27,\n ...\n PORT90, PORT91, PORT92, ..., PORT97,\n PORT100, PORT101, PORT102, ..., PORT107,\n ...\n\n\nNo PORT08, PORT09, ...\nAs I said above, only the one's place is octal.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=nifty.com header.i=@nifty.com\n\theader.b=\"kkLm+BjC\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yBpqL2MWfz9t39\n\tfor ;\n\tWed, 11 Oct 2017 20:39:58 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752346AbdJKJjn (ORCPT\n\t);\n\tWed, 11 Oct 2017 05:39:43 -0400","from conssluserg-03.nifty.com ([210.131.2.82]:32233 \"EHLO\n\tconssluserg-03.nifty.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751462AbdJKJjl (ORCPT\n\t); Wed, 11 Oct 2017 05:39:41 -0400","from mail-qt0-f181.google.com (mail-qt0-f181.google.com\n\t[209.85.216.181]) (authenticated)\n\tby conssluserg-03.nifty.com with ESMTP id v9B9dTKj019564;\n\tWed, 11 Oct 2017 18:39:30 +0900","by mail-qt0-f181.google.com with SMTP id x54so3302327qth.12;\n\tWed, 11 Oct 2017 02:39:30 -0700 (PDT)","by 10.237.61.199 with HTTP; Wed, 11 Oct 2017 02:38:48 -0700 (PDT)"],"DKIM-Filter":"OpenDKIM Filter v2.10.3 conssluserg-03.nifty.com v9B9dTKj019564","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com;\n\ts=dec2015msa; t=1507714770;\n\tbh=OzTJexCurI+OiXXDJiRm1Is2luFooJh+MOS7k4l/QfI=;\n\th=In-Reply-To:References:From:Date:Subject:To:Cc:From;\n\tb=kkLm+BjC5uX0Sd7YsGtsVCeifEoCy1zI5pXnCQtqqMuLIh4nuvL73GBCHNBzzEwf+\n\tJ3SWemdLLM9TXId2zaWoO7dPOZYYrquHDrB8FbNv+6YEv5RQ30Q4aAOoXcqBL0gj1G\n\tpj+oFXpR1AkxpI14Imh/z0I3eKHFAo3lmO54U0R8sV39vwUL9d0YzACWKzI5ylJ7qN\n\tj0jNNZimnOHpp+VLnHyz3GnTOeVe77JwQAH+N4zcZWBO0ZRUpcLJ8obq8C/IYCVPNs\n\tQweZI4fr2f6R1Hzq5KfNQGg2ahhjotjTtg/wdQzDbbgyt2ChG6jTjzPt6WrwzbJUVH\n\tAxdpdMtuhTX2w==","X-Nifty-SrcIP":"[209.85.216.181]","X-Gm-Message-State":"AMCzsaVJZ+CROKUgoDV+GDD2NYPyIIUj/xRQPy9vDEX4Exq32KQ+jYkA\n\t05RLObDp4siaCJY4Mfj5OfzJihVdBxlugJrHWhc=","X-Google-Smtp-Source":"AOwi7QBXpM8jjwnP5xIYqpW8zHWumJvO2Wa9bJ3uADo743SfMUmumuC+wInhH3M4Wp6yKOtq/8zuxR7Bn6eBxQAfoNg=","X-Received":"by 10.55.178.65 with SMTP id b62mr18517397qkf.348.1507714769193; \n\tWed, 11 Oct 2017 02:39:29 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"","References":"<1506480022-8995-1-git-send-email-yamada.masahiro@socionext.com>\n\t<1506480022-8995-3-git-send-email-yamada.masahiro@socionext.com>\n\t","From":"Masahiro Yamada ","Date":"Wed, 11 Oct 2017 18:38:48 +0900","X-Gmail-Original-Message-ID":"","Message-ID":"","Subject":"Re: [PATCH v6 2/2] gpio: uniphier: add UniPhier GPIO controller\n\tdriver","To":"Linus Walleij ","Cc":"\"linux-gpio@vger.kernel.org\" ,\n\t\"devicetree@vger.kernel.org\" ,\n\tRob Herring , Masami Hiramatsu ,\n\tJassi Brar ,\n\tMauro Carvalho Chehab ,\n\tRandy Dunlap ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\t\"David S. Miller\" ,\n\tRob Herring , \n\tGreg Kroah-Hartman ,\n\tMark Rutland ,\n\t\"linux-arm-kernel@lists.infradead.org\" \n\t","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]