[{"id":1776066,"web_url":"http://patchwork.ozlabs.org/comment/1776066/","msgid":"<20170927085318.0670a849@xps13>","list_archive_url":null,"date":"2017-09-27T06:53:18","subject":"Re: [PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","submitter":{"id":71917,"url":"http://patchwork.ozlabs.org/api/people/71917/","name":"Miquel Raynal","email":"miquel.raynal@free-electrons.com"},"content":"Hello Kalyan,\n\nOn Wed, 27 Sep 2017 13:55:16 +1300\nKalyan Kinthada wrote:\n\n> When the arbitration between NOR and NAND flash is enabled\n> the field bit[21] in the Data Flash Control Register\n> needs to be set to 1 according to guidleine GL-5830741.\n> \n> This commit sets the FORCE_CSX bit to 1 for all\n> ARMADA370 variants as the arbitration is always enabled by default.\n\nMaybe you could mention here that this does not apply for pxa3xx\nvariant as this bit does not exist/is reserved on the NFCv1.\n\n> \n> Signed-off-by: Kalyan Kinthada \n> ---\n> drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++\n> 1 file changed, 7 insertions(+)\n> \n> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..b2753eea567c\n> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n> @@ -68,6 +68,7 @@\n> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n> #define NDCR_NCSX\t\t(0x1 << 23)\n> #define NDCR_ND_MODE\t\t(0x3 << 21)\n> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n> #define NDCR_NAND_MODE \t(0x0)\n\nThe three lines above seems to have the same purpose.\nI had a look to the specs (pxa/370/375/xp/380/390), and I could\nnot find any reference to a valid bit 22 in NDCR (it is always\nreserved). Maybe you could delete NDCR_ND_MODE and\nNDCR_NAND_MODE then ?\n\n> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n> @@ -1464,6 +1465,9 @@ static int pxa3xx_nand_config_ident(struct\n> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN :\n> 0;\n> +\t/* Set FORCE_CSX bit for all ARMADAGL-5830741370 Variants.\n> Ref#: GL-5830741*/\n\nYou miss a space between \"GL-5830741\" and \"*/\".\n\n> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n> \n> @@ -1498,6 +1502,9 @@ static void pxa3xx_nand_detect_config(struct\n> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n> NDCR_ND_ARB_EN : 0;\n> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n> GL-5830741*/\n\nSame here.\n\n> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n> }\n\n\nThanks,\nMiquèl","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y27nc0sc2z9t4X\n\tfor ;\n\tWed, 27 Sep 2017 16:53:24 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752112AbdI0GxW convert rfc822-to-8bit (ORCPT\n\t);\n\tWed, 27 Sep 2017 02:53:22 -0400","from mail.free-electrons.com ([62.4.15.54]:51113 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751276AbdI0GxV (ORCPT\n\t); Wed, 27 Sep 2017 02:53:21 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 1D632208BA; Wed, 27 Sep 2017 08:53:19 +0200 (CEST)","from xps13 (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id B69D0208A8;\n\tWed, 27 Sep 2017 08:53:18 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Wed, 27 Sep 2017 08:53:18 +0200","From":"Miquel RAYNAL ","To":"Kalyan Kinthada ","Cc":"dwmw2@infradead.org, computersforpeace@gmail.com,\n\tboris.brezillon@free-electrons.com, marek.vasut@gmail.com,\n\trichard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,\n\tmark.rutland@arm.com, ezequiel.garcia@free-electrons.com,\n\tdevicetree@vger.kernel.org, linux-mtd@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, chris.packham@alliedtelesis.co.nz","Subject":"Re: [PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","Message-ID":"<20170927085318.0670a849@xps13>","In-Reply-To":"<20170927005516.28374-2-kalyan.kinthada@alliedtelesis.co.nz>","References":"<20170927005516.28374-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170927005516.28374-2-kalyan.kinthada@alliedtelesis.co.nz>","Organization":"Free Electrons","X-Mailer":"Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8BIT","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776171,"web_url":"http://patchwork.ozlabs.org/comment/1776171/","msgid":"<20170927111547.3536eb2b@xps13>","list_archive_url":null,"date":"2017-09-27T09:15:47","subject":"Re: [PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","submitter":{"id":71917,"url":"http://patchwork.ozlabs.org/api/people/71917/","name":"Miquel Raynal","email":"miquel.raynal@free-electrons.com"},"content":"On Wed, 27 Sep 2017 08:53:18 +0200\nMiquel RAYNAL wrote:\n\n> Hello Kalyan,\n> \n> On Wed, 27 Sep 2017 13:55:16 +1300\n> Kalyan Kinthada wrote:\n> \n> > When the arbitration between NOR and NAND flash is enabled\n> > the field bit[21] in the Data Flash Control Register\n> > needs to be set to 1 according to guidleine GL-5830741.\n\nI forgot to ask you what is this guideline ? Is this a Marvell\ndocument ? I could not find it. The functional spec clearly states:\n\"When NOR/NAND hardware arbiter enabled, this bit must be set\" but as\nyou mention it in the commit log and in the code it is worth knowing\nwhat your are referring to.\n\nAlso, could you test if this bit introduces a regression or a speed\npenalty when using for instance only one NAND chip (so not using\nthe arbiter even if it is enabled) ?\n\nTo do so you may use the flash_speed tool from the mtd-utils package:\nhttp://lists.infradead.org/pipermail/linux-mtd/2017-August/076477.html\n\nThank you,\nMiquèl\n\n> > \n> > This commit sets the FORCE_CSX bit to 1 for all\n> > ARMADA370 variants as the arbitration is always enabled by\n> > default. \n> \n> Maybe you could mention here that this does not apply for pxa3xx\n> variant as this bit does not exist/is reserved on the NFCv1.\n> \n> > \n> > Signed-off-by: Kalyan Kinthada \n> > ---\n> > drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++\n> > 1 file changed, 7 insertions(+)\n> > \n> > diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n> > b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..b2753eea567c\n> > 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n> > +++ b/drivers/mtd/nand/pxa3xx_nand.c\n> > @@ -68,6 +68,7 @@\n> > #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n> > #define NDCR_NCSX\t\t(0x1 << 23)\n> > #define NDCR_ND_MODE\t\t(0x3 << 21)\n> > +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n> > #define NDCR_NAND_MODE \t(0x0) \n> \n> The three lines above seems to have the same purpose.\n> I had a look to the specs (pxa/370/375/xp/380/390), and I could\n> not find any reference to a valid bit 22 in NDCR (it is always\n> reserved). Maybe you could delete NDCR_ND_MODE and\n> NDCR_NAND_MODE then ?\n> \n> > #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n> > #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n> > @@ -1464,6 +1465,9 @@ static int pxa3xx_nand_config_ident(struct\n> > pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n> > \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n> > \tinfo->reg_ndcr |= (pdata->enable_arbiter) ?\n> > NDCR_ND_ARB_EN : 0;\n> > +\t/* Set FORCE_CSX bit for all ARMADAGL-5830741370 Variants.\n> > Ref#: GL-5830741*/ \n> \n> You miss a space between \"GL-5830741\" and \"*/\".\n> \n> > +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> > +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> > \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n> > \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n> > \n> > @@ -1498,6 +1502,9 @@ static void pxa3xx_nand_detect_config(struct\n> > pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n> > \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n> > NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n> > NDCR_ND_ARB_EN : 0;\n> > +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n> > GL-5830741*/ \n> \n> Same here.\n> \n> > +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n> > +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n> > \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n> > \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n> > } \n> \n> \n> Thanks,\n> Miquèl\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2By23ZW1z9tXn\n\tfor ;\n\tWed, 27 Sep 2017 19:15:54 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752453AbdI0JPv convert rfc822-to-8bit (ORCPT\n\t);\n\tWed, 27 Sep 2017 05:15:51 -0400","from mail.free-electrons.com ([62.4.15.54]:56154 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751787AbdI0JPu (ORCPT\n\t); Wed, 27 Sep 2017 05:15:50 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid C87AF208C5; Wed, 27 Sep 2017 11:15:47 +0200 (CEST)","from xps13 (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 5E2EF208B6;\n\tWed, 27 Sep 2017 11:15:47 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Wed, 27 Sep 2017 11:15:47 +0200","From":"Miquel RAYNAL ","To":"Kalyan Kinthada ","Cc":"dwmw2@infradead.org, computersforpeace@gmail.com,\n\tboris.brezillon@free-electrons.com, marek.vasut@gmail.com,\n\trichard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,\n\tmark.rutland@arm.com, ezequiel.garcia@free-electrons.com,\n\tdevicetree@vger.kernel.org, linux-mtd@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, chris.packham@alliedtelesis.co.nz","Subject":"Re: [PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","Message-ID":"<20170927111547.3536eb2b@xps13>","In-Reply-To":"<20170927085318.0670a849@xps13>","References":"<20170927005516.28374-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170927005516.28374-2-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170927085318.0670a849@xps13>","Organization":"Free Electrons","X-Mailer":"Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8BIT","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776646,"web_url":"http://patchwork.ozlabs.org/comment/1776646/","msgid":"","list_archive_url":null,"date":"2017-09-27T21:53:39","subject":"Re: [PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370\n\tvariants.","submitter":{"id":27499,"url":"http://patchwork.ozlabs.org/api/people/27499/","name":"Chris Packham","email":"chris.packham@alliedtelesis.co.nz"},"content":"Hi Miquel,\n\nOn 27/09/17 22:16, Miquel RAYNAL wrote:\n> On Wed, 27 Sep 2017 08:53:18 +0200\n> Miquel RAYNAL wrote:\n> \n>> Hello Kalyan,\n>>\n>> On Wed, 27 Sep 2017 13:55:16 +1300\n>> Kalyan Kinthada wrote:\n>>\n>>> When the arbitration between NOR and NAND flash is enabled\n>>> the field bit[21] in the Data Flash Control Register\n>>> needs to be set to 1 according to guidleine GL-5830741.\n> \n> I forgot to ask you what is this guideline ? Is this a Marvell\n> document ? I could not find it. The functional spec clearly states:\n> \"When NOR/NAND hardware arbiter enabled, this bit must be set\" but as\n> you mention it in the commit log and in the code it is worth knowing\n> what your are referring to.\n\nThe guideline number is from a Marvell Errata document MV-S501377-00, \nalthough this specific change is a guideline not an erratum. You'll need \naccess to Marvell's extranet (with appropriate NDAs etc) to retrieve it. \nWe can mention the document reference in the commit message for v3.\n\n> Also, could you test if this bit introduces a regression or a speed\n> penalty when using for instance only one NAND chip (so not using\n> the arbiter even if it is enabled) ?\n> \n> To do so you may use the flash_speed tool from the mtd-utils package:\n> http://lists.infradead.org/pipermail/linux-mtd/2017-August/076477.html\n\nWe haven't run flash_speed (yet) but anecdotally we've seen no \nnoticeable performance difference.\n\n> \n> Thank you,\n> Miquèl\n> \n>>>\n>>> This commit sets the FORCE_CSX bit to 1 for all\n>>> ARMADA370 variants as the arbitration is always enabled by\n>>> default.\n>>\n>> Maybe you could mention here that this does not apply for pxa3xx\n>> variant as this bit does not exist/is reserved on the NFCv1.\n>>\n>>>\n>>> Signed-off-by: Kalyan Kinthada \n>>> ---\n>>> drivers/mtd/nand/pxa3xx_nand.c | 7 +++++++\n>>> 1 file changed, 7 insertions(+)\n>>>\n>>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n>>> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..b2753eea567c\n>>> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n>>> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n>>> @@ -68,6 +68,7 @@\n>>> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n>>> #define NDCR_NCSX\t\t(0x1 << 23)\n>>> #define NDCR_ND_MODE\t\t(0x3 << 21)\n>>> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n>>> #define NDCR_NAND_MODE \t(0x0)\n>>\n>> The three lines above seems to have the same purpose.\n>> I had a look to the specs (pxa/370/375/xp/380/390), and I could\n>> not find any reference to a valid bit 22 in NDCR (it is always\n>> reserved). Maybe you could delete NDCR_ND_MODE and\n>> NDCR_NAND_MODE then ?\n>>\n>>> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n>>> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n>>> @@ -1464,6 +1465,9 @@ static int pxa3xx_nand_config_ident(struct\n>>> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n>>> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n>>> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ?\n>>> NDCR_ND_ARB_EN : 0;\n>>> +\t/* Set FORCE_CSX bit for all ARMADAGL-5830741370 Variants.\n>>> Ref#: GL-5830741*/\n>>\n>> You miss a space between \"GL-5830741\" and \"*/\".\n>>\n>>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n>>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n>>> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n>>> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n>>> \n>>> @@ -1498,6 +1502,9 @@ static void pxa3xx_nand_detect_config(struct\n>>> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n>>> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n>>> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n>>> NDCR_ND_ARB_EN : 0;\n>>> +\t/* Set FORCE_CSX bit for all ARMADA370 Variants. Ref#:\n>>> GL-5830741*/\n>>\n>> Same here.\n>>\n>>> +\tif (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)\n>>> +\t\tinfo->reg_ndcr |= NDCR_FORCE_CSX;\n>>> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n>>> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n>>> }\n>>\n>>\n>> Thanks,\n>> Miquèl\n>>\n> \n> \n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=alliedtelesis.co.nz\n\theader.i=@alliedtelesis.co.nz\n\theader.b=\"Y90ZdihW\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2Wmk1djqz9t6B\n\tfor ;\n\tThu, 28 Sep 2017 07:53:58 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752445AbdI0Vxo (ORCPT\n\t);\n\tWed, 27 Sep 2017 17:53:44 -0400","from gate2.alliedtelesis.co.nz ([202.36.163.20]:51773 \"EHLO\n\tgate2.alliedtelesis.co.nz\" rhost-flags-OK-OK-OK-OK) by\n\tvger.kernel.org with ESMTP id S1752231AbdI0Vxn (ORCPT\n\t); Wed, 27 Sep 2017 17:53:43 -0400","from mmarshal3.atlnz.lc (mmarshal3.atlnz.lc [10.32.18.43])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (Client did not present a certificate)\n\tby gate2.alliedtelesis.co.nz (Postfix) with ESMTPS id 8CF6B8365D;\n\tThu, 28 Sep 2017 10:53:40 +1300 (NZDT)","from svr-chch-ex1.atlnz.lc (Not Verified[10.32.16.77]) by\n\tmmarshal3.atlnz.lc with Trustwave SEG (v7, 5, 8, 10121)\n\tid ; Thu, 28 Sep 2017 10:53:40 +1300","from svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8:409d:36f5:8899:92e8)\n\tby svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8:409d:36f5:8899:92e8)\n\twith Microsoft SMTP Server (TLS) id 15.0.1156.6;\n\tThu, 28 Sep 2017 10:53:40 +1300","from svr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8]) by\n\tsvr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8%12]) with mapi id\n\t15.00.1156.000; Thu, 28 Sep 2017 10:53:40 +1300"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=alliedtelesis.co.nz; \n\ts=mail; t=1506549220;\n\tbh=TF1eDMQ6XcONFT1uTAYs8ceGlGf7kERWq5DH7d1pGMY=;\n\th=From:To:CC:Subject:Date:References;\n\tb=Y90ZdihW5aTpwaWRXGptVcX8nd5jm8Qd4su/cQSk210k/VAqA3IYcjPygY91CJJZ2\n\tNcRn7SO4HmzuFwwl6aBOrwS6IkkYV3NqkWVhgNhG7pysv6QPr1Cnz/9lKXgVuocLNB\n\tYJ3c5HemBt5jphAytAB+VdlLewKK6ipuKmKzZcpM=","From":"Chris Packham ","To":"Miquel RAYNAL ,\n\tKalyan Kinthada ","CC":"\"dwmw2@infradead.org\" ,\n\t\"computersforpeace@gmail.com\" ,\n\t\"boris.brezillon@free-electrons.com\"\n\t, \n\t\"marek.vasut@gmail.com\" ,\n\t\"richard@nod.at\" ,\n\t\"cyrille.pitchen@wedev4u.fr\" ,\n\t\"robh+dt@kernel.org\" ,\n\t\"mark.rutland@arm.com\" ,\n\t\"ezequiel.garcia@free-electrons.com\"\n\t, \n\t\"devicetree@vger.kernel.org\" ,\n\t\"linux-mtd@lists.infradead.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ","Subject":"Re: [PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370\n\tvariants.","Thread-Topic":"[PATCH v2 1/1] mtd: nand: pxa3xx: Set FORCE_CSX bit to\n\tARMADA370 variants.","Thread-Index":"AQHTNytLUtKhATKjOUqNtrev7jsPFQ==","Date":"Wed, 27 Sep 2017 21:53:39 +0000","Message-ID":"","References":"<20170927005516.28374-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170927005516.28374-2-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170927085318.0670a849@xps13> <20170927111547.3536eb2b@xps13>","Accept-Language":"en-NZ, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-ms-exchange-transport-fromentityheader":"Hosted","x-originating-ip":"[10.32.1.10]","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","MIME-Version":"1.0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]