[{"id":1776870,"web_url":"http://patchwork.ozlabs.org/comment/1776870/","msgid":"<20170928083827.GE23750@n2100.armlinux.org.uk>","list_archive_url":null,"date":"2017-09-28T08:38:27","subject":"Re: [PATCH v4 2/2] memory: ti-emif-sram: introduce relocatable\n\tsuspend/resume handlers","submitter":{"id":69080,"url":"http://patchwork.ozlabs.org/api/people/69080/","name":"Russell King (Oracle)","email":"linux@armlinux.org.uk"},"content":"On Tue, Sep 26, 2017 at 07:03:55PM -0500, Dave Gerlach wrote:\n> diff --git a/drivers/memory/emif-asm-offsets.c b/drivers/memory/emif-asm-offsets.c\n> new file mode 100644\n> index 000000000000..bdb153c9e948\n> --- /dev/null\n> +++ b/drivers/memory/emif-asm-offsets.c\n> @@ -0,0 +1,22 @@\n> +/*\n> + * TI AM33XX EMIF PM Assembly Offsets\n> + *\n> + * Copyright (C) 2016-2017 Texas Instruments Inc.\n> + *\n> + * This program is free software; you can redistribute it and/or\n> + * modify it under the terms of the GNU General Public License as\n> + * published by the Free Software Foundation version 2.\n> + *\n> + * This program is distributed \"as is\" WITHOUT ANY WARRANTY of any\n> + * kind, whether express or implied; without even the implied warranty\n> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n> + * GNU General Public License for more details.\n> + */\n> +#include \n> +\n> +int main(void)\n> +{\n> +\tti_emif_offsets();\n> +\n> +\treturn 0;\n> +}\n\n...\n\n> +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)\n> +static inline void ti_emif_offsets(void)\n> +{\n> +\tDEFINE(EMIF_SDCFG_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_sdcfg_val));\n> +\tDEFINE(EMIF_TIMING1_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_timing1_val));\n> +\tDEFINE(EMIF_TIMING2_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_timing2_val));\n> +\tDEFINE(EMIF_TIMING3_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_timing3_val));\n> +\tDEFINE(EMIF_REF_CTRL_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));\n> +\tDEFINE(EMIF_ZQCFG_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_zqcfg_val));\n> +\tDEFINE(EMIF_PMCR_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_pmcr_val));\n> +\tDEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));\n> +\tDEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));\n> +\tDEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));\n> +\tDEFINE(EMIF_COS_CONFIG_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_cos_config));\n> +\tDEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));\n> +\tDEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));\n> +\tDEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));\n> +\tDEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_ocp_config_val));\n> +\tDEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));\n> +\tDEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));\n> +\tDEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));\n> +\tDEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));\n> +\tDEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));\n> +\tDEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,\n> +\t offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));\n> +\tDEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));\n> +\n> +\tBLANK();\n> +\n> +\tDEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,\n> +\t offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));\n> +\tDEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,\n> +\t offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));\n> +\tDEFINE(EMIF_PM_CONFIG_OFFSET,\n> +\t offsetof(struct ti_emif_pm_data, ti_emif_sram_config));\n> +\tDEFINE(EMIF_PM_REGS_VIRT_OFFSET,\n> +\t offsetof(struct ti_emif_pm_data, regs_virt));\n> +\tDEFINE(EMIF_PM_REGS_PHYS_OFFSET,\n> +\t offsetof(struct ti_emif_pm_data, regs_phys));\n> +\tDEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));\n> +\n> +\tBLANK();\n> +\n> +\tDEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,\n> +\t offsetof(struct ti_emif_pm_functions, save_context));\n> +\tDEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,\n> +\t offsetof(struct ti_emif_pm_functions, restore_context));\n> +\tDEFINE(EMIF_PM_ENTER_SR_OFFSET,\n> +\t offsetof(struct ti_emif_pm_functions, enter_sr));\n> +\tDEFINE(EMIF_PM_EXIT_SR_OFFSET,\n> +\t offsetof(struct ti_emif_pm_functions, exit_sr));\n> +\tDEFINE(EMIF_PM_ABORT_SR_OFFSET,\n> +\t offsetof(struct ti_emif_pm_functions, abort_sr));\n> +\tDEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));\n> +}\n> +#else\n> +static inline void ti_emif_offsets(void) {}\n> +#endif\n\nAny reason the above can't be part of emif-asm-offsets.c ?","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778418,"web_url":"http://patchwork.ozlabs.org/comment/1778418/","msgid":"<0bbba52e-c7d8-647e-9b58-55cbbe236d4a@ti.com>","list_archive_url":null,"date":"2017-10-02T15:34:18","subject":"Re: [PATCH v4 2/2] memory: ti-emif-sram: introduce relocatable\n\tsuspend/resume handlers","submitter":{"id":61863,"url":"http://patchwork.ozlabs.org/api/people/61863/","name":"Dave Gerlach","email":"d-gerlach@ti.com"},"content":"Russell,\nOn 09/28/2017 03:38 AM, Russell King - ARM Linux wrote:\n> On Tue, Sep 26, 2017 at 07:03:55PM -0500, Dave Gerlach wrote:\n>> diff --git a/drivers/memory/emif-asm-offsets.c b/drivers/memory/emif-asm-offsets.c\n>> new file mode 100644\n>> index 000000000000..bdb153c9e948\n>> --- /dev/null\n>> +++ b/drivers/memory/emif-asm-offsets.c\n>> @@ -0,0 +1,22 @@\n>> +/*\n>> + * TI AM33XX EMIF PM Assembly Offsets\n>> + *\n>> + * Copyright (C) 2016-2017 Texas Instruments Inc.\n>> + *\n>> + * This program is free software; you can redistribute it and/or\n>> + * modify it under the terms of the GNU General Public License as\n>> + * published by the Free Software Foundation version 2.\n>> + *\n>> + * This program is distributed \"as is\" WITHOUT ANY WARRANTY of any\n>> + * kind, whether express or implied; without even the implied warranty\n>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n>> + * GNU General Public License for more details.\n>> + */\n>> +#include \n>> +\n>> +int main(void)\n>> +{\n>> +\tti_emif_offsets();\n>> +\n>> +\treturn 0;\n>> +}\n> \n> ...\n> \n>> +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)\n>> +static inline void ti_emif_offsets(void)\n>> +{\n>> +\tDEFINE(EMIF_SDCFG_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_sdcfg_val));\n>> +\tDEFINE(EMIF_TIMING1_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_timing1_val));\n>> +\tDEFINE(EMIF_TIMING2_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_timing2_val));\n>> +\tDEFINE(EMIF_TIMING3_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_timing3_val));\n>> +\tDEFINE(EMIF_REF_CTRL_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));\n>> +\tDEFINE(EMIF_ZQCFG_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_zqcfg_val));\n>> +\tDEFINE(EMIF_PMCR_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_pmcr_val));\n>> +\tDEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));\n>> +\tDEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));\n>> +\tDEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));\n>> +\tDEFINE(EMIF_COS_CONFIG_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_cos_config));\n>> +\tDEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));\n>> +\tDEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));\n>> +\tDEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));\n>> +\tDEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_ocp_config_val));\n>> +\tDEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));\n>> +\tDEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));\n>> +\tDEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));\n>> +\tDEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));\n>> +\tDEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));\n>> +\tDEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,\n>> +\t offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));\n>> +\tDEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));\n>> +\n>> +\tBLANK();\n>> +\n>> +\tDEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));\n>> +\tDEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));\n>> +\tDEFINE(EMIF_PM_CONFIG_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_data, ti_emif_sram_config));\n>> +\tDEFINE(EMIF_PM_REGS_VIRT_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_data, regs_virt));\n>> +\tDEFINE(EMIF_PM_REGS_PHYS_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_data, regs_phys));\n>> +\tDEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));\n>> +\n>> +\tBLANK();\n>> +\n>> +\tDEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_functions, save_context));\n>> +\tDEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_functions, restore_context));\n>> +\tDEFINE(EMIF_PM_ENTER_SR_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_functions, enter_sr));\n>> +\tDEFINE(EMIF_PM_EXIT_SR_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_functions, exit_sr));\n>> +\tDEFINE(EMIF_PM_ABORT_SR_OFFSET,\n>> +\t offsetof(struct ti_emif_pm_functions, abort_sr));\n>> +\tDEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));\n>> +}\n>> +#else\n>> +static inline void ti_emif_offsets(void) {}\n>> +#endif\n> \n> Any reason the above can't be part of emif-asm-offsets.c ?\n> \n\nYes that's a good point. I was focused on moving the macros and didn't think\nabout why I hid everything away in the header in the first place, to avoid\ncluttering the global asm-offsets.c. Now that we have our own file there's no\nreason for this, I will fix this and the kbuild robot issue and send v5. I can\nsimplify the makefile more which will avoid that build error.\n\nRegards,\nDave","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"LbmThM67\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"SCAAoCWd\"; \n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y5R7N63j7z9t6m\n\tfor ;\n\tTue, 3 Oct 2017 02:35:12 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dz2kO-00023G-Pg; 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bh=ql1xgfeI0nRsMXhoZsYACbjyxgYTG5a4iq1MZZi15n8=;\n\tb=LbmThM671ybx7m\n\tisFm72yzqTIEEnXHS2Mj4C6jSp+IkovJBQ3hRAlRj+mSokrNmj/4qTadOF+yBVYAhSdF/FHZsfuX9\n\t1oaQGj3RTh+qCTeAtUnz42p0z+rHnUzFmV9V1cQlK/fll70w/sGexXzdBuh+X0baWyQQjoy42oUKT\n\t32OqWFVzRdGRVwcQuuNkYw757zSuDbbB8W/An7Xzu6UvNwFGOMgUtS78hcBspqXYx51mIgYyd3f5o\n\t2RUAoAuezxKiQ+zOAb2vDzi43GB6/ayLDTlt64qFqawRicvQJyVYKYdmTnUAkUlxPByGdwyXkW4yZ\n\tOY61jLzkqZWNSqizRQdg==;","v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506958458;\n\tbh=kwwl3PKOMbiC7+g6S0dK/Y6z94jVuw3DoTItTUbX/B8=;\n\th=Subject:To:References:CC:From:Date:In-Reply-To;\n\tb=SCAAoCWdm/iGx2GRZiep4K7KUsIF6SulUe/8brWx0av+6kG2du9FNoXaLEpXD+bLy\n\tehU0nHoVSUcrUQ37n2rDKpRnlmFROd+uE7RPoQ4CNXpeOoXWhk1q1HakYxI1QkjEqD\n\tPcCJzZlpJj3gKzV/J+VLY3F2bvKpmoGlBtCzJp28="],"Subject":"Re: [PATCH v4 2/2] memory: ti-emif-sram: introduce relocatable\n\tsuspend/resume handlers","To":"Russell King - ARM Linux ","References":"<20170927000355.30597-1-d-gerlach@ti.com>\n\t<20170927000355.30597-3-d-gerlach@ti.com>\n\t<20170928083827.GE23750@n2100.armlinux.org.uk>","From":"Dave Gerlach ","Message-ID":"<0bbba52e-c7d8-647e-9b58-55cbbe236d4a@ti.com>","Date":"Mon, 2 Oct 2017 10:34:18 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.5.1","MIME-Version":"1.0","In-Reply-To":"<20170928083827.GE23750@n2100.armlinux.org.uk>","X-Originating-IP":"[128.247.59.203]","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171002_083500_591743_5DC2B014 ","X-CRM114-Status":"GOOD ( 12.48 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [198.47.19.17 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Tony Lindgren ,\n\tKeerthy J , linux-kernel@vger.kernel.org,\n\tJohan Hovold , Rob Herring ,\n\tSantosh Shilimkar , linux-omap@vger.kernel.org, \n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1779064,"web_url":"http://patchwork.ozlabs.org/comment/1779064/","msgid":"<169e5257-3e05-3c61-32ae-27b34123859c@ti.com>","list_archive_url":null,"date":"2017-10-03T15:14:23","subject":"Re: [PATCH v4 2/2] memory: ti-emif-sram: introduce relocatable\n\tsuspend/resume handlers","submitter":{"id":61863,"url":"http://patchwork.ozlabs.org/api/people/61863/","name":"Dave Gerlach","email":"d-gerlach@ti.com"},"content":"On 10/02/2017 10:34 AM, Dave Gerlach wrote:\n> Russell,\n> On 09/28/2017 03:38 AM, Russell King - ARM Linux wrote:\n>> On Tue, Sep 26, 2017 at 07:03:55PM -0500, Dave Gerlach wrote:\n>>> diff --git a/drivers/memory/emif-asm-offsets.c b/drivers/memory/emif-asm-offsets.c\n>>> new file mode 100644\n>>> index 000000000000..bdb153c9e948\n>>> --- /dev/null\n>>> +++ b/drivers/memory/emif-asm-offsets.c\n>>> @@ -0,0 +1,22 @@\n>>> +/*\n>>> + * TI AM33XX EMIF PM Assembly Offsets\n>>> + *\n>>> + * Copyright (C) 2016-2017 Texas Instruments Inc.\n>>> + *\n>>> + * This program is free software; you can redistribute it and/or\n>>> + * modify it under the terms of the GNU General Public License as\n>>> + * published by the Free Software Foundation version 2.\n>>> + *\n>>> + * This program is distributed \"as is\" WITHOUT ANY WARRANTY of any\n>>> + * kind, whether express or implied; without even the implied warranty\n>>> + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n>>> + * GNU General Public License for more details.\n>>> + */\n>>> +#include \n>>> +\n>>> +int main(void)\n>>> +{\n>>> +\tti_emif_offsets();\n>>> +\n>>> +\treturn 0;\n>>> +}\n>>\n>> ...\n>>\n>>> +#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)\n>>> +static inline void ti_emif_offsets(void)\n>>> +{\n>>> +\tDEFINE(EMIF_SDCFG_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_sdcfg_val));\n>>> +\tDEFINE(EMIF_TIMING1_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_timing1_val));\n>>> +\tDEFINE(EMIF_TIMING2_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_timing2_val));\n>>> +\tDEFINE(EMIF_TIMING3_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_timing3_val));\n>>> +\tDEFINE(EMIF_REF_CTRL_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_ref_ctrl_val));\n>>> +\tDEFINE(EMIF_ZQCFG_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_zqcfg_val));\n>>> +\tDEFINE(EMIF_PMCR_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_pmcr_val));\n>>> +\tDEFINE(EMIF_PMCR_SHDW_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_pmcr_shdw_val));\n>>> +\tDEFINE(EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_rd_wr_level_ramp_ctrl));\n>>> +\tDEFINE(EMIF_RD_WR_EXEC_THRESH_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_rd_wr_exec_thresh));\n>>> +\tDEFINE(EMIF_COS_CONFIG_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_cos_config));\n>>> +\tDEFINE(EMIF_PRIORITY_TO_COS_MAPPING_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_priority_to_cos_mapping));\n>>> +\tDEFINE(EMIF_CONNECT_ID_SERV_1_MAP_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_connect_id_serv_1_map));\n>>> +\tDEFINE(EMIF_CONNECT_ID_SERV_2_MAP_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_connect_id_serv_2_map));\n>>> +\tDEFINE(EMIF_OCP_CONFIG_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_ocp_config_val));\n>>> +\tDEFINE(EMIF_LPDDR2_NVM_TIM_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim));\n>>> +\tDEFINE(EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_lpddr2_nvm_tim_shdw));\n>>> +\tDEFINE(EMIF_DLL_CALIB_CTRL_VAL_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val));\n>>> +\tDEFINE(EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_dll_calib_ctrl_val_shdw));\n>>> +\tDEFINE(EMIF_DDR_PHY_CTLR_1_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_ddr_phy_ctlr_1));\n>>> +\tDEFINE(EMIF_EXT_PHY_CTRL_VALS_OFFSET,\n>>> +\t offsetof(struct emif_regs_amx3, emif_ext_phy_ctrl_vals));\n>>> +\tDEFINE(EMIF_REGS_AMX3_SIZE, sizeof(struct emif_regs_amx3));\n>>> +\n>>> +\tBLANK();\n>>> +\n>>> +\tDEFINE(EMIF_PM_BASE_ADDR_VIRT_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_data, ti_emif_base_addr_virt));\n>>> +\tDEFINE(EMIF_PM_BASE_ADDR_PHYS_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_data, ti_emif_base_addr_phys));\n>>> +\tDEFINE(EMIF_PM_CONFIG_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_data, ti_emif_sram_config));\n>>> +\tDEFINE(EMIF_PM_REGS_VIRT_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_data, regs_virt));\n>>> +\tDEFINE(EMIF_PM_REGS_PHYS_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_data, regs_phys));\n>>> +\tDEFINE(EMIF_PM_DATA_SIZE, sizeof(struct ti_emif_pm_data));\n>>> +\n>>> +\tBLANK();\n>>> +\n>>> +\tDEFINE(EMIF_PM_SAVE_CONTEXT_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_functions, save_context));\n>>> +\tDEFINE(EMIF_PM_RESTORE_CONTEXT_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_functions, restore_context));\n>>> +\tDEFINE(EMIF_PM_ENTER_SR_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_functions, enter_sr));\n>>> +\tDEFINE(EMIF_PM_EXIT_SR_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_functions, exit_sr));\n>>> +\tDEFINE(EMIF_PM_ABORT_SR_OFFSET,\n>>> +\t offsetof(struct ti_emif_pm_functions, abort_sr));\n>>> +\tDEFINE(EMIF_PM_FUNCTIONS_SIZE, sizeof(struct ti_emif_pm_functions));\n>>> +}\n>>> +#else\n>>> +static inline void ti_emif_offsets(void) {}\n>>> +#endif\n>>\n>> Any reason the above can't be part of emif-asm-offsets.c ?\n>>\n> \n> Yes that's a good point. I was focused on moving the macros and didn't think\n> about why I hid everything away in the header in the first place, to avoid\n> cluttering the global asm-offsets.c. Now that we have our own file there's no\n> reason for this, I will fix this and the kbuild robot issue and send v5. I can\n> simplify the makefile more which will avoid that build error.\n\nOn second thought, perhaps it is best we keep these offsets in the header so\nthat they can be easily included for generation in the pm-asm-offsets header.\n\nBefore, everything was generated in the top-level asm-offsets.h so I could\neasily access all macros from ti-emif-sram-pm.S and also the sleep33xx.S found\nhere [1]. Now I can generate emif-asm-offsets.h and pm-asm-offsets.h as separate\nfiles but the sleep33xx.S code requires the macros from both, and because\nemif-asm-offsets.h is generated at build it is hard to describe the build\ndependency from the arch/arm/mach-omap2/Makefile to a generated header in\ndrivers/memory.\n\nThe cleanest solution I have found is to include the emif macros in\npm-asm-offsets.h directly by placing ti_emif_offsets() in the c file used to\ngenerate the PM macros. Next version I send will do it this way unless there is\nan objection.\n\nRegards,\nDave\n\n[1] https://www.spinics.net/lists/arm-kernel/msg595934.html\n\n> \n> Regards,\n> Dave\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"CpCCUMLz\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"SvYOVbv5\"; \n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y62gx4lFkz9sRV\n\tfor ;\n\tWed, 4 Oct 2017 02:17:01 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dzOwM-0006Mb-7v; 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bh=K5nZYc2wx+mEbGe/+SKag8pQgBEq1jIGvQO0XjKDAl8=;\n\tb=CpCCUMLzIc2fdw\n\tZOwY+aAqtavL/xHRG5ZFS5AdB42klRQ5GynX1SbrzV6xcGHfoiyuxotfIRn1UTJqzZ09ncHMtSMal\n\tjOOaeqiFA/HpKXWAYKYSLL2Bs8l1eI5qKyy6dL9pS7Demm0x0wvpsccJkzSuhT3O+LStFhaUts3c1\n\tn9ogHwt1/V3ejd0AQ1fUfozenZBldwUkWdfZRxifBfNgfESiydgj7h1g0F+v70nvpotTlgdsipLEo\n\tfgsjPjVvgmCC0WRbxPCGg7uWB6fzPvtdklczF3tgEkULa0nHbi8ZUgq4YknmLm4ZDR2xh9UymH51D\n\tiJZPfzXFPaia6ZjRUAlg==;","v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1507043724;\n\tbh=NkqO7xVcPLH/UlIYiyFquaRSMgKFMwhOostYPjk+mtU=;\n\th=Subject:To:References:CC:From:Date:In-Reply-To;\n\tb=SvYOVbv5tqZCoJU3Pzjw/6ZVvITaN8SRKbacx0fiUEN7gE6YVNhduFGloUzhMxq7z\n\tkVtxDW+l0rltf5ZfokoXVejfVDF5Zkg57VU4PA/V1BLMrXm23+aKV3aTdKwp1BWYiA\n\tRHdtknNHffDImS2QxxPTrcP0/VGkYE0FkkRtKaQA="],"Subject":"Re: [PATCH v4 2/2] memory: ti-emif-sram: introduce relocatable\n\tsuspend/resume handlers","To":"Russell King - ARM Linux ","References":"<20170927000355.30597-1-d-gerlach@ti.com>\n\t<20170927000355.30597-3-d-gerlach@ti.com>\n\t<20170928083827.GE23750@n2100.armlinux.org.uk>\n\t<0bbba52e-c7d8-647e-9b58-55cbbe236d4a@ti.com>","From":"Dave Gerlach ","Message-ID":"<169e5257-3e05-3c61-32ae-27b34123859c@ti.com>","Date":"Tue, 3 Oct 2017 10:14:23 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.5.1","MIME-Version":"1.0","In-Reply-To":"<0bbba52e-c7d8-647e-9b58-55cbbe236d4a@ti.com>","X-Originating-IP":"[128.247.59.203]","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171003_081650_053991_DB832D27 ","X-CRM114-Status":"GOOD ( 16.12 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [198.47.19.16 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Tony Lindgren ,\n\tKeerthy J , linux-kernel@vger.kernel.org,\n\tJohan Hovold , Rob Herring ,\n\tSantosh Shilimkar , linux-omap@vger.kernel.org, \n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; 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