[{"id":1782612,"web_url":"http://patchwork.ozlabs.org/comment/1782612/","msgid":"<20171009084739.GK2761@lahna.fi.intel.com>","list_archive_url":null,"date":"2017-10-09T08:47:39","subject":"Re: [PATCH 0/7] PCI: Improvements for native PCIe hotplug","submitter":{"id":14534,"url":"http://patchwork.ozlabs.org/api/people/14534/","name":"Mika Westerberg","email":"mika.westerberg@linux.intel.com"},"content":"On Tue, Sep 26, 2017 at 05:17:13PM +0300, Mika Westerberg wrote:\n> Hi,\n> \n> Currently when plugging PCIe device using native PCIe hotplug Linux PCI\n> core tries to allocate bus space and resources so that the newly enumerated\n> topology barely fits there. Now, if the PCIe topology that was just plugged\n> in has more PCIe hotplug ports we will run out of bus space and resources\n> pretty quickly. There is a workaround for this by passing pci=hpbussize=N\n> in the kernel command line but it runs to the same situation after next\n> hotplug.\n\nHi Bjorn,\n\nDo you have any comments regarding this series? I think I need to respin\nthis on top of Andy's for_each_pci_bridge() patch but if there are other\ncomments I can address them at the same time.\n\nThanks!","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y9Yy571Zsz9t6C\n\tfor ;\n\tMon, 9 Oct 2017 19:56:29 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752390AbdJII42 (ORCPT );\n\tMon, 9 Oct 2017 04:56:28 -0400","from mga01.intel.com ([192.55.52.88]:14289 \"EHLO mga01.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751834AbdJII41 (ORCPT );\n\tMon, 9 Oct 2017 04:56:27 -0400","from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t09 Oct 2017 01:56:27 -0700","from lahna.fi.intel.com (HELO lahna) ([10.237.72.157])\n\tby FMSMGA003.fm.intel.com with SMTP; 09 Oct 2017 01:56:23 -0700","by lahna (sSMTP sendmail emulation);\n\tMon, 09 Oct 2017 11:47:39 +0300"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,499,1500966000\"; d=\"scan'208\";a=\"908106263\"","Date":"Mon, 9 Oct 2017 11:47:39 +0300","From":"Mika Westerberg ","To":"Bjorn Helgaas ","Cc":"Ashok Raj , Keith Busch ,\n\t\"Rafael J . Wysocki\" ,\n\tLukas Wunner , Michael Jamet ,\n\tYehezkel Bernat ,\n\tMario.Limonciello@dell.com, linux-pci@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"Re: [PATCH 0/7] PCI: Improvements for native PCIe hotplug","Message-ID":"<20171009084739.GK2761@lahna.fi.intel.com>","References":"<20170926141720.25067-1-mika.westerberg@linux.intel.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170926141720.25067-1-mika.westerberg@linux.intel.com>","Organization":"Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo","User-Agent":"Mutt/1.9.0 (2017-09-02)","Sender":"linux-pci-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-pci@vger.kernel.org"}}]