[{"id":1775204,"web_url":"http://patchwork.ozlabs.org/comment/1775204/","msgid":"<20170926091852.196f647d@xps13>","list_archive_url":null,"date":"2017-09-26T07:18:52","subject":"Re: [PATCH 2/2] mtd: nand: pxa3xx: Handle \"marvell, nand-force-csx\"\n\tcompatible string","submitter":{"id":71917,"url":"http://patchwork.ozlabs.org/api/people/71917/","name":"Miquel Raynal","email":"miquel.raynal@free-electrons.com"},"content":"Hi Kalyan,\n\nOn Tue, 26 Sep 2017 17:17:00 +1300\nKalyan Kinthada wrote:\n\n> When the arbitration between NOR and NAND flash is enabled\n> the field bit[21] in the Data Flash Control Register\n> needs to be set to 1 according to guidleine GL-5830741.\n\nI do agree, the driver lacks the support of this bit, which\nlooks important when you effectively use the arbiter.\nNevertheless:\n\n- On PXA (marvell,pxa3xx-nand compatible), there is a ND_ARB_EN bit to\n enable or disable the arbiter, but there is no FORCE_CSX bit (bit 21\n of NDCR, the so called Control Register, is reserved).\n- On Armada (marvell,armada370-nand), there is a FORCE_CSX bit, but\n there is no ND_ARB_EN bit in the NDCR (moved to system registers) and\n the arbitration is always enabled by default.\n\nI guess you should always set the FORCE_CSX bit when using the armada\ncompatible, because it is harmless, right? Thus, you could get rid\nof the new DT property.\n\nThank you,\nMiquèl\n\n> \n> This commit sets the FORCE_CSX bit to 1 if the compatible\n> string \"marvell,nand-force-csx\" is enabled in the device tree\n> of the corresponding boards.\n> \n> Signed-off-by: Kalyan Kinthada \n> ---\n> drivers/mtd/nand/pxa3xx_nand.c | 6 ++++++\n> include/linux/platform_data/mtd-nand-pxa3xx.h | 3 +++\n> 2 files changed, 9 insertions(+)\n> \n> diff --git a/drivers/mtd/nand/pxa3xx_nand.c\n> b/drivers/mtd/nand/pxa3xx_nand.c index 85cff68643e0..4ad1f0601930\n> 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c\n> +++ b/drivers/mtd/nand/pxa3xx_nand.c\n> @@ -68,6 +68,7 @@\n> #define NDCR_PAGE_SZ\t\t(0x1 << 24)\n> #define NDCR_NCSX\t\t(0x1 << 23)\n> #define NDCR_ND_MODE\t\t(0x3 << 21)\n> +#define NDCR_FORCE_CSX\t\t(0x1 << 21)\n> #define NDCR_NAND_MODE \t(0x0)\n> #define NDCR_CLR_PG_CNT\t\t(0x1 << 20)\n> #define NFCV1_NDCR_ARB_CNTL\t(0x1 << 19)\n> @@ -1464,6 +1465,7 @@ static int pxa3xx_nand_config_ident(struct\n> pxa3xx_nand_info *info) info->chunk_size = PAGE_CHUNK_SIZE;\n> \tinfo->reg_ndcr = 0x0; /* enable all interrupts */\n> \tinfo->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN :\n> 0;\n> +\tinfo->reg_ndcr |= (pdata->force_csx) ? NDCR_FORCE_CSX : 0;\n> \tinfo->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);\n> \tinfo->reg_ndcr |= NDCR_SPARE_EN;\n> \n> @@ -1498,6 +1500,7 @@ static void pxa3xx_nand_detect_config(struct\n> pxa3xx_nand_info *info) info->reg_ndcr = ndcr &\n> \t\t~(NDCR_INT_MASK | NDCR_ND_ARB_EN |\n> NFCV1_NDCR_ARB_CNTL); info->reg_ndcr |= (pdata->enable_arbiter) ?\n> NDCR_ND_ARB_EN : 0;\n> +\tinfo->reg_ndcr |= (pdata->force_csx) ? NDCR_FORCE_CSX : 0;\n> \tinfo->ndtr0cs0 = nand_readl(info, NDTR0CS0);\n> \tinfo->ndtr1cs0 = nand_readl(info, NDTR1CS0);\n> }\n> @@ -1936,6 +1939,9 @@ static int pxa3xx_nand_probe_dt(struct\n> platform_device *pdev) pdata->enable_arbiter = 1;\n> \tif (of_get_property(np, \"marvell,nand-keep-config\", NULL))\n> \t\tpdata->keep_config = 1;\n> +\tif (of_get_property(np, \"marvell,nand-force-csx\", NULL))\n> +\t\t/* Ref#: GL-5830741 */\n> +\t\tpdata->force_csx = 1;\n> \tof_property_read_u32(np, \"num-cs\", &pdata->num_cs);\n> \n> \tpdev->dev.platform_data = pdata;\n> diff --git a/include/linux/platform_data/mtd-nand-pxa3xx.h\n> b/include/linux/platform_data/mtd-nand-pxa3xx.h index\n> 394d15597dc7..e7f2c8647c0e 100644 ---\n> a/include/linux/platform_data/mtd-nand-pxa3xx.h +++\n> b/include/linux/platform_data/mtd-nand-pxa3xx.h @@ -28,6 +28,9 @@\n> struct pxa3xx_nand_platform_data { /* allow platform code to keep\n> OBM/bootloader defined NFC config */ int\tkeep_config;\n> \n> +\t/* Force chip select false on busy */\n> +\tint\tforce_csx;\n> +\n> \t/* indicate how many chip selects will be used */\n> \tint\tnum_cs;\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1XPY1G2Hz9tXc\n\tfor ;\n\tTue, 26 Sep 2017 17:18:57 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S934038AbdIZHSz convert rfc822-to-8bit (ORCPT\n\t);\n\tTue, 26 Sep 2017 03:18:55 -0400","from mail.free-electrons.com ([62.4.15.54]:42812 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S936001AbdIZHSy (ORCPT\n\t); Tue, 26 Sep 2017 03:18:54 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 420632090D; Tue, 26 Sep 2017 09:18:52 +0200 (CEST)","from xps13 (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr\n\t[90.63.216.87])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id D2E3F208BF;\n\tTue, 26 Sep 2017 09:18:51 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Tue, 26 Sep 2017 09:18:52 +0200","From":"Miquel RAYNAL ","To":"Kalyan Kinthada ","Cc":"dwmw2@infradead.org, computersforpeace@gmail.com,\n\tboris.brezillon@free-electrons.com, marek.vasut@gmail.com,\n\trichard@nod.at, cyrille.pitchen@wedev4u.fr, robh+dt@kernel.org,\n\tmark.rutland@arm.com, ezequiel.garcia@free-electrons.com,\n\tdevicetree@vger.kernel.org, chris.packham@alliedtelesis.co.nz,\n\tlinux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH 2/2] mtd: nand: pxa3xx: Handle \"marvell, nand-force-csx\"\n\tcompatible string","Message-ID":"<20170926091852.196f647d@xps13>","In-Reply-To":"<20170926041700.22663-3-kalyan.kinthada@alliedtelesis.co.nz>","References":"<20170926041700.22663-1-kalyan.kinthada@alliedtelesis.co.nz>\n\t<20170926041700.22663-3-kalyan.kinthada@alliedtelesis.co.nz>","Organization":"Free Electrons","X-Mailer":"Claws Mail 3.14.1 (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8BIT","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]