[{"id":1776909,"web_url":"http://patchwork.ozlabs.org/comment/1776909/","msgid":"<20170928093104.GC30097@localhost>","list_archive_url":null,"date":"2017-09-28T09:31:04","subject":"Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote:\n> NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels,\n> supports AHB <-> Memory and Memory <-> Memory transfers, slave / master\n> modes. This driver is primarily supposed to be used by gpu/host1x in a\n> master mode, performing 3D HW context stores.\n> \n> Dmitry Osipenko (5):\n> clk: tegra: Add AHB DMA clock entry\n> clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20\n> dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller\n> dmaengine: Add driver for NVIDIA Tegra AHB DMA controller\n> ARM: dts: tegra: Add AHB DMA controller nodes\n\nI don't think they are dependent, so consider sending them separately","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2q8s2VBKz9t39\n\tfor ;\n\tThu, 28 Sep 2017 19:27:25 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752333AbdI1J1M (ORCPT );\n\tThu, 28 Sep 2017 05:27:12 -0400","from mga07.intel.com ([134.134.136.100]:56668 \"EHLO\n\tmga07.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751088AbdI1J1K (ORCPT );\n\tThu, 28 Sep 2017 05:27:10 -0400","from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga105.jf.intel.com with ESMTP; 28 Sep 2017 02:27:09 -0700","from vkoul-udesk7.iind.intel.com (HELO localhost) ([10.223.84.143])\n\tby orsmga003.jf.intel.com with ESMTP; 28 Sep 2017 02:27:05 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,449,1500966000\"; d=\"scan'208\";a=\"1019374746\"","Date":"Thu, 28 Sep 2017 15:01:04 +0530","From":"Vinod Koul ","To":"Dmitry Osipenko ","Cc":"Thierry Reding ,\n\tJonathan Hunter ,\n\tLaxman Dewangan ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd ,\n\tRob Herring , linux-tegra@vger.kernel.org,\n\tdevicetree@vger.kernel.org, dmaengine@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver","Message-ID":"<20170928093104.GC30097@localhost>","References":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.5.24 (2015-08-30)","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"}},{"id":1776998,"web_url":"http://patchwork.ozlabs.org/comment/1776998/","msgid":"<275b6188-00de-3c45-9764-f16332d2dbdd@gmail.com>","list_archive_url":null,"date":"2017-09-28T12:24:57","subject":"Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver","submitter":{"id":18124,"url":"http://patchwork.ozlabs.org/api/people/18124/","name":"Dmitry Osipenko","email":"digetx@gmail.com"},"content":"On 28.09.2017 12:31, Vinod Koul wrote:\n> On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote:\n>> NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels,\n>> supports AHB <-> Memory and Memory <-> Memory transfers, slave / master\n>> modes. This driver is primarily supposed to be used by gpu/host1x in a\n>> master mode, performing 3D HW context stores.\n>>\n>> Dmitry Osipenko (5):\n>> clk: tegra: Add AHB DMA clock entry\n>> clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20\n>> dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller\n>> dmaengine: Add driver for NVIDIA Tegra AHB DMA controller\n>> ARM: dts: tegra: Add AHB DMA controller nodes\n> \n> I don't think they are dependent, so consider sending them separately\n> \n\nWell, they are dependent in a sense of making driver usable. Only the \"SCLK rate\nbump\" patch isn't strictly needed.\n\nSplitting this series won't cause building failures, but all pieces should be in\nplace for the working driver. So I suppose it is okay if clk patches would get\nin earlier than the others, I'll split the series.\n\nThank you for the review.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-tegra-owner@vger.kernel.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"btydCJJM\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2v6643MSz9tXj\n\tfor ;\n\tThu, 28 Sep 2017 22:25:18 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752859AbdI1MZD (ORCPT );\n\tThu, 28 Sep 2017 08:25:03 -0400","from mail-wr0-f169.google.com ([209.85.128.169]:45232 \"EHLO\n\tmail-wr0-f169.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752359AbdI1MZB (ORCPT\n\t);\n\tThu, 28 Sep 2017 08:25:01 -0400","by mail-wr0-f169.google.com with SMTP id m18so2353511wrm.2;\n\tThu, 28 Sep 2017 05:25:00 -0700 (PDT)","from [192.168.1.145] (ppp109-252-90-109.pppoe.spdop.ru.\n\t[109.252.90.109]) by smtp.googlemail.com with ESMTPSA id\n\tz86sm271755ljb.75.2017.09.28.05.24.58\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tThu, 28 Sep 2017 05:24:58 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=gmail.com; s=20161025;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=Ih+/iKYAaR4lFgNaUi4zQyEYngpdFCJs4OXd8D9XXnw=;\n\tb=btydCJJM7C68GgiV5YAObu3Q8kld4g1n1Eg9hfQMevOW5eHYRdFPatHe3n3virjbz5\n\tDxwPAG7WLW4zJgcCoccTAU7ohW6tJ7QTDAzO/LiVMoMda5t3nkZlhITM0Rx8+DJS3qp+\n\tnRhSjQGgPKcuq7SPsUppoAfxr3KzDkG/TMJx3qMJndBtg+9rZ3/Z17WOax2tVthOnTEX\n\t5A6hzoKCA2LoNkdHqhZlwR4DBnl0kJuEkR1MghurcCOY0OZ2prmDw1yC1z+8MZlr/yTH\n\tz/QCxQIZ80eeBDYQW+jTG4le0nLDq8l9eeZx6luc2ChRiFxABR50LE2Ni2LXfUgzgi/Z\n\tYNIg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=Ih+/iKYAaR4lFgNaUi4zQyEYngpdFCJs4OXd8D9XXnw=;\n\tb=Wf4Rb2E8at40a7YE1dcH7hnfBDvk5lMVms0Kw+3tqPp2iNkK2FCT94ZAuMxET4NZsr\n\tGqtaFX9W6WsheVsI5NjoIku0+L8SwAlEV/vs5w8XPXG12oP9t0BRlHGiVeoO6pbD1nQn\n\tkT8yQUphaaR1FWm1UcJ05eoUqZgaDJpP/qwKKLaF8G1+vhMnySQED9bQLRQVTeiwZwgx\n\tAWVeSioKBLL5mJNbKkIamWrh3f5gHRfkuzX7yqFrnJK2oqJCYTX7MwN35WlxZcR0T5NC\n\t8uCPaVR8ZQXkqdAKdXddTPq2XaHsWEVIXFLUZhbsb8fJsYYjRbhbVRAufvbmXIyDLXog\n\ttkbw==","X-Gm-Message-State":"AHPjjUi4XzBF3TTCOp0Y5iyvs+t1Eu6xAvt2NV4CCv2ya5Tzo+9ja27N\n\tp5eBy86XNjAsx561LKE1R/C2A1v/","X-Google-Smtp-Source":"AOwi7QD38+/9NHwWibEFPfNZbBR1NzkysjhuLqQXP7SgLKy9SGeiKcarEDLNgI468cIBUet4H//+EA==","X-Received":"by 10.46.0.208 with SMTP id e77mr2164395lji.170.1506601499416;\n\tThu, 28 Sep 2017 05:24:59 -0700 (PDT)","Subject":"Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver","To":"Vinod Koul ","Cc":"Thierry Reding ,\n\tJonathan Hunter ,\n\tLaxman Dewangan ,\n\tPeter De Schrijver ,\n\tPrashant Gaikwad ,\n\tMichael Turquette ,\n\tStephen Boyd ,\n\tRob Herring , linux-tegra@vger.kernel.org,\n\tdevicetree@vger.kernel.org, dmaengine@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org","References":"\n\t<20170928093104.GC30097@localhost>","From":"Dmitry Osipenko ","Message-ID":"<275b6188-00de-3c45-9764-f16332d2dbdd@gmail.com>","Date":"Thu, 28 Sep 2017 15:24:57 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170928093104.GC30097@localhost>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"linux-tegra-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"linux-tegra@vger.kernel.org"}}]