[{"id":1778326,"web_url":"http://patchwork.ozlabs.org/comment/1778326/","msgid":"<1506950874.17300.48.camel@baylibre.com>","list_archive_url":null,"date":"2017-10-02T13:27:54","subject":"Re: [PATCH 0/2] Meson GXL USB3 PHY and OTG detection driver","submitter":{"id":69839,"url":"http://patchwork.ozlabs.org/api/people/69839/","name":"Jerome Brunet","email":"jbrunet@baylibre.com"},"content":"On Sun, 2017-09-24 at 21:49 +0200, Martin Blumenstingl wrote:\n> Amlogic Meson GXL SoCs use a dwc3 controller with two USB2 ports,\n> Meson GXM SoCs use the same dwc3 controller but with three USB3\n> ports enabled. Neither of these SoCs has any USB3 port enabled in\n> the dwc3 registers.\n> The first USB2 port on both SoCs supports host and peripheral\n> (also called \"device\") mode.\n> \n> The dwc3 controller supports host mode only. Peripheral mode is\n> implemented through an additional dwc2 controller (which only enables\n> device mode). The USB3 PHY has register bits which allow a driver to\n> detect the current mode - however this is currently not implemented\n> as the dwc2 controller seems to hang during reset (and I do not have\n> a use-case where I need peripheral/device mode).\n> \n> While the dwc3 controller has no USB3 port enabled we still need the\n> USB3 PHY to be initialized, otherwise some boards (probably those where\n> the bootloader does not initialize the USB3 PHY) show errors with\n> high-speed USB devices connected to any of the USB2 ports. Configuring\n> the USB_R1_U3H_FLADJ_30MHZ_REG_MASK register as it's done by Amlogic's\n> vendor GPL kernel sources makes these error go away.\n> \n> Thanks to Jerome Brunet for reporting the errors and Neil Armstrong\n> for discovering that initializing the USB3 PHY fixes these USB errors!\n> \n\nThis series works well on the libretech-cc (le potato)\nFor the series:\n\nTested-by: Jerome Brunet \n\n> \n> Martin Blumenstingl (2):\n> dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL\n> SoCs\n> phy: amlogic: add USB3 PHY support for Meson GXL and GXM\n> \n> .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt | 19 +++\n> drivers/phy/amlogic/Kconfig | 12 ++\n> drivers/phy/amlogic/Makefile | 1 +\n> drivers/phy/amlogic/phy-meson-gxl-usb3.c | 177\n> +++++++++++++++++++++\n> 4 files changed, 209 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-\n> phy.txt\n> create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c\n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tMon, 02 Oct 2017 06:27:55 -0700 (PDT)","Message-ID":"<1506950874.17300.48.camel@baylibre.com>","Subject":"Re: [PATCH 0/2] Meson GXL USB3 PHY and OTG detection driver","From":"Jerome Brunet ","To":"Martin Blumenstingl ,\n\tkishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com,\n\tdevicetree@vger.kernel.org, linux-amlogic@lists.infradead.org","Cc":"carlo@caione.org, khilman@baylibre.com, narmstrong@baylibre.com","Date":"Mon, 02 Oct 2017 15:27:54 +0200","In-Reply-To":"<20170924195000.13276-1-martin.blumenstingl@googlemail.com>","References":"<20170924195000.13276-1-martin.blumenstingl@googlemail.com>","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailer":"Evolution 3.24.5 (3.24.5-1.fc26) ","Mime-Version":"1.0","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1790329,"web_url":"http://patchwork.ozlabs.org/comment/1790329/","msgid":"<5cdc949b-f73e-fca8-246e-26022a743382@baylibre.com>","list_archive_url":null,"date":"2017-10-19T09:57:43","subject":"Re: [PATCH 0/2] Meson GXL USB3 PHY and OTG detection driver","submitter":{"id":67289,"url":"http://patchwork.ozlabs.org/api/people/67289/","name":"Neil Armstrong","email":"narmstrong@baylibre.com"},"content":"On 24/09/2017 21:49, Martin Blumenstingl wrote:\n> Amlogic Meson GXL SoCs use a dwc3 controller with two USB2 ports,\n> Meson GXM SoCs use the same dwc3 controller but with three USB3\n> ports enabled. Neither of these SoCs has any USB3 port enabled in\n> the dwc3 registers.\n> The first USB2 port on both SoCs supports host and peripheral\n> (also called \"device\") mode.\n> \n> The dwc3 controller supports host mode only. Peripheral mode is\n> implemented through an additional dwc2 controller (which only enables\n> device mode). The USB3 PHY has register bits which allow a driver to\n> detect the current mode - however this is currently not implemented\n> as the dwc2 controller seems to hang during reset (and I do not have\n> a use-case where I need peripheral/device mode).\n> \n> While the dwc3 controller has no USB3 port enabled we still need the\n> USB3 PHY to be initialized, otherwise some boards (probably those where\n> the bootloader does not initialize the USB3 PHY) show errors with\n> high-speed USB devices connected to any of the USB2 ports. Configuring\n> the USB_R1_U3H_FLADJ_30MHZ_REG_MASK register as it's done by Amlogic's\n> vendor GPL kernel sources makes these error go away.\n> \n> Thanks to Jerome Brunet for reporting the errors and Neil Armstrong\n> for discovering that initializing the USB3 PHY fixes these USB errors!\n> \n> \n> Martin Blumenstingl (2):\n> dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL\n> SoCs\n> phy: amlogic: add USB3 PHY support for Meson GXL and GXM\n> \n> .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt | 19 +++\n> drivers/phy/amlogic/Kconfig | 12 ++\n> drivers/phy/amlogic/Makefile | 1 +\n> drivers/phy/amlogic/phy-meson-gxl-usb3.c | 177 +++++++++++++++++++++\n> 4 files changed, 209 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt\n> create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c\n> \n\nTested-by: Neil Armstrong \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tThu, 19 Oct 2017 02:57:44 -0700 (PDT)","Subject":"Re: [PATCH 0/2] Meson GXL USB3 PHY and OTG detection driver","To":"Martin Blumenstingl ,\n\tkishon@ti.com, robh+dt@kernel.org, mark.rutland@arm.com,\n\tdevicetree@vger.kernel.org, linux-amlogic@lists.infradead.org","Cc":"carlo@caione.org, khilman@baylibre.com, jbrunet@baylibre.com","References":"<20170924195000.13276-1-martin.blumenstingl@googlemail.com>","From":"Neil Armstrong ","Organization":"Baylibre","Message-ID":"<5cdc949b-f73e-fca8-246e-26022a743382@baylibre.com>","Date":"Thu, 19 Oct 2017 11:57:43 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.4.0","MIME-Version":"1.0","In-Reply-To":"<20170924195000.13276-1-martin.blumenstingl@googlemail.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1799389,"web_url":"http://patchwork.ozlabs.org/comment/1799389/","msgid":"","list_archive_url":null,"date":"2017-11-05T21:35:50","subject":"Re: [PATCH 0/2] Meson GXL USB3 PHY and OTG detection driver","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"content":"Hi Kishon,\n\nOn Sun, Sep 24, 2017 at 9:49 PM, Martin Blumenstingl\n wrote:\n> Amlogic Meson GXL SoCs use a dwc3 controller with two USB2 ports,\n> Meson GXM SoCs use the same dwc3 controller but with three USB3\n> ports enabled. Neither of these SoCs has any USB3 port enabled in\n> the dwc3 registers.\n> The first USB2 port on both SoCs supports host and peripheral\n> (also called \"device\") mode.\n>\n> The dwc3 controller supports host mode only. Peripheral mode is\n> implemented through an additional dwc2 controller (which only enables\n> device mode). The USB3 PHY has register bits which allow a driver to\n> detect the current mode - however this is currently not implemented\n> as the dwc2 controller seems to hang during reset (and I do not have\n> a use-case where I need peripheral/device mode).\n>\n> While the dwc3 controller has no USB3 port enabled we still need the\n> USB3 PHY to be initialized, otherwise some boards (probably those where\n> the bootloader does not initialize the USB3 PHY) show errors with\n> high-speed USB devices connected to any of the USB2 ports. Configuring\n> the USB_R1_U3H_FLADJ_30MHZ_REG_MASK register as it's done by Amlogic's\n> vendor GPL kernel sources makes these error go away.\n>\n> Thanks to Jerome Brunet for reporting the errors and Neil Armstrong\n> for discovering that initializing the USB3 PHY fixes these USB errors!\n>\n>\n> Martin Blumenstingl (2):\n> dt-bindings: phy: Add support for the USB3 PHY on Amlogic Meson GXL\n> SoCs\nI need to update the dt-bindings patch as there is an interrupt which\nseems to exist on all hardware revisions (but this interrupt is not\ndescribed in the binding yet)\nso please do NOT take this series until I re-spin it so I can add the\nmandatory interrupt (if we add it later we can only add it optionally)\n\n> phy: amlogic: add USB3 PHY support for Meson GXL and GXM\ncould you please give your feedback on this one?\n\n>\n> .../devicetree/bindings/phy/meson-gxl-usb3-phy.txt | 19 +++\n> drivers/phy/amlogic/Kconfig | 12 ++\n> drivers/phy/amlogic/Makefile | 1 +\n> drivers/phy/amlogic/phy-meson-gxl-usb3.c | 177 +++++++++++++++++++++\n> 4 files changed, 209 insertions(+)\n> create mode 100644 Documentation/devicetree/bindings/phy/meson-gxl-usb3-phy.txt\n> create mode 100644 drivers/phy/amlogic/phy-meson-gxl-usb3.c\n>\n> --\n> 2.14.1\n>\n\n\nRegards,\nMartin\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1800237,"web_url":"http://patchwork.ozlabs.org/comment/1800237/","msgid":"<463fae8a-4b6d-1111-7ac2-1d3f1f31b9b1@ti.com>","list_archive_url":null,"date":"2017-11-07T05:53:18","subject":"Re: [PATCH 2/2] phy: amlogic: add USB3 PHY support for Meson GXL and\n\tGXM","submitter":{"id":14965,"url":"http://patchwork.ozlabs.org/api/people/14965/","name":"Kishon Vijay Abraham I","email":"kishon@ti.com"},"content":"Hi,\n\nOn Monday 25 September 2017 01:20 AM, Martin Blumenstingl wrote:\n> This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs\n> (both SoCs are using the same USB PHY register layout).\n> \n> Unfortunately there is no documentation for this PHY in the public S905X\n> datasheet (published for example by Khadas). What we know so far about\n> this PHY:\n> - even though the Meson GXL and GXM SoCs do not expose an USB3 port (the\n> dwc3 controller only has USB2 ports enabled) we need to initialize the\n> USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this\n> initialization high-speed USB devices (especially USB hard disks and\n> thumb drives, slower devices like mice do not seem to be affected)\n> - it is responsible for the OTG detection and for switching the first\n> USB2 PHY between host and peripheral (aka device) mode. an interrupt\n> can be used to detect changes between host and device mode.\n> \n> The whole OTG detection logic is currently not implemented.\n\nIs this an independent instance of the phy? The programming model looks similar\nto phy-meson-gxl-usb2.c..\n\nI'm just thinking if we should have only a phy-meson-gxl-usb.c and have both\nusb2 and usb3 phy programming there?\n\nThanks\nKishon\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"ImjYYN1J\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yWJXz5S0Dz9s71\n\tfor ;\n\tTue, 7 Nov 2017 16:54:43 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753833AbdKGFym (ORCPT\n\t);\n\tTue, 7 Nov 2017 00:54:42 -0500","from lelnx193.ext.ti.com ([198.47.27.77]:10242 \"EHLO\n\tlelnx193.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753828AbdKGFyl (ORCPT\n\t); Tue, 7 Nov 2017 00:54:41 -0500","from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id vA75rMEm014156; \n\tMon, 6 Nov 2017 23:53:22 -0600","from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id vA75rMgo029501; \n\tMon, 6 Nov 2017 23:53:22 -0600","from DLEE108.ent.ti.com (157.170.170.38) by DLEE112.ent.ti.com\n\t(157.170.170.23) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tMon, 6 Nov 2017 23:53:22 -0600","from dflp33.itg.ti.com (10.64.6.16) by DLEE108.ent.ti.com\n\t(157.170.170.38) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Mon, 6 Nov 2017 23:53:22 -0600","from [172.24.190.233] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id vA75rIw2008283;\n\tMon, 6 Nov 2017 23:53:20 -0600"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1510034003;\n\tbh=AS0wlUKkq79gF7xelenfdfB98D5lIvYRqFuTeDD5R9c=;\n\th=Subject:To:References:CC:From:Date:In-Reply-To;\n\tb=ImjYYN1JFp206LxNO9HDerJw2aYDFxWMbr+pwmr1mfvTG8+8J5qZ3NofmPOgsZ5Ds\n\tAe6mnvi+zOlHUh2XXhONFHIwu5fTU24lCJK1LxC0T381VuojD8WKjDlqnnl7PVHuPd\n\ta+SJtBATbCO2j5TrGlisjLlBatFE00a5DsfbbsDg=","Subject":"Re: [PATCH 2/2] phy: amlogic: add USB3 PHY support for Meson GXL and\n\tGXM","To":"Martin Blumenstingl ,\n\t, ,\n\t, ","References":"<20170924195000.13276-1-martin.blumenstingl@googlemail.com>\n\t<20170924195000.13276-3-martin.blumenstingl@googlemail.com>","CC":", ,\n\t, ","From":"Kishon Vijay Abraham I ","Message-ID":"<463fae8a-4b6d-1111-7ac2-1d3f1f31b9b1@ti.com>","Date":"Tue, 7 Nov 2017 11:23:18 +0530","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.7.0","MIME-Version":"1.0","In-Reply-To":"<20170924195000.13276-3-martin.blumenstingl@googlemail.com>","Content-Type":"text/plain; charset=\"windows-1252\"","Content-Transfer-Encoding":"7bit","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1800842,"web_url":"http://patchwork.ozlabs.org/comment/1800842/","msgid":"","list_archive_url":null,"date":"2017-11-07T21:29:45","subject":"Re: [PATCH 2/2] phy: amlogic: add USB3 PHY support for Meson GXL and\n\tGXM","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"content":"Hi Kishon,\n\nthank you for reviewing this!\n\nOn Tue, Nov 7, 2017 at 6:53 AM, Kishon Vijay Abraham I wrote:\n> Hi,\n>\n> On Monday 25 September 2017 01:20 AM, Martin Blumenstingl wrote:\n>> This adds a new driver for the USB3 PHY found on Meson GXL and GXM SoCs\n>> (both SoCs are using the same USB PHY register layout).\n>>\n>> Unfortunately there is no documentation for this PHY in the public S905X\n>> datasheet (published for example by Khadas). What we know so far about\n>> this PHY:\n>> - even though the Meson GXL and GXM SoCs do not expose an USB3 port (the\n>> dwc3 controller only has USB2 ports enabled) we need to initialize the\n>> USB3 PHY (specifically USB_R1_U3H_FLADJ_30MHZ_REG_MASK). Without this\n>> initialization high-speed USB devices (especially USB hard disks and\n>> thumb drives, slower devices like mice do not seem to be affected)\n>> - it is responsible for the OTG detection and for switching the first\n>> USB2 PHY between host and peripheral (aka device) mode. an interrupt\n>> can be used to detect changes between host and device mode.\n>>\n>> The whole OTG detection logic is currently not implemented.\n>\n> Is this an independent instance of the phy? The programming model looks similar\n> to phy-meson-gxl-usb2.c..\nthere are up to four USB2 PHYs in these SoCs but only one USB3 PHY.\nfrom what I can tell both PHY types are different (both use a totally\ndifferent register layout)\n\n> I'm just thinking if we should have only a phy-meson-gxl-usb.c and have both\n> usb2 and usb3 phy programming there?\nI can try that, but I think it would make the result harder to read\n(as the only parts that can be re-used are in the priv memory\nallocation, creating the regmap and the PHY registration in the _probe\nfunction)\nso I would prefer to keep both PHYs as separate drivers in separate files\n\n\nRegards\nMartin\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=googlemail.com header.i=@googlemail.com\n\theader.b=\"DMK6oyu0\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yWjJJ6p14z9s7F\n\tfor ;\n\tWed, 8 Nov 2017 08:30:08 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755606AbdKGVaH (ORCPT\n\t);\n\tTue, 7 Nov 2017 16:30:07 -0500","from mail-io0-f170.google.com ([209.85.223.170]:47103 \"EHLO\n\tmail-io0-f170.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751565AbdKGVaH (ORCPT\n\t); Tue, 7 Nov 2017 16:30:07 -0500","by mail-io0-f170.google.com with SMTP id 101so3711493ioj.3\n\tfor ;\n\tTue, 07 Nov 2017 13:30:06 -0800 (PST)","by 10.2.151.236 with HTTP; Tue, 7 Nov 2017 13:29:45 -0800 (PST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=googlemail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc; bh=KtH6X9kY8Wq22YGFnPXMEmXNgJ3q7Vkkd1GGncyoSmQ=;\n\tb=DMK6oyu0CVnI2XK2ZWthuc9QrHpykX8gLtlqZfZWRbuBVmM7s6tJZcQRcJLfbG7jEW\n\tsDdCODSp1HSPMYcuFPjdFjhEicB65QqDkPrFgXg9S6nwwUIkgZDs9pmZpQBsFYb9CM0x\n\tZBjSyyK5QCsXbR/NKJxIahAPN6/EcR9icGzuUHCU/MckljfkDM7mYBYp1kQMw6WIcs64\n\txiGwgoWsfLO3zXEHcAfM2tbM9W3z3trS3NQURw6XRoAkM69+Oe2Tx3tLQWAIhTEdtkF8\n\t8b53F8xihVkh6von7rtD/YuZ+4vsO4mxWdry+O5WZUNBFay/iBgLTm/avxLnHpm6bhE8\n\tu2mw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc;\n\tbh=KtH6X9kY8Wq22YGFnPXMEmXNgJ3q7Vkkd1GGncyoSmQ=;\n\tb=qAzJP8DTsw9sx/dJeL14DMDB1SEchF2s/qc3KAQgEZZ3scHs79yPCJbmAlvEUYbv87\n\tpP+xmvHuzq4q82d4zhEZesplXSzpyOK5OUrlqsTVvMuirtFc4zdJYC5pfJfQLjxSmr1i\n\trY2kXpwi5PWswI2TGN0IjxfFt1fkXL5zAU9L1lPdCBqiDZYTWaTLTNbG+rAnQxMWNhh6\n\tMbj2N/xVncqvNd8mNN+URJMyv+u1rVmKOC7QEf1esuR4nql2XnwwnsmI2oRoASk3Nreb\n\tewRcP0fsLo9o3/IqfhSpZ6qMJy8eolPoUymoyg8vrQGHtpgFu5uLUID5OnK33VMpNUpE\n\t/wEw==","X-Gm-Message-State":"AJaThX7I0fzi15r9GwwRFlrSpu3rV/Vi37vlIKL536HO4lC0env0EHfJ\n\tzDtqxhhlU3DkxpSJt6oPCgMAuoskEGe5T/tCATk=","X-Google-Smtp-Source":"AGs4zMYvAoA8gzBlNdcfC+I/fwqaVhZogtRHBaaRW70fXEA/2viFFPjcJ/7ROgOhfHez21n7Lqz2qwmszXBVDjuOvAk=","X-Received":"by 10.107.57.137 with SMTP id g131mr152501ioa.269.1510090206164; \n\tTue, 07 Nov 2017 13:30:06 -0800 (PST)","MIME-Version":"1.0","In-Reply-To":"<463fae8a-4b6d-1111-7ac2-1d3f1f31b9b1@ti.com>","References":"<20170924195000.13276-1-martin.blumenstingl@googlemail.com>\n\t<20170924195000.13276-3-martin.blumenstingl@googlemail.com>\n\t<463fae8a-4b6d-1111-7ac2-1d3f1f31b9b1@ti.com>","From":"Martin Blumenstingl ","Date":"Tue, 7 Nov 2017 22:29:45 +0100","Message-ID":"","Subject":"Re: [PATCH 2/2] phy: amlogic: add USB3 PHY support for Meson GXL and\n\tGXM","To":"Kishon Vijay Abraham I ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com,\n\tdevicetree@vger.kernel.org, linux-amlogic@lists.infradead.org,\n\tcarlo@caione.org, khilman@baylibre.com,\n\tNeil Armstrong , jbrunet@baylibre.com","Content-Type":"text/plain; charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]