[{"id":1774150,"web_url":"http://patchwork.ozlabs.org/comment/1774150/","msgid":"<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>","list_archive_url":null,"date":"2017-09-24T11:59:45","subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 12:59 PM, Vignesh R wrote:\n> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access\n> Controller programming sequence, a delay equal to couple of QSPI master\n> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and\n> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY\n> to handle this and set this flag for TI 66AK2G SoC.\n> \n> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf\n> \n> Signed-off-by: Vignesh R \n\nIs this TI specific or is this controller property ? I wouldn't be\nsurprised of the later ...\n\n> ---\n> \n> v3:\n> Fix build warnings reported by kbuild test bot.\n> \n> drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-\n> 1 file changed, 26 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n> index 53c7d8e0327a..5cd5d6f7303f 100644\n> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n> @@ -38,6 +38,9 @@\n> #define CQSPI_NAME\t\t\t\"cadence-qspi\"\n> #define CQSPI_MAX_CHIPSELECT\t\t16\n> \n> +/* Quirks */\n> +#define CQSPI_NEEDS_WR_DELAY\t\tBIT(0)\n> +\n> struct cqspi_st;\n> \n> struct cqspi_flash_pdata {\n> @@ -76,6 +79,7 @@ struct cqspi_st {\n> \tu32\t\t\tfifo_depth;\n> \tu32\t\t\tfifo_width;\n> \tu32\t\t\ttrigger_address;\n> +\tu32\t\t\twr_delay;\n> \tstruct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];\n> };\n> \n> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,\n> \treinit_completion(&cqspi->transfer_complete);\n> \twritel(CQSPI_REG_INDIRECTWR_START_MASK,\n> \t reg_base + CQSPI_REG_INDIRECTWR);\n> +\t/*\n> +\t * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access\n> +\t * Controller programming sequence, couple of cycles of\n> +\t * QSPI_REF_CLK delay is required for the above bit to\n> +\t * be internally synchronized by the QSPI module. Provide 5\n> +\t * cycles of delay.\n> +\t */\n> +\tif (cqspi->wr_delay)\n> +\t\tndelay(cqspi->wr_delay);\n> \n> \twhile (remaining > 0) {\n> \t\twrite_bytes = remaining > page_size ? page_size : remaining;\n> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)\n> \tstruct cqspi_st *cqspi;\n> \tstruct resource *res;\n> \tstruct resource *res_ahb;\n> +\tunsigned long data;\n> \tint ret;\n> \tint irq;\n> \n> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)\n> \t}\n> \n> \tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n> +\tdata = (unsigned long)of_device_get_match_data(dev);\n> +\tif (data & CQSPI_NEEDS_WR_DELAY)\n> +\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n> +\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n> \n> \tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n> \t\t\t pdev->name, cqspi);\n> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {\n> #endif\n> \n> static const struct of_device_id cqspi_dt_ids[] = {\n> -\t{.compatible = \"cdns,qspi-nor\",},\n> +\t{\n> +\t\t.compatible = \"cdns,qspi-nor\",\n> +\t\t.data = (void *)0,\n> +\t},\n> +\t{\n> +\t\t.compatible = \"ti,k2g-qspi\",\n> +\t\t.data = (void *)CQSPI_NEEDS_WR_DELAY,\n> +\t},\n> \t{ /* end of table */ }\n> };\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tSun, 24 Sep 2017 05:11:53 -0700 (PDT)","Subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","To":"Vignesh R , Cyrille Pitchen ","Cc":"David Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\tlinux-mtd@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-3-vigneshr@ti.com>","From":"Marek Vasut ","Message-ID":"<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>","Date":"Sun, 24 Sep 2017 13:59:45 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170924105924.23923-3-vigneshr@ti.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774151,"web_url":"http://patchwork.ozlabs.org/comment/1774151/","msgid":"<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>","list_archive_url":null,"date":"2017-09-24T12:01:03","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 12:59 PM, Vignesh R wrote:\n> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n> switch on QSPI power domain on TI 66AK2G SoC during probe.\n> \n> Signed-off-by: Vignesh R \n\nAre you planning to add some more fine-grained PM control later?\n\n> ---\n> drivers/mtd/spi-nor/cadence-quadspi.c | 11 +++++++++++\n> 1 file changed, 11 insertions(+)\n> \n> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n> index d9629e8f4798..2c8e6226d267 100644\n> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n> @@ -31,6 +31,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -1224,6 +1225,13 @@ static int cqspi_probe(struct platform_device *pdev)\n> \t\treturn -ENXIO;\n> \t}\n> \n> +\tpm_runtime_enable(&pdev->dev);\n> +\tret = pm_runtime_get_sync(&pdev->dev);\n> +\tif (ret < 0) {\n> +\t\tpm_runtime_put_noidle(&pdev->dev);\n> +\t\treturn ret;\n> +\t}\n> +\n> \tret = clk_prepare_enable(cqspi->clk);\n> \tif (ret) {\n> \t\tdev_err(dev, \"Cannot enable QSPI clock.\\n\");\n> @@ -1275,6 +1283,9 @@ static int cqspi_remove(struct platform_device *pdev)\n> \n> \tclk_disable_unprepare(cqspi->clk);\n> \n> +\tpm_runtime_put_sync(&pdev->dev);\n> +\tpm_runtime_disable(&pdev->dev);\n> +\n> \treturn 0;\n> }\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170924105924.23923-6-vigneshr@ti.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774159,"web_url":"http://patchwork.ozlabs.org/comment/1774159/","msgid":"<8990b971-91d5-747f-905b-5e24743e090d@ti.com>","list_archive_url":null,"date":"2017-09-24T12:33:51","subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"On 9/24/2017 5:29 PM, Marek Vasut wrote:\n> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access\n>> Controller programming sequence, a delay equal to couple of QSPI master\n>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and\n>> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY\n>> to handle this and set this flag for TI 66AK2G SoC.\n>>\n>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf\n>>\n>> Signed-off-by: Vignesh R \n> \n> Is this TI specific or is this controller property ? I wouldn't be\n> surprised of the later ...\n\nI am not sure, there is no generic public documentation by cadence for\nthis IP. TI TRM clearly states this delay is required and I have\nverified it practically that this delay is indeed needed.\nBut current user of this IP, socfpga does not seem to mention anything\nabout it. So, I guess its TI specific quirk.\n\n> \n>> ---\n>>\n>> v3:\n>> Fix build warnings reported by kbuild test bot.\n>>\n>> drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-\n>> 1 file changed, 26 insertions(+), 1 deletion(-)\n>>\n>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> index 53c7d8e0327a..5cd5d6f7303f 100644\n>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> @@ -38,6 +38,9 @@\n>> #define CQSPI_NAME\t\t\t\"cadence-qspi\"\n>> #define CQSPI_MAX_CHIPSELECT\t\t16\n>> \n>> +/* Quirks */\n>> +#define CQSPI_NEEDS_WR_DELAY\t\tBIT(0)\n>> +\n>> struct cqspi_st;\n>> \n>> struct cqspi_flash_pdata {\n>> @@ -76,6 +79,7 @@ struct cqspi_st {\n>> \tu32\t\t\tfifo_depth;\n>> \tu32\t\t\tfifo_width;\n>> \tu32\t\t\ttrigger_address;\n>> +\tu32\t\t\twr_delay;\n>> \tstruct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];\n>> };\n>> \n>> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,\n>> \treinit_completion(&cqspi->transfer_complete);\n>> \twritel(CQSPI_REG_INDIRECTWR_START_MASK,\n>> \t reg_base + CQSPI_REG_INDIRECTWR);\n>> +\t/*\n>> +\t * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access\n>> +\t * Controller programming sequence, couple of cycles of\n>> +\t * QSPI_REF_CLK delay is required for the above bit to\n>> +\t * be internally synchronized by the QSPI module. Provide 5\n>> +\t * cycles of delay.\n>> +\t */\n>> +\tif (cqspi->wr_delay)\n>> +\t\tndelay(cqspi->wr_delay);\n>> \n>> \twhile (remaining > 0) {\n>> \t\twrite_bytes = remaining > page_size ? page_size : remaining;\n>> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)\n>> \tstruct cqspi_st *cqspi;\n>> \tstruct resource *res;\n>> \tstruct resource *res_ahb;\n>> +\tunsigned long data;\n>> \tint ret;\n>> \tint irq;\n>> \n>> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)\n>> \t}\n>> \n>> \tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>> +\tdata = (unsigned long)of_device_get_match_data(dev);\n>> +\tif (data & CQSPI_NEEDS_WR_DELAY)\n>> +\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n>> +\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n>> \n>> \tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n>> \t\t\t pdev->name, cqspi);\n>> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {\n>> #endif\n>> \n>> static const struct of_device_id cqspi_dt_ids[] = {\n>> -\t{.compatible = \"cdns,qspi-nor\",},\n>> +\t{\n>> +\t\t.compatible = \"cdns,qspi-nor\",\n>> +\t\t.data = (void *)0,\n>> +\t},\n>> +\t{\n>> +\t\t.compatible = \"ti,k2g-qspi\",\n>> +\t\t.data = (void *)CQSPI_NEEDS_WR_DELAY,\n>> +\t},\n>> \t{ /* end of table */ }\n>> };\n>> \n>>\n> \n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"VZwIaZcC\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0RXP3QgHz9sRW\n\tfor ;\n\tSun, 24 Sep 2017 22:36:05 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752194AbdIXMgC (ORCPT\n\t);\n\tSun, 24 Sep 2017 08:36:02 -0400","from fllnx209.ext.ti.com ([198.47.19.16]:42811 \"EHLO\n\tfllnx209.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752102AbdIXMgB (ORCPT\n\t); Sun, 24 Sep 2017 08:36:01 -0400","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8OCY2JI030858; \n\tSun, 24 Sep 2017 07:34:02 -0500","from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8OCXv3U002604;\n\tSun, 24 Sep 2017 07:33:57 -0500","from DLEE110.ent.ti.com (157.170.170.21) by DLEE107.ent.ti.com\n\t(157.170.170.37) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tSun, 24 Sep 2017 07:33:56 -0500","from dlep32.itg.ti.com (157.170.170.100) by DLEE110.ent.ti.com\n\t(157.170.170.21) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Sun, 24 Sep 2017 07:33:56 -0500","from [172.22.218.57] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8OCXpje000382;\n\tSun, 24 Sep 2017 07:33:52 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506256442;\n\tbh=U4AJTVEHOBpMZFR+ml9l0XP4eWgkIYe3SIRgeYPWSug=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=VZwIaZcCdXBQKS0WQgHPqM0p/F0cotEwq5Mu0Zx2ulhMf6A2ZaNWbmrQPyxY3W3E6\n\tgkmkAeG/0leKwpDpE3M3kwHDYiYYGxsOxOZe/Pb4MSpifj56vCZH3Br0eMstnKBC9d\n\tcrtf3fGJB1ktIGI+Pkki74gpaVwSSr0pv/1OM9dI=","Subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","To":"Marek Vasut ,\n\tCyrille Pitchen ","CC":"David Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\t, ,\n\t,\n\tlinux-arm-kernel ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-3-vigneshr@ti.com>\n\t<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>","From":"Vignesh R ","Message-ID":"<8990b971-91d5-747f-905b-5e24743e090d@ti.com>","Date":"Sun, 24 Sep 2017 18:03:51 +0530","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774177,"web_url":"http://patchwork.ozlabs.org/comment/1774177/","msgid":"<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>","list_archive_url":null,"date":"2017-09-24T13:08:23","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"On 9/24/2017 5:31 PM, Marek Vasut wrote:\n> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>\n>> Signed-off-by: Vignesh R \n> \n> Are you planning to add some more fine-grained PM control later?\n\nYes, I will need to add fine-grained PM control at some point. But, for\nnow SoC does not really support low power mode or runtime power saving\noption.\nThe fact that driver still uses clk_prepare_*() calls to enable/disable\nclocks instead of pm_*() calls makes it a bit tricky though.\n\nJust figured out I forgot to add cleanup code in error handling path of\nprobe(). Will fix that and send a v4.\n\n> \n>> ---\n>> drivers/mtd/spi-nor/cadence-quadspi.c | 11 +++++++++++\n>> 1 file changed, 11 insertions(+)\n>>\n>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> index d9629e8f4798..2c8e6226d267 100644\n>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> @@ -31,6 +31,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>> #include \n>> #include \n>> #include \n>> @@ -1224,6 +1225,13 @@ static int cqspi_probe(struct platform_device *pdev)\n>> \t\treturn -ENXIO;\n>> \t}\n>> \n>> +\tpm_runtime_enable(&pdev->dev);\n>> +\tret = pm_runtime_get_sync(&pdev->dev);\n>> +\tif (ret < 0) {\n>> +\t\tpm_runtime_put_noidle(&pdev->dev);\n>> +\t\treturn ret;\n>> +\t}\n>> +\n>> \tret = clk_prepare_enable(cqspi->clk);\n>> \tif (ret) {\n>> \t\tdev_err(dev, \"Cannot enable QSPI clock.\\n\");\n>> @@ -1275,6 +1283,9 @@ static int cqspi_remove(struct platform_device *pdev)\n>> \n>> \tclk_disable_unprepare(cqspi->clk);\n>> \n>> +\tpm_runtime_put_sync(&pdev->dev);\n>> +\tpm_runtime_disable(&pdev->dev);\n>> +\n>> \treturn 0;\n>> }\n>> \n>>\n> \n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"FrtUls4n\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0SJD5QZXz9sRq\n\tfor ;\n\tSun, 24 Sep 2017 23:10:36 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752445AbdIXNKf (ORCPT\n\t);\n\tSun, 24 Sep 2017 09:10:35 -0400","from fllnx209.ext.ti.com ([198.47.19.16]:43323 \"EHLO\n\tfllnx209.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752347AbdIXNKe (ORCPT\n\t); Sun, 24 Sep 2017 09:10:34 -0400","from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8OD8ZqD000873; \n\tSun, 24 Sep 2017 08:08:35 -0500","from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8OD8Uf4008266; \n\tSun, 24 Sep 2017 08:08:30 -0500","from DLEE106.ent.ti.com (157.170.170.36) by DLEE100.ent.ti.com\n\t(157.170.170.30) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tSun, 24 Sep 2017 08:08:30 -0500","from dlep33.itg.ti.com (157.170.170.75) by DLEE106.ent.ti.com\n\t(157.170.170.36) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Sun, 24 Sep 2017 08:08:30 -0500","from [172.22.218.57] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8OD8Op7018225;\n\tSun, 24 Sep 2017 08:08:25 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506258515;\n\tbh=awk7ZFFBUO7M3Pfur1niddfdlV1zeWFvGhfus+VnrE8=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=FrtUls4nGw1YlkIX+6wd7sPLvmJLpZ+nBboG3IsT9yeFmKbNEISUTOHTv+LvnphZz\n\tkvHopk8XomIk/oyCp7jMeQkpElYo1d1D0SXaNtxYuz9beUnBrFXrt2OVZ4NKn+U3F4\n\tG9GSIlGXy6KuJEA0pPSior/89umzZZkdkh/DonCE=","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","To":"Marek Vasut ,\n\tCyrille Pitchen ","CC":"David Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\t, ,\n\t,\n\tlinux-arm-kernel ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>","From":"Vignesh R ","Message-ID":"<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>","Date":"Sun, 24 Sep 2017 18:38:23 +0530","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774180,"web_url":"http://patchwork.ozlabs.org/comment/1774180/","msgid":"","list_archive_url":null,"date":"2017-09-24T13:12:37","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 03:08 PM, Vignesh R wrote:\n> \n> \n> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>\n>>> Signed-off-by: Vignesh R \n>>\n>> Are you planning to add some more fine-grained PM control later?\n> \n> Yes, I will need to add fine-grained PM control at some point. But, for\n> now SoC does not really support low power mode or runtime power saving\n> option.\n> The fact that driver still uses clk_prepare_*() calls to enable/disable\n> clocks instead of pm_*() calls makes it a bit tricky though.\n> \n> Just figured out I forgot to add cleanup code in error handling path of\n> probe(). Will fix that and send a v4.\n\nOK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\neither, so it's fine for now.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"fz6ka5JW\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0SLf4t8Yz9sRm\n\tfor ;\n\tSun, 24 Sep 2017 23:12:42 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752503AbdIXNMl (ORCPT\n\t);\n\tSun, 24 Sep 2017 09:12:41 -0400","from mail-wr0-f194.google.com ([209.85.128.194]:35811 \"EHLO\n\tmail-wr0-f194.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752499AbdIXNMk (ORCPT\n\t); Sun, 24 Sep 2017 09:12:40 -0400","by mail-wr0-f194.google.com with SMTP id n64so2986443wrb.2;\n\tSun, 24 Sep 2017 06:12:39 -0700 (PDT)","from [192.168.1.4] (ip-86-49-107-50.net.upcbroadband.cz.\n\t[86.49.107.50]) by smtp.gmail.com with ESMTPSA id\n\tf43sm9404003wra.79.2017.09.24.06.12.37\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 24 Sep 2017 06:12:38 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=kmll9l4eAvYUwnIen3TWbsYuSMORrldpFD+hfGSzAsY=;\n\tb=fz6ka5JW4WCJWvkTaVSR+bjIZTuqfgozYRHQjZzx+yfgr2Rrk+Sybqpj+BiwQpT0ix\n\tHKA6KLrZg058l9+s2lSd8+PdJzwKUhpqh8CtWmJxIZuzlMgUPcLocniAC5dZ2MgLyCpu\n\tJhboloG7GBRrFTCRNgPxU75eUKDMpTMwALcuY+tRPzD4TXWn7y8iWubwhtdo5cJucuyl\n\tW0hI5/oS9tqU3Md0uCdHFjK8RKleL+d5FRYzmfkDIRm6jxh3Ui3JSxcz/VsVWXR/0y9c\n\truwwyPPg/mm136/LFaf4pF3PP92YWTuJ06ko7AG39QGKWg+HcEQqjQSRjZa5c4wK0lpM\n\tM36g==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=kmll9l4eAvYUwnIen3TWbsYuSMORrldpFD+hfGSzAsY=;\n\tb=MKau8KdMTFY2Hccai+fa4EVBb82v4xWrlJN0qf4Z57dPdNswuMnzt+GvPieWJIaY8o\n\tqOewRdLgzbmQCv+dAkLKtpgFhhIhcdRN2NhEEnJZ3IqwCSlB2urHQMBxawfLlVdjpKuH\n\t47U1tXg3Tu8bsJl2MSqkBrxIVHOtwxxVaeHKBJnHJiTkJwUW5pZ7IgiVqqA+LPPEE9Rc\n\tHw9fSIt8KGmILLvMjyELSSmFU/GjbbSAd2Emg/PAHoc/K0zz2iKChoAqf3E4WQX1xEo/\n\tzbiMaZ26zVCNlYMD5OPfPWB/xOLOtaJwftwzJWR34p4Ig7yDesDI2/zIWdG/ryc49T4c\n\tMnNw==","X-Gm-Message-State":"AHPjjUgv9+nFg7OnDL4UoOgnYmFQ+edozd+BimKsglDZSu3AbAfi91L5\n\tKeDG6eMV+qJx0702tkBcMro=","X-Google-Smtp-Source":"AOwi7QCUd5yPWnj1p6AjLk702on1A1wVgLzyK6hnqT1u0dESyQWhvmWxF2/hSoRlQ5HfXHN/f+y6hw==","X-Received":"by 10.223.195.108 with SMTP id e41mr3539544wrg.51.1506258758775; \n\tSun, 24 Sep 2017 06:12:38 -0700 (PDT)","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","To":"Vignesh R , Cyrille Pitchen ","Cc":"David Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\tlinux-mtd@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>\n\t<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>","From":"Marek Vasut ","Message-ID":"","Date":"Sun, 24 Sep 2017 15:12:37 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774183,"web_url":"http://patchwork.ozlabs.org/comment/1774183/","msgid":"","list_archive_url":null,"date":"2017-09-24T13:13:56","subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 02:33 PM, Vignesh R wrote:\n> \n> \n> On 9/24/2017 5:29 PM, Marek Vasut wrote:\n>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access\n>>> Controller programming sequence, a delay equal to couple of QSPI master\n>>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and\n>>> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY\n>>> to handle this and set this flag for TI 66AK2G SoC.\n>>>\n>>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf\n>>>\n>>> Signed-off-by: Vignesh R \n>>\n>> Is this TI specific or is this controller property ? I wouldn't be\n>> surprised of the later ...\n> \n> I am not sure, there is no generic public documentation by cadence for\n> this IP. TI TRM clearly states this delay is required and I have\n> verified it practically that this delay is indeed needed.\n> But current user of this IP, socfpga does not seem to mention anything\n> about it. So, I guess its TI specific quirk.\n\nOK, let's go with that then. I didn't observe any stability issues with\nSoCFPGA, but I didn't run the flash at 100s of MHz either. At what kind\nof frequencies does the quirk become relevant ?\n\n>>\n>>> ---\n>>>\n>>> v3:\n>>> Fix build warnings reported by kbuild test bot.\n>>>\n>>> drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-\n>>> 1 file changed, 26 insertions(+), 1 deletion(-)\n>>>\n>>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>>> index 53c7d8e0327a..5cd5d6f7303f 100644\n>>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>>> @@ -38,6 +38,9 @@\n>>> #define CQSPI_NAME\t\t\t\"cadence-qspi\"\n>>> #define CQSPI_MAX_CHIPSELECT\t\t16\n>>> \n>>> +/* Quirks */\n>>> +#define CQSPI_NEEDS_WR_DELAY\t\tBIT(0)\n>>> +\n>>> struct cqspi_st;\n>>> \n>>> struct cqspi_flash_pdata {\n>>> @@ -76,6 +79,7 @@ struct cqspi_st {\n>>> \tu32\t\t\tfifo_depth;\n>>> \tu32\t\t\tfifo_width;\n>>> \tu32\t\t\ttrigger_address;\n>>> +\tu32\t\t\twr_delay;\n>>> \tstruct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];\n>>> };\n>>> \n>>> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,\n>>> \treinit_completion(&cqspi->transfer_complete);\n>>> \twritel(CQSPI_REG_INDIRECTWR_START_MASK,\n>>> \t reg_base + CQSPI_REG_INDIRECTWR);\n>>> +\t/*\n>>> +\t * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access\n>>> +\t * Controller programming sequence, couple of cycles of\n>>> +\t * QSPI_REF_CLK delay is required for the above bit to\n>>> +\t * be internally synchronized by the QSPI module. Provide 5\n>>> +\t * cycles of delay.\n>>> +\t */\n>>> +\tif (cqspi->wr_delay)\n>>> +\t\tndelay(cqspi->wr_delay);\n>>> \n>>> \twhile (remaining > 0) {\n>>> \t\twrite_bytes = remaining > page_size ? page_size : remaining;\n>>> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)\n>>> \tstruct cqspi_st *cqspi;\n>>> \tstruct resource *res;\n>>> \tstruct resource *res_ahb;\n>>> +\tunsigned long data;\n>>> \tint ret;\n>>> \tint irq;\n>>> \n>>> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)\n>>> \t}\n>>> \n>>> \tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>>> +\tdata = (unsigned long)of_device_get_match_data(dev);\n>>> +\tif (data & CQSPI_NEEDS_WR_DELAY)\n>>> +\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n>>> +\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n>>> \n>>> \tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n>>> \t\t\t pdev->name, cqspi);\n>>> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {\n>>> #endif\n>>> \n>>> static const struct of_device_id cqspi_dt_ids[] = {\n>>> -\t{.compatible = \"cdns,qspi-nor\",},\n>>> +\t{\n>>> +\t\t.compatible = \"cdns,qspi-nor\",\n>>> +\t\t.data = (void *)0,\n>>> +\t},\n>>> +\t{\n>>> +\t\t.compatible = \"ti,k2g-qspi\",\n>>> +\t\t.data = (void *)CQSPI_NEEDS_WR_DELAY,\n>>> +\t},\n>>> \t{ /* end of table */ }\n>>> };\n>>> \n>>>\n>>\n>>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tSun, 24 Sep 2017 06:13:57 -0700 (PDT)","Subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","To":"Vignesh R , Cyrille Pitchen ","Cc":"David Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\tlinux-mtd@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-3-vigneshr@ti.com>\n\t<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>\n\t<8990b971-91d5-747f-905b-5e24743e090d@ti.com>","From":"Marek Vasut ","Message-ID":"","Date":"Sun, 24 Sep 2017 15:13:56 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<8990b971-91d5-747f-905b-5e24743e090d@ti.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774187,"web_url":"http://patchwork.ozlabs.org/comment/1774187/","msgid":"<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>","list_archive_url":null,"date":"2017-09-24T13:27:30","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"On 9/24/2017 6:42 PM, Marek Vasut wrote:\n> On 09/24/2017 03:08 PM, Vignesh R wrote:\n>>\n>>\n>> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>>\n>>>> Signed-off-by: Vignesh R \n>>>\n>>> Are you planning to add some more fine-grained PM control later?\n>>\n>> Yes, I will need to add fine-grained PM control at some point. But, for\n>> now SoC does not really support low power mode or runtime power saving\n>> option.\n>> The fact that driver still uses clk_prepare_*() calls to enable/disable\n>> clocks instead of pm_*() calls makes it a bit tricky though.\n>>\n>> Just figured out I forgot to add cleanup code in error handling path of\n>> probe(). Will fix that and send a v4.\n> \n> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\n> either, so it's fine for now.\n> \n\nOk thanks! Do you know if pm_runtime_get_sync() can enable clocks for\nQSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\nif its possible to get rid of clk_*() calls in favor of pm_*() calls.\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"wCnYb//M\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0Shx0FQTz9sRm\n\tfor ;\n\tSun, 24 Sep 2017 23:28:32 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752476AbdIXN2a (ORCPT\n\t);\n\tSun, 24 Sep 2017 09:28:30 -0400","from lelnx194.ext.ti.com ([198.47.27.80]:28300 \"EHLO\n\tlelnx194.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752437AbdIXN23 (ORCPT\n\t); Sun, 24 Sep 2017 09:28:29 -0400","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8ODRakU004576; \n\tSun, 24 Sep 2017 08:27:36 -0500","from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8ODRaw3015498;\n\tSun, 24 Sep 2017 08:27:36 -0500","from DFLE102.ent.ti.com (10.64.6.23) by DFLE112.ent.ti.com\n\t(10.64.6.33) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tSun, 24 Sep 2017 08:27:36 -0500","from dlep32.itg.ti.com (157.170.170.100) by DFLE102.ent.ti.com\n\t(10.64.6.23) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Sun, 24 Sep 2017 08:27:36 -0500","from [172.22.218.57] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8ODRVCm018249;\n\tSun, 24 Sep 2017 08:27:32 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506259656;\n\tbh=6cTk15AFBdDOnLJfVCJvqBics3ytgMCy13z2Zyqs0oI=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=wCnYb//MdN4kROW8vPg+m/Id/6/vx3iXfYZQfdmNpM7bPnjqaPLxUfKUHqZzcnXCi\n\t//72kbwQLTQycWuXZIUGykvTO9h34LQxN30gbp8yA3LQPWVcnQn53UKz+MKbEJZRGP\n\tx8gS3LEFoNcP+FIqhUxR5nImTz2VdGaxNglBLd0o=","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","To":"Marek Vasut ,\n\tCyrille Pitchen ","CC":"David Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\t, ,\n\t,\n\tlinux-arm-kernel ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>\n\t<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>\n\t","From":"Vignesh R ","Message-ID":"<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>","Date":"Sun, 24 Sep 2017 18:57:30 +0530","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774196,"web_url":"http://patchwork.ozlabs.org/comment/1774196/","msgid":"","list_archive_url":null,"date":"2017-09-24T13:51:55","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/24/2017 03:27 PM, Vignesh R wrote:\n> \n> \n> On 9/24/2017 6:42 PM, Marek Vasut wrote:\n>> On 09/24/2017 03:08 PM, Vignesh R wrote:\n>>>\n>>>\n>>> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>>>\n>>>>> Signed-off-by: Vignesh R \n>>>>\n>>>> Are you planning to add some more fine-grained PM control later?\n>>>\n>>> Yes, I will need to add fine-grained PM control at some point. But, for\n>>> now SoC does not really support low power mode or runtime power saving\n>>> option.\n>>> The fact that driver still uses clk_prepare_*() calls to enable/disable\n>>> clocks instead of pm_*() calls makes it a bit tricky though.\n>>>\n>>> Just figured out I forgot to add cleanup code in error handling path of\n>>> probe(). Will fix that and send a v4.\n>>\n>> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\n>> either, so it's fine for now.\n>>\n> \n> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n\nNot of the top of my head, sorry. +CC Matthew, he should know.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"pqU7tp/g\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y0TD173Pmz9sRV\n\tfor ;\n\tSun, 24 Sep 2017 23:52:01 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752352AbdIXNv6 (ORCPT\n\t);\n\tSun, 24 Sep 2017 09:51:58 -0400","from mail-wm0-f68.google.com ([74.125.82.68]:33472 \"EHLO\n\tmail-wm0-f68.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752396AbdIXNv5 (ORCPT\n\t); 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1775005,"web_url":"http://patchwork.ozlabs.org/comment/1775005/","msgid":"","list_archive_url":null,"date":"2017-09-25T22:41:40","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":70992,"url":"http://patchwork.ozlabs.org/api/people/70992/","name":"Matthew Gerlach","email":"matthew.gerlach@linux.intel.com"},"content":"On Sun, 24 Sep 2017, Marek Vasut wrote:\n\n> On 09/24/2017 03:27 PM, Vignesh R wrote:\n>>\n>>\n>> On 9/24/2017 6:42 PM, Marek Vasut wrote:\n>>> On 09/24/2017 03:08 PM, Vignesh R wrote:\n>>>>\n>>>>\n>>>> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>>>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>>>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>>>>\n>>>>>> Signed-off-by: Vignesh R \n>>>>>\n>>>>> Are you planning to add some more fine-grained PM control later?\n>>>>\n>>>> Yes, I will need to add fine-grained PM control at some point. But, for\n>>>> now SoC does not really support low power mode or runtime power saving\n>>>> option.\n>>>> The fact that driver still uses clk_prepare_*() calls to enable/disable\n>>>> clocks instead of pm_*() calls makes it a bit tricky though.\n>>>>\n>>>> Just figured out I forgot to add cleanup code in error handling path of\n>>>> probe(). Will fix that and send a v4.\n>>>\n>>> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\n>>> either, so it's fine for now.\n>>>\n>>\n>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n>> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n>\n> Not of the top of my head, sorry. +CC Matthew, he should know.\n\nI am not an expert at the clock framework nor the power management, but I\ndid ask around a bit. No one I asked was planning to change the clk_*()\ncalls to pm_*() call, but the feedback was that it would be a good idea.\n\nMatthew Gerlach\n\n\n>\n> -- \n> Best regards,\n> Marek Vasut\n>\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1Jwp26MYz9sRV\n\tfor ;\n\tTue, 26 Sep 2017 08:41:46 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S934513AbdIYWlo (ORCPT );\n\tMon, 25 Sep 2017 18:41:44 -0400","from mga05.intel.com ([192.55.52.43]:44663 \"EHLO mga05.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S934254AbdIYWlo (ORCPT );\n\tMon, 25 Sep 2017 18:41:44 -0400","from orsmga005.jf.intel.com ([10.7.209.41])\n\tby fmsmga105.fm.intel.com with ESMTP; 25 Sep 2017 15:41:43 -0700","from mgerlach-mobl.amr.corp.intel.com (HELO [10.0.2.15])\n\t([10.255.79.44])\n\tby orsmga005.jf.intel.com with ESMTP; 25 Sep 2017 15:41:42 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,437,1500966000\"; d=\"scan'208\";a=\"153240557\"","Date":"Mon, 25 Sep 2017 15:41:40 -0700 (PDT)","From":"matthew.gerlach@linux.intel.com","X-X-Sender":"mgerlach@mgerlach-VirtualBox","To":"Marek Vasut ","cc":"Vignesh R , Cyrille Pitchen ,\n\tDavid Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\tlinux-mtd@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel ","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","In-Reply-To":"","Message-ID":"","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>\n\t<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>\n\t\n\t<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>\n\t","User-Agent":"Alpine 2.20 (DEB 67 2015-01-07)","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII; format=flowed","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1775049,"web_url":"http://patchwork.ozlabs.org/comment/1775049/","msgid":"","list_archive_url":null,"date":"2017-09-25T23:49:46","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":1124,"url":"http://patchwork.ozlabs.org/api/people/1124/","name":"Marek Vasut","email":"marek.vasut@gmail.com"},"content":"On 09/26/2017 12:41 AM, matthew.gerlach@linux.intel.com wrote:\n> \n> \n> On Sun, 24 Sep 2017, Marek Vasut wrote:\n> \n>> On 09/24/2017 03:27 PM, Vignesh R wrote:\n>>>\n>>>\n>>> On 9/24/2017 6:42 PM, Marek Vasut wrote:\n>>>> On 09/24/2017 03:08 PM, Vignesh R wrote:\n>>>>>\n>>>>>\n>>>>> On 9/24/2017 5:31 PM, Marek Vasut wrote:\n>>>>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>>>>> Add pm_runtime* calls to cadence-quadspi driver. This is required to\n>>>>>>> switch on QSPI power domain on TI 66AK2G SoC during probe.\n>>>>>>>\n>>>>>>> Signed-off-by: Vignesh R \n>>>>>>\n>>>>>> Are you planning to add some more fine-grained PM control later?\n>>>>>\n>>>>> Yes, I will need to add fine-grained PM control at some point. But,\n>>>>> for\n>>>>> now SoC does not really support low power mode or runtime power saving\n>>>>> option.\n>>>>> The fact that driver still uses clk_prepare_*() calls to\n>>>>> enable/disable\n>>>>> clocks instead of pm_*() calls makes it a bit tricky though.\n>>>>>\n>>>>> Just figured out I forgot to add cleanup code in error handling\n>>>>> path of\n>>>>> probe(). Will fix that and send a v4.\n>>>>\n>>>> OK, fine. Cleanups are welcome. The SoCFPGA doesn't do much runtime PM\n>>>> either, so it's fine for now.\n>>>>\n>>>\n>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n>>\n>> Not of the top of my head, sorry. +CC Matthew, he should know.\n> \n> I am not an expert at the clock framework nor the power management, but I\n> did ask around a bit.  No one I asked was planning to change the clk_*()\n> calls to pm_*() call, but the feedback was that it would be a good idea.\n\nThe question is, if we do the replacement, will it break on socfpga ?\nA quick test might be useful.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"a21DzvEi\"; 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\n\tMon, 25 Sep 2017 16:49:48 -0700 (PDT)","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","To":"matthew.gerlach@linux.intel.com","Cc":"Vignesh R , Cyrille Pitchen ,\n\tDavid Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\tlinux-mtd@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>\n\t<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>\n\t\n\t<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>\n\t\n\t","From":"Marek Vasut ","Message-ID":"","Date":"Tue, 26 Sep 2017 01:49:46 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1777085,"web_url":"http://patchwork.ozlabs.org/comment/1777085/","msgid":"","list_archive_url":null,"date":"2017-09-28T15:01:36","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":70992,"url":"http://patchwork.ozlabs.org/api/people/70992/","name":"Matthew Gerlach","email":"matthew.gerlach@linux.intel.com"},"content":"Hi Vignesh,\n\nI tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi \nkernel, and it did not go well. Commands to the flash chip timedout \nresulting in the probe function failing. I ran into other problems, not \nrelated to cadence-quadspi, that prevented me from testing against 4.9 and \n4.12 kernels, but I suspect similar behavior.\n\nMatthew Gerlach\n\nOn Wed, 27 Sep 2017, Vignesh R wrote:\n\n> Hi Matthew,\n>\n> On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote:\n> [...]\n>>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n>>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n>>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n>>>>\n>>>> Not of the top of my head, sorry. +CC Matthew, he should know.\n>>>\n>>> I am not an expert at the clock framework nor the power management, but I\n>>> did ask around a bit.  No one I asked was planning to change the clk_*()\n>>> calls to pm_*() call, but the feedback was that it would be a good idea.\n>>\n>> The question is, if we do the replacement, will it break on socfpga ?\n>> A quick test might be useful.\n>>\n>\n> yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls\n> like below patch would be helpful:\n>\n>\n> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n> index 53c7d8e0327a..7ad3e176cc88 100644\n> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n> @@ -34,6 +34,7 @@\n> #include \n> #include \n> #include \n> +#include \n>\n> #define CQSPI_NAME \"cadence-qspi\"\n> #define CQSPI_MAX_CHIPSELECT 16\n> @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev)\n> return -ENXIO;\n> }\n>\n> - ret = clk_prepare_enable(cqspi->clk);\n> - if (ret) {\n> - dev_err(dev, \"Cannot enable QSPI clock.\\n\");\n> - return ret;\n> - }\n> + pm_runtime_enable(dev);\n> + pm_runtime_get_sync(dev);\n>\n> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>\n>\n>\n>\n>\n> -- \n> Regards\n> Vignesh\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2yZk0gk0z9t66\n\tfor ;\n\tFri, 29 Sep 2017 01:01:50 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753316AbdI1PBn (ORCPT\n\t);\n\tThu, 28 Sep 2017 11:01:43 -0400","from mga01.intel.com ([192.55.52.88]:16561 \"EHLO mga01.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752506AbdI1PBm (ORCPT );\n\tThu, 28 Sep 2017 11:01:42 -0400","from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t28 Sep 2017 08:01:39 -0700","from mgerlach-mobl.amr.corp.intel.com (HELO [10.0.2.15])\n\t([10.252.139.46])\n\tby fmsmga005.fm.intel.com with ESMTP; 28 Sep 2017 08:01:38 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,450,1500966000\"; d=\"scan'208\";a=\"156599517\"","Date":"Thu, 28 Sep 2017 08:01:36 -0700 (PDT)","From":"matthew.gerlach@linux.intel.com","X-X-Sender":"mgerlach@mgerlach-VirtualBox","To":"Vignesh R ","cc":"Marek Vasut ,\n\tCyrille Pitchen ,\n\tDavid Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\tlinux-mtd@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel ","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","In-Reply-To":"<7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com>","Message-ID":"","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>\n\t<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>\n\t\n\t<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>\n\t\n\t\n\t\n\t<7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com>","User-Agent":"Alpine 2.20 (DEB 67 2015-01-07)","MIME-Version":"1.0","Content-Type":"multipart/mixed; BOUNDARY=\"8323329-1557128041-1506610898=:2488\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1778288,"web_url":"http://patchwork.ozlabs.org/comment/1778288/","msgid":"<5bc42364-21e1-56b6-788c-2848b8faa50f@ti.com>","list_archive_url":null,"date":"2017-10-02T12:28:55","subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"Hi,\n\nOn 9/28/2017 8:31 PM, matthew.gerlach@linux.intel.com wrote:\n> \n> Hi Vignesh,\n> \n> I tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi \n> kernel, and it did not go well. Commands to the flash chip timedout \n> resulting in the probe function failing. I ran into other problems, not \n> related to cadence-quadspi, that prevented me from testing against 4.9 and \n> 4.12 kernels, but I suspect similar behavior.\n> \n\nOk, thanks! I will keep the clk_*() calls for now.\n\nRegards\nVignesh\n> Matthew Gerlach\n> \n> On Wed, 27 Sep 2017, Vignesh R wrote:\n> \n>> Hi Matthew,\n>>\n>> On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote:\n>> [...]\n>>>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for\n>>>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see\n>>>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls.\n>>>>>\n>>>>> Not of the top of my head, sorry. +CC Matthew, he should know.\n>>>>\n>>>> I am not an expert at the clock framework nor the power management, but I\n>>>> did ask around a bit.  No one I asked was planning to change the clk_*()\n>>>> calls to pm_*() call, but the feedback was that it would be a good idea.\n>>>\n>>> The question is, if we do the replacement, will it break on socfpga ?\n>>> A quick test might be useful.\n>>>\n>>\n>> yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls\n>> like below patch would be helpful:\n>>\n>>\n>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> index 53c7d8e0327a..7ad3e176cc88 100644\n>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>> @@ -34,6 +34,7 @@\n>> #include \n>> #include \n>> #include \n>> +#include \n>>\n>> #define CQSPI_NAME \"cadence-qspi\"\n>> #define CQSPI_MAX_CHIPSELECT 16\n>> @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev)\n>> return -ENXIO;\n>> }\n>>\n>> - ret = clk_prepare_enable(cqspi->clk);\n>> - if (ret) {\n>> - dev_err(dev, \"Cannot enable QSPI clock.\\n\");\n>> - return ret;\n>> - }\n>> + pm_runtime_enable(dev);\n>> + pm_runtime_get_sync(dev);\n>>\n>> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>>\n>>\n>>\n>>\n>>\n>> -- \n>> Regards\n>> Vignesh\n>>\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"ddKb7Rmh\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y5M1m1Ygtz9t4c\n\tfor ;\n\tMon, 2 Oct 2017 23:30:04 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751145AbdJBMaC (ORCPT\n\t);\n\tMon, 2 Oct 2017 08:30:02 -0400","from lelnx194.ext.ti.com ([198.47.27.80]:35041 \"EHLO\n\tlelnx194.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750978AbdJBMaB (ORCPT\n\t); Mon, 2 Oct 2017 08:30:01 -0400","from dflxv15.itg.ti.com ([128.247.5.124])\n\tby lelnx194.ext.ti.com (8.15.1/8.15.1) with ESMTP id v92CT0Qv014407; \n\tMon, 2 Oct 2017 07:29:00 -0500","from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34])\n\tby dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v92CT0qs032621;\n\tMon, 2 Oct 2017 07:29:00 -0500","from DLEE101.ent.ti.com (157.170.170.31) by DLEE104.ent.ti.com\n\t(157.170.170.34) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tMon, 2 Oct 2017 07:28:59 -0500","from dlep33.itg.ti.com (157.170.170.75) by DLEE101.ent.ti.com\n\t(157.170.170.31) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Mon, 2 Oct 2017 07:29:00 -0500","from [172.22.217.158] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v92CStG9031830;\n\tMon, 2 Oct 2017 07:28:56 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506947340;\n\tbh=w6bZDGs8nZtmZIJLRM+aNeYg43MFvjUnu1eZEo0SNVE=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=ddKb7Rmh0KqhZfw9N8igCk1R+/dFSnEhqXXVyciGVZJRlsrIn6LCMOqGMNprR5eoM\n\tpvt1I+rW1YYshcTZu4YL424e/q0qzGQm24eNp6+NQUpWsS46MDQkiFWFOTcMGv9wXp\n\tvVfMDsgUn+WPnW9m55115yx0o78KvDjZVA2S1uNI=","Subject":"Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM\n\tsupport","To":"\"matthew.gerlach@linux.intel.com\" ","CC":"Marek Vasut ,\n\tCyrille Pitchen ,\n\tDavid Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\t\"linux-mtd@lists.infradead.org\" ,\n\t\"devicetree@vger.kernel.org\" ,\n\t\"linux-kernel@vger.kernel.org\" ,\n\tlinux-arm-kernel ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-6-vigneshr@ti.com>\n\t<3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com>\n\t<4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com>\n\t\n\t<038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com>\n\t\n\t\n\t\n\t<7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com>\n\t","From":"Vignesh R ","Message-ID":"<5bc42364-21e1-56b6-788c-2848b8faa50f@ti.com>","Date":"Mon, 2 Oct 2017 17:58:55 +0530","User-Agent":"Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"8bit","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1778300,"web_url":"http://patchwork.ozlabs.org/comment/1778300/","msgid":"<07137a92-244b-e009-54ae-71f733860f28@ti.com>","list_archive_url":null,"date":"2017-10-02T12:46:40","subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","submitter":{"id":65039,"url":"http://patchwork.ozlabs.org/api/people/65039/","name":"Raghavendra, Vignesh","email":"vigneshr@ti.com"},"content":"On 9/24/2017 6:43 PM, Marek Vasut wrote:\n> On 09/24/2017 02:33 PM, Vignesh R wrote:\n>>\n>>\n>> On 9/24/2017 5:29 PM, Marek Vasut wrote:\n>>> On 09/24/2017 12:59 PM, Vignesh R wrote:\n>>>> As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access\n>>>> Controller programming sequence, a delay equal to couple of QSPI master\n>>>> clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and\n>>>> writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY\n>>>> to handle this and set this flag for TI 66AK2G SoC.\n>>>>\n>>>> [1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf\n>>>>\n>>>> Signed-off-by: Vignesh R \n>>>\n>>> Is this TI specific or is this controller property ? I wouldn't be\n>>> surprised of the later ...\n>>\n>> I am not sure, there is no generic public documentation by cadence for\n>> this IP. TI TRM clearly states this delay is required and I have\n>> verified it practically that this delay is indeed needed.\n>> But current user of this IP, socfpga does not seem to mention anything\n>> about it. So, I guess its TI specific quirk.\n> \n> OK, let's go with that then. I didn't observe any stability issues with\n> SoCFPGA, but I didn't run the flash at 100s of MHz either. At what kind\n> of frequencies does the quirk become relevant ?\n> \n\nActually, delay is tied to QSPI master clk rate(not SPI bus clk rate).\nIt runs at 384MHz. Changing SPI bus rate has no effect.\n\nRegards\nVignesh\n\n>>>\n>>>> ---\n>>>>\n>>>> v3:\n>>>> Fix build warnings reported by kbuild test bot.\n>>>>\n>>>> drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++++++++++++++++-\n>>>> 1 file changed, 26 insertions(+), 1 deletion(-)\n>>>>\n>>>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c\n>>>> index 53c7d8e0327a..5cd5d6f7303f 100644\n>>>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c\n>>>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c\n>>>> @@ -38,6 +38,9 @@\n>>>> #define CQSPI_NAME\t\t\t\"cadence-qspi\"\n>>>> #define CQSPI_MAX_CHIPSELECT\t\t16\n>>>> \n>>>> +/* Quirks */\n>>>> +#define CQSPI_NEEDS_WR_DELAY\t\tBIT(0)\n>>>> +\n>>>> struct cqspi_st;\n>>>> \n>>>> struct cqspi_flash_pdata {\n>>>> @@ -76,6 +79,7 @@ struct cqspi_st {\n>>>> \tu32\t\t\tfifo_depth;\n>>>> \tu32\t\t\tfifo_width;\n>>>> \tu32\t\t\ttrigger_address;\n>>>> +\tu32\t\t\twr_delay;\n>>>> \tstruct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];\n>>>> };\n>>>> \n>>>> @@ -608,6 +612,15 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,\n>>>> \treinit_completion(&cqspi->transfer_complete);\n>>>> \twritel(CQSPI_REG_INDIRECTWR_START_MASK,\n>>>> \t reg_base + CQSPI_REG_INDIRECTWR);\n>>>> +\t/*\n>>>> +\t * As per 66AK2G02 TRM SPRUHY8F section 11.15.5.3 Indirect Access\n>>>> +\t * Controller programming sequence, couple of cycles of\n>>>> +\t * QSPI_REF_CLK delay is required for the above bit to\n>>>> +\t * be internally synchronized by the QSPI module. Provide 5\n>>>> +\t * cycles of delay.\n>>>> +\t */\n>>>> +\tif (cqspi->wr_delay)\n>>>> +\t\tndelay(cqspi->wr_delay);\n>>>> \n>>>> \twhile (remaining > 0) {\n>>>> \t\twrite_bytes = remaining > page_size ? page_size : remaining;\n>>>> @@ -1156,6 +1169,7 @@ static int cqspi_probe(struct platform_device *pdev)\n>>>> \tstruct cqspi_st *cqspi;\n>>>> \tstruct resource *res;\n>>>> \tstruct resource *res_ahb;\n>>>> +\tunsigned long data;\n>>>> \tint ret;\n>>>> \tint irq;\n>>>> \n>>>> @@ -1213,6 +1227,10 @@ static int cqspi_probe(struct platform_device *pdev)\n>>>> \t}\n>>>> \n>>>> \tcqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);\n>>>> +\tdata = (unsigned long)of_device_get_match_data(dev);\n>>>> +\tif (data & CQSPI_NEEDS_WR_DELAY)\n>>>> +\t\tcqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,\n>>>> +\t\t\t\t\t\t cqspi->master_ref_clk_hz);\n>>>> \n>>>> \tret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,\n>>>> \t\t\t pdev->name, cqspi);\n>>>> @@ -1284,7 +1302,14 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = {\n>>>> #endif\n>>>> \n>>>> static const struct of_device_id cqspi_dt_ids[] = {\n>>>> -\t{.compatible = \"cdns,qspi-nor\",},\n>>>> +\t{\n>>>> +\t\t.compatible = \"cdns,qspi-nor\",\n>>>> +\t\t.data = (void *)0,\n>>>> +\t},\n>>>> +\t{\n>>>> +\t\t.compatible = \"ti,k2g-qspi\",\n>>>> +\t\t.data = (void *)CQSPI_NEEDS_WR_DELAY,\n>>>> +\t},\n>>>> \t{ /* end of table */ }\n>>>> };\n>>>> \n>>>>\n>>>\n>>>\n> \n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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Mon, 2 Oct 2017 07:46:46 -0500","from [172.22.217.158] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v92Cke3b030547;\n\tMon, 2 Oct 2017 07:46:41 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506948406;\n\tbh=H3RjL1kLx1KII/o+Hf+Lj5y45ctD3ttPK2l2O8fUDyg=;\n\th=Subject:To:CC:References:From:Date:In-Reply-To;\n\tb=AAPB58NZpVErvHLm8IQ6eDKd6KWUA12F6br2Ed3BbIH4SnKzHKxko1WcYnyJRZV0U\n\t15fJKX1b+4K1u5m5ad0R5lg6axwVQUvC0MOtcudBxJRWNq9Z2WR+XsgMRrzNURZkTw\n\tcUGoFd8dDFpl/EshQ57/YskQikfxRur6zZOFbbDM=","Subject":"Re: [PATCH v3 2/5] mtd: spi-nor: cadence-quadspi: add a delay in\n\twrite sequence","To":"Marek Vasut ,\n\tCyrille Pitchen ","CC":"David Woodhouse ,\n\tBrian Norris ,\n\tBoris Brezillon ,\n\tRob Herring ,\n\t, ,\n\t,\n\tlinux-arm-kernel ","References":"<20170924105924.23923-1-vigneshr@ti.com>\n\t<20170924105924.23923-3-vigneshr@ti.com>\n\t<94313cae-4805-0b13-a469-72aa7556b685@gmail.com>\n\t<8990b971-91d5-747f-905b-5e24743e090d@ti.com>\n\t","From":"Vignesh R ","Message-ID":"<07137a92-244b-e009-54ae-71f733860f28@ti.com>","Date":"Mon, 2 Oct 2017 18:16:40 +0530","User-Agent":"Mozilla/5.0 (Windows NT 10.0; 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