[{"id":1774615,"web_url":"http://patchwork.ozlabs.org/comment/1774615/","msgid":"<20170925101027.lghnnll4h6inreqm@flea.home>","list_archive_url":null,"date":"2017-09-25T10:10:27","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi,\n\nOn Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n> This patchset imports simple DVFS support for Allwinner A64 SoC.\n> \n> As the thermal sensor driver is not yet implemented and some boards\n> have still no AXP PMIC support, now only two OPPs are present --\n> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n> \n> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n> set up the device tree bits of the DVFS on Pine64.\n\nHow has this been tested?\n\nWhat tasks did you run, with what governor, etc...\n\nThanks!\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"MeeZUzCW\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y10Gl6gX5z9tXF\n\tfor ;\n\tMon, 25 Sep 2017 20:11:11 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwQLy-0006xa-Or; Mon, 25 Sep 2017 10:11:06 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwQLt-0006ph-Ti for linux-arm-kernel@lists.infradead.org;\n\tMon, 25 Sep 2017 10:11:04 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 8064720A01; Mon, 25 Sep 2017 12:10:38 +0200 (CEST)","from localhost (unknown [109.190.253.16])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 2B77D209F6;\n\tMon, 25 Sep 2017 12:10:27 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=SAQTUDaxDvedAcJpvQtzrX3/xSQQuKaP17jS1EWOup0=;\n\tb=MeeZUzCWtXtaYdRhzCor91zND\n\to7eh3TPZSl+5G1gAGr6zagsUwiCro+kjSG0dxpCe+vYlgR0TsXQauxKNFw1yEdeJMgR9Yis8QeibY\n\t0iSxsv7xG2FvWqxEr8n87c5RUb/2uYes23ZyFlx0cfi7jNiHhI2ZsfcNdse6wbWbS8y5EGqt8byP2\n\tz42G+a72aH7z5Ba2IjlJjsrmoMwYLykdKdBKUpUy7GGmkYaqSWpaIMSo5oAq7qzG5TILpqmBElLsu\n\trbr54iaXtK3QtqbU96Qw7pi6u/wzXysGu1rqjp3VVg6xnUdQZyJ7tUXBkOmMoQhRG2wuRR4ce34vv\n\tm+QPefoIw==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 25 Sep 2017 12:10:27 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","Message-ID":"<20170925101027.lghnnll4h6inreqm@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<20170923001531.14285-1-icenowy@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170925_031102_111385_30FBF704 ","X-CRM114-Status":"GOOD ( 12.22 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"multipart/mixed;\n\tboundary=\"===============1315259496361551249==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1774624,"web_url":"http://patchwork.ozlabs.org/comment/1774624/","msgid":"<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>","list_archive_url":null,"date":"2017-09-25T10:12:09","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard 写到:\n>Hi,\n>\n>On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n>> This patchset imports simple DVFS support for Allwinner A64 SoC.\n>> \n>> As the thermal sensor driver is not yet implemented and some boards\n>> have still no AXP PMIC support, now only two OPPs are present --\n>> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n>> \n>> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n>> set up the device tree bits of the DVFS on Pine64.\n>\n>How has this been tested?\n>\n>What tasks did you run, with what governor, etc...\n\nI only tested manual frequency switching between 648MHz and\n816MHz, and tested the PLL stuck issue by change the OPPs to\nsome random value.\n\n>\n>Thanks!\n>Maxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Mon, 25 Sep 2017 10:12:27 +0000","from localhost (localhost [127.0.0.1]) (Authenticated sender:\n\ticenowy@aosc.io)\n\tby hermes.aosc.io (Postfix) with ESMTPSA id 03D8544CC1;\n\tMon, 25 Sep 2017 10:12:20 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:Message-ID:From:To:Subject:MIME-Version\n\t:References:In-Reply-To:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=4jgN3kd44wfmLfkpmMiV0EHE24Hay7ojMC65Biclo1M=;\n\tb=PTk+7nkHzAnqjB\n\torHNTPV1ZvHYNHgjqXMkoCpoYzC3gQ/q/AvCfCYd9TZUDCSXCAynNTfn/46ri1jhKIX5Rj2ILOAhY\n\tRHb0BYz5AYCFxHfFjyY9190fcnBrKP4WZJ8ZZZrOiYX2bbIjY/W7ElxytP3jr2ux788/+twBC9uR8\n\ti5zgKm49WqTDjaHCDjC7TUQ5zdBTCqnFxeKzk2iQ1kxQgzRqubhp4Fn+PFCXhPZuIN2Y5U4VY9cB0\n\tJcY/P1Xc7Ot6uDVmSiJpUxtT5wo79Fc8xl15dbvUnW/V7MGyAdKL314OYfn9Su6zhCQOKu95zmLNQ\n\t5BBDmy6+ddYAi3wsOuuw==;","X-Sender-Id":["lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io","lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io"],"X-MC-Relay":"Neutral","X-MailChannels-SenderId":"lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io","X-MailChannels-Auth-Id":"lmn-TZDUIOWCRQMW","X-Descriptive-Dime":"42e637fe15b3c372_1506334347053_2648970940","X-MC-Loop-Signature":"1506334347053:2488164480","X-MC-Ingress-Time":"1506334347053","Date":"Mon, 25 Sep 2017 18:12:09 +0800","In-Reply-To":"<20170925101027.lghnnll4h6inreqm@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>","MIME-Version":"1.0","Subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","To":"Maxime Ripard ","From":"Icenowy Zheng ","Message-ID":"<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170925_031254_641497_C0BF73E1 ","X-CRM114-Status":"UNSURE ( 8.53 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-4.7 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [23.83.222.31 listed in list.dnswl.org]\n\t-2.8 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2)\n\t[23.83.222.31 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1774633,"web_url":"http://patchwork.ozlabs.org/comment/1774633/","msgid":"<20170925102744.qixfwlheeimemhcf@flea.home>","list_archive_url":null,"date":"2017-09-25T10:27:44","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard 写到:\n> >Hi,\n> >\n> >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n> >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n> >> \n> >> As the thermal sensor driver is not yet implemented and some boards\n> >> have still no AXP PMIC support, now only two OPPs are present --\n> >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n> >> \n> >> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n> >> set up the device tree bits of the DVFS on Pine64.\n> >\n> >How has this been tested?\n> >\n> >What tasks did you run, with what governor, etc...\n> \n> I only tested manual frequency switching between 648MHz and\n> 816MHz, and tested the PLL stuck issue by change the OPPs to\n> some random value.\n\nIdeally, we should test that it's actually reliable. Poorly chosen\nOPPs might lead to corrupt data that you might not get before a while.\n\nPlease test using:\nhttps://linux-sunxi.org/Hardware_Reliability_Tests#Reliability_of_cpufreq_voltage.2Ffrequency_settings\n\nAnd post the report.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"A+W06Yjt\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y10ff08Ssz9tXF\n\tfor ;\n\tMon, 25 Sep 2017 20:28:26 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwQcf-000063-PN; Mon, 25 Sep 2017 10:28:21 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwQcb-0008Pq-3n for linux-arm-kernel@lists.infradead.org;\n\tMon, 25 Sep 2017 10:28:19 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 2D273209E3; Mon, 25 Sep 2017 12:27:55 +0200 (CEST)","from localhost (unknown [109.190.253.16])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id B4709208BF;\n\tMon, 25 Sep 2017 12:27:44 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=7uPVuxtM2yPO+n7yNc3nP/5qsBcI2YJYSzJOn30XwGo=;\n\tb=A+W06Yjtkfz7iF6/jt5Z3QPit\n\tvOoyPiGeG/xvdtpj28it9yYoM3B2XJ1Y3KPPfQ+F6FFv9/1w/uCX7RnO1Iq2iVUAqORGnJI9oEaj5\n\tFJB/HH2kZW7FpbLJpoRyZuIfMRrBwNZWgS5Bcg4aYBIIUNH8NFhyHtNGt1njteR5aYFQYybP/pCmz\n\t+29t5ySAirXF7LT3J41XePRvTfHpdLhdm7mSTRoUFj5bw49Qe+JHZLq4RwqqwEpJyH0glnPCrMi7l\n\t7Jao1Ie0+/AP/K7hoivpHBeO/Zxed763C3TUPERpcUHacQ+ShuMbPkIaHO997rx5tzQCeVbBidY/X\n\t6PtICBDTg==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 25 Sep 2017 12:27:44 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","Message-ID":"<20170925102744.qixfwlheeimemhcf@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>\n\t<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170925_032817_327217_43C3CFA2 ","X-CRM114-Status":"GOOD ( 15.13 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"multipart/mixed;\n\tboundary=\"===============6737746378181053406==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1774635,"web_url":"http://patchwork.ozlabs.org/comment/1774635/","msgid":"<1C624335-37C2-4F22-BE78-A94F26D1D248@aosc.io>","list_archive_url":null,"date":"2017-09-25T10:29:38","subject":"Re: [linux-sunxi] Re: [PATCH 0/3] Simple DVFS support for Allwinner\n\tA64 SoC","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard 写到:\n>On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n>> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard\n> 写到:\n>> >Hi,\n>> >\n>> >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n>> >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n>> >> \n>> >> As the thermal sensor driver is not yet implemented and some\n>boards\n>> >> have still no AXP PMIC support, now only two OPPs are present --\n>> >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n>> >> \n>> >> PATCH 1 is a fix to the CCU driver of A64, and the remaining\n>patches\n>> >> set up the device tree bits of the DVFS on Pine64.\n>> >\n>> >How has this been tested?\n>> >\n>> >What tasks did you run, with what governor, etc...\n>> \n>> I only tested manual frequency switching between 648MHz and\n>> 816MHz, and tested the PLL stuck issue by change the OPPs to\n>> some random value.\n>\n>Ideally, we should test that it's actually reliable. Poorly chosen\n>OPPs might lead to corrupt data that you might not get before a while.\n\nThese are OPPs from the official sys_config.fex .\n\n>\n>Please test using:\n>https://linux-sunxi.org/Hardware_Reliability_Tests#Reliability_of_cpufreq_voltage.2Ffrequency_settings\n>\n>And post the report.\n>\n>Maxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"LEvSgqgC\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y10lp2Y6Mz9tXD\n\tfor ;\n\tMon, 25 Sep 2017 20:32:54 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwQgz-000348-73; Mon, 25 Sep 2017 10:32:49 +0000","from butterfly.ash.relay.mailchannels.net ([23.83.222.27])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwQgu-0002wW-B4 for linux-arm-kernel@lists.infradead.org;\n\tMon, 25 Sep 2017 10:32:47 +0000","from relay.mailchannels.net (localhost [127.0.0.1])\n\tby relay.mailchannels.net (Postfix) with ESMTP id 1E8068A6E54;\n\tMon, 25 Sep 2017 10:32:19 +0000 (UTC)","from hermes.aosc.io (unknown [100.96.137.66])\n\t(Authenticated sender: lmn-TZDUIOWCRQMW)\n\tby relay.mailchannels.net (Postfix) with ESMTPA id 6E54D8A4092;\n\tMon, 25 Sep 2017 10:32:18 +0000 (UTC)","from hermes.aosc.io (hermes.aosc.io [172.20.62.11])\n\t(using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384)\n\tby 0.0.0.0:2500 (trex/5.9.14); Mon, 25 Sep 2017 10:32:19 +0000","from localhost (localhost [127.0.0.1]) (Authenticated sender:\n\ticenowy@aosc.io)\n\tby hermes.aosc.io (Postfix) with ESMTPSA id 07C4A48157;\n\tMon, 25 Sep 2017 10:31:09 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:Message-ID:From:To:Subject:MIME-Version\n\t:References:In-Reply-To:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=Q2o1L5noDKJLtiuAnzt/Muwvlcpe9GJe1qz7WBOAWcM=;\n\tb=LEvSgqgC7XtqPl\n\tSH4cqLumPgfGrlaDrpIk+cBKn/rUbyKW8wlRmf9chBjpLa8Ao33Nf8tl6Q3z4hU7tD1XME/J0zE2Z\n\tvY/3I+kcgI+oIy8dmuHU1MgwuecBtgabN2tn03y6bU4GgnWkRSUid47eTdWDpEMZR/BDY7xgn2cxG\n\tF70JKeDNYa/P+xSQkyaMlfJq4FSXCchGS/LgDCPZDihhbzsMgbBYtZ5x+iysNgMfuMBUpo2fy4Wdp\n\tPiB5jwVScdcNIN+VModljSdE21ijtg8lVwBGTILR35S2pHmCLwOIiHNxNxyt+T18lc4dUwVf5RDad\n\thZP1djqmjTepfDUxHIdw==;","X-Sender-Id":["lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io","lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io"],"X-MC-Relay":"Neutral","X-MailChannels-SenderId":"lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io","X-MailChannels-Auth-Id":"lmn-TZDUIOWCRQMW","X-Stop-Tasty":"74672a8a62987850_1506335538917_1340546876","X-MC-Loop-Signature":"1506335538917:2172190458","X-MC-Ingress-Time":"1506335538917","Date":"Mon, 25 Sep 2017 18:29:38 +0800","In-Reply-To":"<20170925102744.qixfwlheeimemhcf@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>\n\t<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>\n\t<20170925102744.qixfwlheeimemhcf@flea.home>","MIME-Version":"1.0","Subject":"Re: [linux-sunxi] Re: [PATCH 0/3] Simple DVFS support for Allwinner\n\tA64 SoC","To":"maxime.ripard@free-electrons.com,\n\tMaxime Ripard ","From":"Icenowy Zheng ","Message-ID":"<1C624335-37C2-4F22-BE78-A94F26D1D248@aosc.io>","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170925_033245_020029_C225A6BC ","X-CRM114-Status":"UNSURE ( 8.66 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [23.83.222.27 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[23.83.222.27 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1774641,"web_url":"http://patchwork.ozlabs.org/comment/1774641/","msgid":"<20170925104328.jttvrdbptor5zhsr@flea.home>","list_archive_url":null,"date":"2017-09-25T10:43:28","subject":"Re: [linux-sunxi] Re: [PATCH 0/3] Simple DVFS support for Allwinner\n\tA64 SoC","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Mon, Sep 25, 2017 at 10:29:38AM +0000, Icenowy Zheng wrote:\n> \n> \n> 于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard 写到:\n> >On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n> >> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard\n> > 写到:\n> >> >Hi,\n> >> >\n> >> >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n> >> >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n> >> >> \n> >> >> As the thermal sensor driver is not yet implemented and some\n> >boards\n> >> >> have still no AXP PMIC support, now only two OPPs are present --\n> >> >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n> >> >> \n> >> >> PATCH 1 is a fix to the CCU driver of A64, and the remaining\n> >patches\n> >> >> set up the device tree bits of the DVFS on Pine64.\n> >> >\n> >> >How has this been tested?\n> >> >\n> >> >What tasks did you run, with what governor, etc...\n> >> \n> >> I only tested manual frequency switching between 648MHz and\n> >> 816MHz, and tested the PLL stuck issue by change the OPPs to\n> >> some random value.\n> >\n> >Ideally, we should test that it's actually reliable. Poorly chosen\n> >OPPs might lead to corrupt data that you might not get before a while.\n> \n> These are OPPs from the official sys_config.fex .\n\nAnd the rest of the code isn't, such as the clock or regulator code\nthat is critical as well here.\n\nI'm not asking this out of nowhere, we've had to debug this more than\nonce already.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"OuqDaMwm\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y110r2pgnz9sNr\n\tfor ;\n\tMon, 25 Sep 2017 20:44:10 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwQrt-0000sa-8E; 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/* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-816000000 {\n> +\t\t\topp-hz = /bits/ 64 <816000000>;\n> +\t\t\topp-microvolt = <1100000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\t};\n> +\n> \tcpus {\n> \t\t#address-cells = <1>;\n> \t\t#size-cells = <0>;\n> @@ -61,6 +78,10 @@\n> \t\t\tdevice_type = \"cpu\";\n> \t\t\treg = <0>;\n> \t\t\tenable-method = \"psci\";\n> +\t\t\tclocks = <&ccu CLK_CPUX>;\nCLK_CPUX is not currently exposed in the dt-bindings header, so this\ndoesn't compile.\n\n> +\t\t\tclock-names = \"cpu\";\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> +\t\t\t#cooling-cells = <2>;\n> \t\t};\n> \n> \t\tcpu1: cpu@1 {\n> @@ -68,6 +89,7 @@\n> \t\t\tdevice_type = \"cpu\";\n> \t\t\treg = <1>;\n> \t\t\tenable-method = \"psci\";\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> \t\t};\n> \n> \t\tcpu2: cpu@2 {\n> @@ -75,6 +97,7 @@\n> \t\t\tdevice_type = \"cpu\";\n> \t\t\treg = <2>;\n> \t\t\tenable-method = \"psci\";\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> \t\t};\n> \n> \t\tcpu3: cpu@3 {\n> @@ -82,6 +105,7 @@\n> \t\t\tdevice_type = \"cpu\";\n> \t\t\treg = <3>;\n> \t\t\tenable-method = \"psci\";\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> \t\t};\n> \t};\n> \n> \n\nThanks,\nSamuel","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.0","MIME-Version":"1.0","In-Reply-To":"<20170923001531.14285-3-icenowy@aosc.io>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170925_103914_797629_A5D2AAC1 ","X-CRM114-Status":"GOOD ( 10.23 )","X-Spam-Score":"-2.7 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [66.111.4.25 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[66.111.4.25 listed in wl.mailspike.net]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's\n\tdomain -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-clk@vger.kernel.org","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776276,"web_url":"http://patchwork.ozlabs.org/comment/1776276/","msgid":"<9b3aeb6cb155bb2f9a7cee438de82ccb@aosc.io>","list_archive_url":null,"date":"2017-09-27T11:51:30","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"在 2017-09-25 18:27，Maxime Ripard 写道：\n> On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n>> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard \n>> 写到:\n>> >Hi,\n>> >\n>> >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n>> >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n>> >>\n>> >> As the thermal sensor driver is not yet implemented and some boards\n>> >> have still no AXP PMIC support, now only two OPPs are present --\n>> >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n>> >>\n>> >> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n>> >> set up the device tree bits of the DVFS on Pine64.\n>> >\n>> >How has this been tested?\n>> >\n>> >What tasks did you run, with what governor, etc...\n>> \n>> I only tested manual frequency switching between 648MHz and\n>> 816MHz, and tested the PLL stuck issue by change the OPPs to\n>> some random value.\n> \n> Ideally, we should test that it's actually reliable. Poorly chosen\n> OPPs might lead to corrupt data that you might not get before a while.\n> \n> Please test using:\n> https://linux-sunxi.org/Hardware_Reliability_Tests#Reliability_of_cpufreq_voltage.2Ffrequency_settings\n> \n> And post the report.\n\n```\nroot@p64 [ cpuburn-arm@master ] # ./cpuburn-a53 &\n[1] 2543\nroot@p64 [ cpuburn-arm@master ] # ./cpufreq-ljt-stress-test\nCreating './whitenoise-1920x1080.jpg' ... done\nCPU stress test, which is doing JPEG decoding by libjpeg-turbo\nat different cpufreq operating points.\n\nTesting CPU 0\n 816 MHz ............................................................ \nOK\n 648 MHz ............................................................ \nOK\n\nTesting CPU 1\n 816 MHz ............................................................ \nOK\n 648 MHz ............................................................ \nOK\n\nTesting CPU 2\n 816 MHz ............................................................ \nOK\n 648 MHz ............................................................ \nOK\n\nTesting CPU 3\n 816 MHz ............................................................ \nOK\n 648 MHz ............................................................ \nOK\n\nOverall result : PASSED\n```\n\n> \n> Maxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"utf-8\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776938,"web_url":"http://patchwork.ozlabs.org/comment/1776938/","msgid":"<20170928102752.ceo54qccqakb4xyx@flea>","list_archive_url":null,"date":"2017-09-28T10:27:52","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi,\n\nOn Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n> The A64 PLL_CPU clock has the same instability if some factor changed\n> without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n> H3.\n> \n> Add the mux and pll notifiers for A64 CPU clock to workaround the\n> problem.\n> \n> Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n> Signed-off-by: Icenowy Zheng \n> ---\n> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28 +++++++++++++++++++++++++++-\n> 1 file changed, 27 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> index 2bb4cabf802f..b55fa69dd0c1 100644\n> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {\n> \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n> };\n> \n> +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n> +\t.common\t= &pll_cpux_clk.common,\n> +\t/* copy from pll_cpux_clk */\n> +\t.enable\t= BIT(31),\n> +\t.lock\t= BIT(28),\n> +};\n> +\n> +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n> +\t.common\t\t= &cpux_clk.common,\n> +\t.cm\t\t= &cpux_clk.mux,\n> +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n> +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n> +};\n> +\n>\n> static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n> {\n> \tstruct resource *res;\n> \tvoid __iomem *reg;\n> \tu32 val;\n> +\tint ret;\n> \n> \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> \treg = devm_ioremap_resource(&pdev->dev, res);\n> @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n> \n> \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n> \n> -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n> +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\t/* Gate then ungate PLL CPU after any rate changes */\n> +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n> +\n> +\t/* Reparent CPU during PLL CPU rate changes */\n> +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n> +\t\t\t\t &sun50i_a64_cpu_nb);\n> +\n> +\treturn 0;\n\nSo this is the fourth user of the exact same code, can you turn that\ninto a shared function?\n\nThanks!\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"b1bRmDTn\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2rWW0PDhz9tXj\n\tfor ;\n\tThu, 28 Sep 2017 20:28:34 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxW3S-0001Lf-8L; Thu, 28 Sep 2017 10:28:30 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxW3N-00019V-VG for linux-arm-kernel@lists.infradead.org;\n\tThu, 28 Sep 2017 10:28:28 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 6856E207ED; Thu, 28 Sep 2017 12:28:02 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 3D42A207A1;\n\tThu, 28 Sep 2017 12:27:52 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=VVMHRzIjp6tkVXCFC1qr0tmSnXKKyTz/UF30CqcsFBs=;\n\tb=b1bRmDTnobC+BzENI9OXOiDMD\n\t/BF6V8dXJjcqigiOOPZ/1fvK1JVXpwhGahNwUp/1YPXTJZbI15xkOLAfsPhebWXFcAdX3NxmntFJb\n\tGW27BsXJ9442B/N5nfvJB2IFUPAAZb7wtLbKk028nFozQ/fHWn5+WWG7J7mRlvgT2tQKA09tVkxPf\n\t26A107ixKFEMAeSIFBj06IhFoYHpaOLAPMwueeKmsCYkI9HdDEJCk9E2OJFPfKh2+7NptHabiwOOv\n\tfALKff1ES0/rJSo9GZUb/7bkFN7yuQBe9kXd4DiUibulR/ZfEt458g7IL7Y0xEVXXzBR2InMX3Lvr\n\t7yC9/3hHQ==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 28 Sep 2017 12:27:52 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","Message-ID":"<20170928102752.ceo54qccqakb4xyx@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<20170923001531.14285-2-icenowy@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170928_032826_322487_D28B99C3 ","X-CRM114-Status":"GOOD ( 16.17 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"multipart/mixed;\n\tboundary=\"===============1329491736692212418==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776941,"web_url":"http://patchwork.ozlabs.org/comment/1776941/","msgid":"<20170928102830.uuicirbjb5q64vwz@flea>","list_archive_url":null,"date":"2017-09-28T10:28:30","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi,\n\nOn Wed, Sep 27, 2017 at 11:51:30AM +0000, icenowy@aosc.io wrote:\n> 在 2017-09-25 18:27，Maxime Ripard 写道：\n> > On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n> > > 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard\n> > > 写到:\n> > > >Hi,\n> > > >\n> > > >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n> > > >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n> > > >>\n> > > >> As the thermal sensor driver is not yet implemented and some boards\n> > > >> have still no AXP PMIC support, now only two OPPs are present --\n> > > >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n> > > >>\n> > > >> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n> > > >> set up the device tree bits of the DVFS on Pine64.\n> > > >\n> > > >How has this been tested?\n> > > >\n> > > >What tasks did you run, with what governor, etc...\n> > > \n> > > I only tested manual frequency switching between 648MHz and\n> > > 816MHz, and tested the PLL stuck issue by change the OPPs to\n> > > some random value.\n> > \n> > Ideally, we should test that it's actually reliable. Poorly chosen\n> > OPPs might lead to corrupt data that you might not get before a while.\n> > \n> > Please test using:\n> > https://linux-sunxi.org/Hardware_Reliability_Tests#Reliability_of_cpufreq_voltage.2Ffrequency_settings\n> > \n> > And post the report.\n> \n> ```\n> root@p64 [ cpuburn-arm@master ] # ./cpuburn-a53 &\n> [1] 2543\n> root@p64 [ cpuburn-arm@master ] # ./cpufreq-ljt-stress-test\n> Creating './whitenoise-1920x1080.jpg' ... done\n> CPU stress test, which is doing JPEG decoding by libjpeg-turbo\n> at different cpufreq operating points.\n> \n> Testing CPU 0\n> 816 MHz ............................................................ OK\n> 648 MHz ............................................................ OK\n> \n> Testing CPU 1\n> 816 MHz ............................................................ OK\n> 648 MHz ............................................................ OK\n> \n> Testing CPU 2\n> 816 MHz ............................................................ OK\n> 648 MHz ............................................................ OK\n> \n> Testing CPU 3\n> 816 MHz ............................................................ OK\n> 648 MHz ............................................................ OK\n> \n> Overall result : PASSED\n> ```\n\nGreat, thanks!\n\nCan you put that in your cover letter for the next version?\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"OYJ9qvud\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2rX65cb5z9tXj\n\tfor ;\n\tThu, 28 Sep 2017 20:29:10 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxW42-0001w2-I1; Thu, 28 Sep 2017 10:29:06 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxW3x-0001Xn-UQ for linux-arm-kernel@lists.infradead.org;\n\tThu, 28 Sep 2017 10:29:04 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid ECB77207EE; Thu, 28 Sep 2017 12:28:39 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id BCDD2207ED;\n\tThu, 28 Sep 2017 12:28:29 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=TdceN0tNXbtngQo4pd1taz5Q+9jLFIOG3NmmNbIJeGI=;\n\tb=OYJ9qvudmgoNUJVLWjcGNavic\n\tq7SnZzOt/o5CReXQdptmGZaaAm2oiEA/s0jxfaR1GSpNIC3NpGG2mN8ldW1fvESNhlnJFgAP1N3Ee\n\tZckzj8ifsMHGPbZbj1wHfrRVNIaRjwjdW7IbM8gPaOgnyTiuadhB4WVKPUWmU+bNXnSxDdHXsHLPo\n\tJ4zgz/bwtxygECpzjbbJW6TMROoJWYXCcvDc/7BG1OOcUM0/jUrbDIEFjaKNe6M8EWlR2MLG1N76y\n\t55euIxJgzJlnVUOtFqJxQFCAvq4bVLNST9Yl0e40jrERsJETrvxf/Vwsu4SvqxQxIrKfL5DlUwzR9\n\tiRbIgcM7Q==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 28 Sep 2017 12:28:30 +0200","From":"Maxime Ripard ","To":"icenowy@aosc.io","Subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","Message-ID":"<20170928102830.uuicirbjb5q64vwz@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>\n\t<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>\n\t<20170925102744.qixfwlheeimemhcf@flea.home>\n\t<9b3aeb6cb155bb2f9a7cee438de82ccb@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<9b3aeb6cb155bb2f9a7cee438de82ccb@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170928_032902_412177_BF18E2EE ","X-CRM114-Status":"GOOD ( 19.65 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"multipart/mixed;\n\tboundary=\"===============2993054201490127056==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776951,"web_url":"http://patchwork.ozlabs.org/comment/1776951/","msgid":"<975c0c884d9a83faad6141df474a93af@aosc.io>","list_archive_url":null,"date":"2017-09-28T10:42:39","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"在 2017-09-28 18:27，Maxime Ripard 写道：\n> Hi,\n> \n> On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n>> The A64 PLL_CPU clock has the same instability if some factor changed\n>> without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n>> H3.\n>> \n>> Add the mux and pll notifiers for A64 CPU clock to workaround the\n>> problem.\n>> \n>> Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n>> Signed-off-by: Icenowy Zheng \n>> ---\n>> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28 \n>> +++++++++++++++++++++++++++-\n>> 1 file changed, 27 insertions(+), 1 deletion(-)\n>> \n>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c \n>> b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> index 2bb4cabf802f..b55fa69dd0c1 100644\n>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc \n>> sun50i_a64_ccu_desc = {\n>> \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n>> };\n>> \n>> +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n>> +\t.common\t= &pll_cpux_clk.common,\n>> +\t/* copy from pll_cpux_clk */\n>> +\t.enable\t= BIT(31),\n>> +\t.lock\t= BIT(28),\n>> +};\n>> +\n>> +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n>> +\t.common\t\t= &cpux_clk.common,\n>> +\t.cm\t\t= &cpux_clk.mux,\n>> +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n>> +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n>> +};\n>> +\n>> \n>> static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n>> {\n>> \tstruct resource *res;\n>> \tvoid __iomem *reg;\n>> \tu32 val;\n>> +\tint ret;\n>> \n>> \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n>> \treg = devm_ioremap_resource(&pdev->dev, res);\n>> @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct \n>> platform_device *pdev)\n>> \n>> \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n>> \n>> -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg, \n>> &sun50i_a64_ccu_desc);\n>> +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n>> +\tif (ret)\n>> +\t\treturn ret;\n>> +\n>> +\t/* Gate then ungate PLL CPU after any rate changes */\n>> +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n>> +\n>> +\t/* Reparent CPU during PLL CPU rate changes */\n>> +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n>> +\t\t\t\t &sun50i_a64_cpu_nb);\n>> +\n>> +\treturn 0;\n> \n> So this is the fourth user of the exact same code, can you turn that\n> into a shared function?\n\nI think it's not so worthful to extract the code, as:\n- the notifier structs contains info of the clocks\n- A31 seems not to need the PLL notifier.\n\n> \n> Thanks!\n> Maxime\n> \n> _______________________________________________\n> linux-arm-kernel mailing list\n> linux-arm-kernel@lists.infradead.org\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"hRKmPk+f\"; dkim-atps=neutral"],"Received":["from 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28 Sep 2017 18:42:39 +0800","From":"icenowy@aosc.io","To":"Maxime Ripard ","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","In-Reply-To":"<20170928102752.ceo54qccqakb4xyx@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>\n\t<20170928102752.ceo54qccqakb4xyx@flea>","Message-ID":"<975c0c884d9a83faad6141df474a93af@aosc.io>","X-Sender":"icenowy@aosc.io","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170928_034310_851565_49FF54FF ","X-CRM114-Status":"GOOD ( 13.22 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777054,"web_url":"http://patchwork.ozlabs.org/comment/1777054/","msgid":"<20170928142050.gkbdqlwpfjmpdlg3@flea>","list_archive_url":null,"date":"2017-09-28T14:20:50","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote:\n> > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n> > > The A64 PLL_CPU clock has the same instability if some factor changed\n> > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n> > > H3.\n> > > \n> > > Add the mux and pll notifiers for A64 CPU clock to workaround the\n> > > problem.\n> > > \n> > > Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n> > > Signed-off-by: Icenowy Zheng \n> > > ---\n> > > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28\n> > > +++++++++++++++++++++++++++-\n> > > 1 file changed, 27 insertions(+), 1 deletion(-)\n> > > \n> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > index 2bb4cabf802f..b55fa69dd0c1 100644\n> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc\n> > > sun50i_a64_ccu_desc = {\n> > > \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n> > > };\n> > > \n> > > +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n> > > +\t.common\t= &pll_cpux_clk.common,\n> > > +\t/* copy from pll_cpux_clk */\n> > > +\t.enable\t= BIT(31),\n> > > +\t.lock\t= BIT(28),\n> > > +};\n> > > +\n> > > +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n> > > +\t.common\t\t= &cpux_clk.common,\n> > > +\t.cm\t\t= &cpux_clk.mux,\n> > > +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n> > > +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n> > > +};\n> > > +\n> > > \n> > > static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n> > > {\n> > > \tstruct resource *res;\n> > > \tvoid __iomem *reg;\n> > > \tu32 val;\n> > > +\tint ret;\n> > > \n> > > \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> > > \treg = devm_ioremap_resource(&pdev->dev, res);\n> > > @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct\n> > > platform_device *pdev)\n> > > \n> > > \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n> > > \n> > > -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg,\n> > > &sun50i_a64_ccu_desc);\n> > > +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n> > > +\tif (ret)\n> > > +\t\treturn ret;\n> > > +\n> > > +\t/* Gate then ungate PLL CPU after any rate changes */\n> > > +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n> > > +\n> > > +\t/* Reparent CPU during PLL CPU rate changes */\n> > > +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n> > > +\t\t\t\t &sun50i_a64_cpu_nb);\n> > > +\n> > > +\treturn 0;\n> > \n> > So this is the fourth user of the exact same code, can you turn that\n> > into a shared function?\n> \n> I think it's not so worthful to extract the code, as:\n\nIt does, because the order is important. If you do not register the\nnotifiers in the right order, you have a bug, and:\n\n> - the notifier structs contains info of the clocks\n\nthis should be passed as a parameter anyway,\n\n> - A31 seems not to need the PLL notifier.\n\nAnd you don't care about the ordering in that case, since there's just\none. If was talking about the H3, A64, R40 and A33 that all have that\ncode.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"EsHMspe9\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2xhD1ZKWz9t5x\n\tfor ;\n\tFri, 29 Sep 2017 00:21:32 +1000 (AEST)","from localhost ([127.0.0.1] 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version=3.4.0","Date":"Thu, 28 Sep 2017 16:20:50 +0200","From":"Maxime Ripard ","To":"icenowy@aosc.io","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","Message-ID":"<20170928142050.gkbdqlwpfjmpdlg3@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>\n\t<20170928102752.ceo54qccqakb4xyx@flea>\n\t<975c0c884d9a83faad6141df474a93af@aosc.io>","MIME-Version":"1.0","In-Reply-To":"<975c0c884d9a83faad6141df474a93af@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170928_072125_128702_8BEF56F8 ","X-CRM114-Status":"GOOD ( 21.77 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"multipart/mixed;\n\tboundary=\"===============1878236466568317905==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777063,"web_url":"http://patchwork.ozlabs.org/comment/1777063/","msgid":"","list_archive_url":null,"date":"2017-09-28T14:24:18","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"在 2017-09-28 22:20，Maxime Ripard 写道：\n> On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote:\n>> > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n>> > > The A64 PLL_CPU clock has the same instability if some factor changed\n>> > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n>> > > H3.\n>> > >\n>> > > Add the mux and pll notifiers for A64 CPU clock to workaround the\n>> > > problem.\n>> > >\n>> > > Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n>> > > Signed-off-by: Icenowy Zheng \n>> > > ---\n>> > > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28\n>> > > +++++++++++++++++++++++++++-\n>> > > 1 file changed, 27 insertions(+), 1 deletion(-)\n>> > >\n>> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> > > index 2bb4cabf802f..b55fa69dd0c1 100644\n>> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> > > @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc\n>> > > sun50i_a64_ccu_desc = {\n>> > > \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n>> > > };\n>> > >\n>> > > +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n>> > > +\t.common\t= &pll_cpux_clk.common,\n>> > > +\t/* copy from pll_cpux_clk */\n>> > > +\t.enable\t= BIT(31),\n>> > > +\t.lock\t= BIT(28),\n>> > > +};\n>> > > +\n>> > > +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n>> > > +\t.common\t\t= &cpux_clk.common,\n>> > > +\t.cm\t\t= &cpux_clk.mux,\n>> > > +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n>> > > +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n>> > > +};\n>> > > +\n>> > >\n>> > > static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n>> > > {\n>> > > \tstruct resource *res;\n>> > > \tvoid __iomem *reg;\n>> > > \tu32 val;\n>> > > +\tint ret;\n>> > >\n>> > > \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n>> > > \treg = devm_ioremap_resource(&pdev->dev, res);\n>> > > @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct\n>> > > platform_device *pdev)\n>> > >\n>> > > \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n>> > >\n>> > > -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg,\n>> > > &sun50i_a64_ccu_desc);\n>> > > +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n>> > > +\tif (ret)\n>> > > +\t\treturn ret;\n>> > > +\n>> > > +\t/* Gate then ungate PLL CPU after any rate changes */\n>> > > +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n>> > > +\n>> > > +\t/* Reparent CPU during PLL CPU rate changes */\n>> > > +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n>> > > +\t\t\t\t &sun50i_a64_cpu_nb);\n>> > > +\n>> > > +\treturn 0;\n>> >\n>> > So this is the fourth user of the exact same code, can you turn that\n>> > into a shared function?\n>> \n>> I think it's not so worthful to extract the code, as:\n> \n> It does, because the order is important. If you do not register the\n> notifiers in the right order, you have a bug, and:\n> \n>> - the notifier structs contains info of the clocks\n> \n> this should be passed as a parameter anyway,\n\nSo the function only does these two registers?\n\n> \n>> - A31 seems not to need the PLL notifier.\n> \n> And you don't care about the ordering in that case, since there's just\n> one. If was talking about the H3, A64, R40 and A33 that all have that\n> code.\n> \n> Maxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"MQBCEkY2\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2xmB1Xdlz9t66\n\tfor ;\n\tFri, 29 Sep 2017 00:24:58 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxZkF-0003Uu-2H; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From:\n\tDate:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=CroKYVwrxqUDPI/7q5ClV0lBQJCFpH5hHWs6NhFYdds=;\n\tb=MQBCEkY2xuPjdASACchCGCoG3\n\t8AP8/OZsaaiCvycfuummoVVPqG6ego4TjertV6s894RL2vhy9CvrIMflV5YeWexytXwqH2FW9PJmk\n\tOjwHSZOllx5j0S0UX/PTNmwv+IQ+I4WQRCtXwz8qKH22+c890AhxbweKMdbgZeZKr6oBLNeuhLQES\n\tEFIPQmMM6Cut27Cen/C5kfmnl2hggVPQYRQA3ZPKC0EBbecxLxM5F+cbsFMfBFS9OdvkwlTpbcFnl\n\tf/NfVh0ZGzqBTmGRKb2b2XcpIA64Ek7DlNRVZczf7S5Kc3iFHmdzQCOUHn78ezUHqC+vV+YSKf9n0\n\t01tR3OabQ==;","X-Sender-Id":["lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io","lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io"],"X-MC-Relay":"Neutral","X-MailChannels-SenderId":"lmn-tzduiowcrqmw|x-authsender|icenowy@aosc.io","X-MailChannels-Auth-Id":"lmn-TZDUIOWCRQMW","X-Arch-Interest":"7af1c8ef3483b9c6_1506608661025_1840859880","X-MC-Loop-Signature":"1506608661025:628149738","X-MC-Ingress-Time":"1506608661025","MIME-Version":"1.0","Date":"Thu, 28 Sep 2017 22:24:18 +0800","From":"icenowy@aosc.io","To":"Maxime Ripard ","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","In-Reply-To":"<20170928142050.gkbdqlwpfjmpdlg3@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>\n\t<20170928102752.ceo54qccqakb4xyx@flea>\n\t<975c0c884d9a83faad6141df474a93af@aosc.io>\n\t<20170928142050.gkbdqlwpfjmpdlg3@flea>","Message-ID":"","X-Sender":"icenowy@aosc.io","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170928_072451_286105_55BC6915 ","X-CRM114-Status":"GOOD ( 18.21 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [46.232.183.96 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[46.232.183.96 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777067,"web_url":"http://patchwork.ozlabs.org/comment/1777067/","msgid":"<20170928143142.f6wtekvkia3bvoq2@flea>","list_archive_url":null,"date":"2017-09-28T14:31:42","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 28, 2017 at 02:24:18PM +0000, icenowy@aosc.io wrote:\n> 在 2017-09-28 22:20，Maxime Ripard 写道：\n> > On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote:\n> > > > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n> > > > > The A64 PLL_CPU clock has the same instability if some factor changed\n> > > > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n> > > > > H3.\n> > > > >\n> > > > > Add the mux and pll notifiers for A64 CPU clock to workaround the\n> > > > > problem.\n> > > > >\n> > > > > Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n> > > > > Signed-off-by: Icenowy Zheng \n> > > > > ---\n> > > > > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28\n> > > > > +++++++++++++++++++++++++++-\n> > > > > 1 file changed, 27 insertions(+), 1 deletion(-)\n> > > > >\n> > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > > > index 2bb4cabf802f..b55fa69dd0c1 100644\n> > > > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > > > @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc\n> > > > > sun50i_a64_ccu_desc = {\n> > > > > \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n> > > > > };\n> > > > >\n> > > > > +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n> > > > > +\t.common\t= &pll_cpux_clk.common,\n> > > > > +\t/* copy from pll_cpux_clk */\n> > > > > +\t.enable\t= BIT(31),\n> > > > > +\t.lock\t= BIT(28),\n> > > > > +};\n> > > > > +\n> > > > > +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n> > > > > +\t.common\t\t= &cpux_clk.common,\n> > > > > +\t.cm\t\t= &cpux_clk.mux,\n> > > > > +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n> > > > > +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n> > > > > +};\n> > > > > +\n> > > > >\n> > > > > static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n> > > > > {\n> > > > > \tstruct resource *res;\n> > > > > \tvoid __iomem *reg;\n> > > > > \tu32 val;\n> > > > > +\tint ret;\n> > > > >\n> > > > > \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> > > > > \treg = devm_ioremap_resource(&pdev->dev, res);\n> > > > > @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct\n> > > > > platform_device *pdev)\n> > > > >\n> > > > > \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n> > > > >\n> > > > > -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg,\n> > > > > &sun50i_a64_ccu_desc);\n> > > > > +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n> > > > > +\tif (ret)\n> > > > > +\t\treturn ret;\n> > > > > +\n> > > > > +\t/* Gate then ungate PLL CPU after any rate changes */\n> > > > > +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n> > > > > +\n> > > > > +\t/* Reparent CPU during PLL CPU rate changes */\n> > > > > +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n> > > > > +\t\t\t\t &sun50i_a64_cpu_nb);\n> > > > > +\n> > > > > +\treturn 0;\n> > > >\n> > > > So this is the fourth user of the exact same code, can you turn that\n> > > > into a shared function?\n> > > \n> > > I think it's not so worthful to extract the code, as:\n> > \n> > It does, because the order is important. If you do not register the\n> > notifiers in the right order, you have a bug, and:\n> > \n> > > - the notifier structs contains info of the clocks\n> > \n> > this should be passed as a parameter anyway,\n> \n> So the function only does these two registers?\n\nYes.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"rgAvpOKa\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2xwc36XCz9t5x\n\tfor ;\n\tFri, 29 Sep 2017 00:32:16 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxZrJ-00084g-5W; Thu, 28 Sep 2017 14:32:13 +0000","from mail.free-electrons.com ([62.4.15.54])\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxZrA-00082v-D9 for linux-arm-kernel@lists.infradead.org;\n\tThu, 28 Sep 2017 14:32:11 +0000","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 9E9502091A; Thu, 28 Sep 2017 16:31:41 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 7040E207FD;\n\tThu, 28 Sep 2017 16:31:41 +0200 (CEST)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:Cc:\n\tList-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:\n\tIn-Reply-To:MIME-Version:References:Message-ID:Subject:To:From:Date:Reply-To:\n\tContent-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=7olHN1liI0Zqck7Fcx11pjG4+8a99GyRG6NS85ID+cw=;\n\tb=rgAvpOKa0WCEj0zn4Rw3ABDRt\n\tZ/bcnw1zdTZP8gbggdA9T28c72t25tZTFPflFIokLqPd1gjtvxzxZjkqi0GIh5Cb3ktnppVsKCmaF\n\t6c/A97Y1uPUGOyw4oK4aqpnYm6SI0ZIVrVqE6FfnZjHd6tZQ/RNMADZPdb+kkjjbEpoiRxw8GVbPt\n\tjzkazBJSdoSk3MPIj3vqCPO4bs2J6CVpPj4PjLq4M8B2UPGIpUu+xcW83Tu3jEznHK93OegXNSDJS\n\tEwCYbzKqH7I+ekHn4H/nCwQEwppx2Jwo7Uf/OEfsbjgaAG9MTkkaJD1udG/A2eFT2edm9UluFQ4Pe\n\tSXmuQiLsw==;","X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 28 Sep 2017 16:31:42 +0200","From":"Maxime Ripard ","To":"icenowy@aosc.io","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","Message-ID":"<20170928143142.f6wtekvkia3bvoq2@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>\n\t<20170928102752.ceo54qccqakb4xyx@flea>\n\t<975c0c884d9a83faad6141df474a93af@aosc.io>\n\t<20170928142050.gkbdqlwpfjmpdlg3@flea>\n\t","MIME-Version":"1.0","In-Reply-To":"","User-Agent":"NeoMutt/20170914 (1.9.0)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170928_073204_756968_3B197F54 ","X-CRM114-Status":"GOOD ( 23.50 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Content-Type":"multipart/mixed;\n\tboundary=\"===============8641592128764454460==\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}}]