[{"id":1774611,"web_url":"http://patchwork.ozlabs.org/comment/1774611/","msgid":"<20170925101027.lghnnll4h6inreqm@flea.home>","list_archive_url":null,"date":"2017-09-25T10:10:27","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi,\n\nOn Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n> This patchset imports simple DVFS support for Allwinner A64 SoC.\n> \n> As the thermal sensor driver is not yet implemented and some boards\n> have still no AXP PMIC support, now only two OPPs are present --\n> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n> \n> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n> set up the device tree bits of the DVFS on Pine64.\n\nHow has this been tested?\n\nWhat tasks did you run, with what governor, etc...\n\nThanks!\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y10GD4CX0z9tX3\n\tfor ;\n\tMon, 25 Sep 2017 20:10:44 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932395AbdIYKKm (ORCPT );\n\tMon, 25 Sep 2017 06:10:42 -0400","from mail.free-electrons.com ([62.4.15.54]:38536 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753856AbdIYKKk (ORCPT\n\t); Mon, 25 Sep 2017 06:10:40 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 8064720A01; Mon, 25 Sep 2017 12:10:38 +0200 (CEST)","from localhost (unknown [109.190.253.16])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 2B77D209F6;\n\tMon, 25 Sep 2017 12:10:27 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 25 Sep 2017 12:10:27 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Cc":"Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","Message-ID":"<20170925101027.lghnnll4h6inreqm@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"cljd2fqx4wv57lmc\"","Content-Disposition":"inline","In-Reply-To":"<20170923001531.14285-1-icenowy@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774622,"web_url":"http://patchwork.ozlabs.org/comment/1774622/","msgid":"<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>","list_archive_url":null,"date":"2017-09-25T10:12:09","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard 写到:\n>Hi,\n>\n>On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n>> This patchset imports simple DVFS support for Allwinner A64 SoC.\n>> \n>> As the thermal sensor driver is not yet implemented and some boards\n>> have still no AXP PMIC support, now only two OPPs are present --\n>> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n>> \n>> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n>> set up the device tree bits of the DVFS on Pine64.\n>\n>How has this been tested?\n>\n>What tasks did you run, with what governor, etc...\n\nI only tested manual frequency switching between 648MHz and\n816MHz, and tested the PLL stuck issue by change the OPPs to\nsome random value.\n\n>\n>Thanks!\n>Maxime\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y10JV3VLVz9tX3\n\tfor ;\n\tMon, 25 Sep 2017 20:12:42 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S934290AbdIYKM1 convert rfc822-to-8bit (ORCPT\n\t);\n\tMon, 25 Sep 2017 06:12:27 -0400","from hermes.aosc.io ([199.195.250.187]:53476 \"EHLO hermes.aosc.io\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S933052AbdIYKM0 (ORCPT );\n\tMon, 25 Sep 2017 06:12:26 -0400","from localhost (localhost [127.0.0.1]) (Authenticated sender:\n\ticenowy@aosc.io)\n\tby hermes.aosc.io (Postfix) with ESMTPSA id 03D8544CC1;\n\tMon, 25 Sep 2017 10:12:20 +0000 (UTC)"],"Date":"Mon, 25 Sep 2017 18:12:09 +0800","In-Reply-To":"<20170925101027.lghnnll4h6inreqm@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>","MIME-Version":"1.0","Content-Type":"text/plain;\n charset=utf-8","Content-Transfer-Encoding":"8BIT","Subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","To":"Maxime Ripard ","CC":"Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-sunxi@googlegroups.com","From":"Icenowy Zheng ","Message-ID":"<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774631,"web_url":"http://patchwork.ozlabs.org/comment/1774631/","msgid":"<20170925102744.qixfwlheeimemhcf@flea.home>","list_archive_url":null,"date":"2017-09-25T10:27:44","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard 写到:\n> >Hi,\n> >\n> >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n> >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n> >> \n> >> As the thermal sensor driver is not yet implemented and some boards\n> >> have still no AXP PMIC support, now only two OPPs are present --\n> >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n> >> \n> >> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n> >> set up the device tree bits of the DVFS on Pine64.\n> >\n> >How has this been tested?\n> >\n> >What tasks did you run, with what governor, etc...\n> \n> I only tested manual frequency switching between 648MHz and\n> 816MHz, and tested the PLL stuck issue by change the OPPs to\n> some random value.\n\nIdeally, we should test that it's actually reliable. Poorly chosen\nOPPs might lead to corrupt data that you might not get before a while.\n\nPlease test using:\nhttps://linux-sunxi.org/Hardware_Reliability_Tests#Reliability_of_cpufreq_voltage.2Ffrequency_settings\n\nAnd post the report.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y10f8088qz9tX3\n\tfor ;\n\tMon, 25 Sep 2017 20:27:59 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S933358AbdIYK16 (ORCPT );\n\tMon, 25 Sep 2017 06:27:58 -0400","from mail.free-electrons.com ([62.4.15.54]:39283 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S932716AbdIYK15 (ORCPT\n\t); Mon, 25 Sep 2017 06:27:57 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 2D273209E3; Mon, 25 Sep 2017 12:27:55 +0200 (CEST)","from localhost (unknown [109.190.253.16])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id B4709208BF;\n\tMon, 25 Sep 2017 12:27:44 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 25 Sep 2017 12:27:44 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Cc":"Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","Message-ID":"<20170925102744.qixfwlheeimemhcf@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>\n\t<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"nxscyzcqnjj4fs3l\"","Content-Disposition":"inline","In-Reply-To":"<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774634,"web_url":"http://patchwork.ozlabs.org/comment/1774634/","msgid":"<1C624335-37C2-4F22-BE78-A94F26D1D248@aosc.io>","list_archive_url":null,"date":"2017-09-25T10:29:38","subject":"Re: [linux-sunxi] Re: [PATCH 0/3] Simple DVFS support for Allwinner\n\tA64 SoC","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard 写到:\n>On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n>> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard\n> 写到:\n>> >Hi,\n>> >\n>> >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n>> >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n>> >> \n>> >> As the thermal sensor driver is not yet implemented and some\n>boards\n>> >> have still no AXP PMIC support, now only two OPPs are present --\n>> >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n>> >> \n>> >> PATCH 1 is a fix to the CCU driver of A64, and the remaining\n>patches\n>> >> set up the device tree bits of the DVFS on Pine64.\n>> >\n>> >How has this been tested?\n>> >\n>> >What tasks did you run, with what governor, etc...\n>> \n>> I only tested manual frequency switching between 648MHz and\n>> 816MHz, and tested the PLL stuck issue by change the OPPs to\n>> some random value.\n>\n>Ideally, we should test that it's actually reliable. Poorly chosen\n>OPPs might lead to corrupt data that you might not get before a while.\n\nThese are OPPs from the official sys_config.fex .\n\n>\n>Please test using:\n>https://linux-sunxi.org/Hardware_Reliability_Tests#Reliability_of_cpufreq_voltage.2Ffrequency_settings\n>\n>And post the report.\n>\n>Maxime\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y10l74yJfz9tXD\n\tfor ;\n\tMon, 25 Sep 2017 20:32:19 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S934294AbdIYKcS convert rfc822-to-8bit (ORCPT\n\t);\n\tMon, 25 Sep 2017 06:32:18 -0400","from hermes.aosc.io ([199.195.250.187]:54122 \"EHLO hermes.aosc.io\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S933128AbdIYKcR (ORCPT );\n\tMon, 25 Sep 2017 06:32:17 -0400","from localhost (localhost [127.0.0.1]) (Authenticated sender:\n\ticenowy@aosc.io)\n\tby hermes.aosc.io (Postfix) with ESMTPSA id 07C4A48157;\n\tMon, 25 Sep 2017 10:31:09 +0000 (UTC)"],"Date":"Mon, 25 Sep 2017 18:29:38 +0800","In-Reply-To":"<20170925102744.qixfwlheeimemhcf@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>\n\t<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>\n\t<20170925102744.qixfwlheeimemhcf@flea.home>","MIME-Version":"1.0","Content-Type":"text/plain;\n charset=utf-8","Content-Transfer-Encoding":"8BIT","Subject":"Re: [linux-sunxi] Re: [PATCH 0/3] Simple DVFS support for Allwinner\n\tA64 SoC","To":"maxime.ripard@free-electrons.com,\n\tMaxime Ripard ","CC":"Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-sunxi@googlegroups.com","From":"Icenowy Zheng ","Message-ID":"<1C624335-37C2-4F22-BE78-A94F26D1D248@aosc.io>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774640,"web_url":"http://patchwork.ozlabs.org/comment/1774640/","msgid":"<20170925104328.jttvrdbptor5zhsr@flea.home>","list_archive_url":null,"date":"2017-09-25T10:43:28","subject":"Re: [linux-sunxi] Re: [PATCH 0/3] Simple DVFS support for Allwinner\n\tA64 SoC","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Mon, Sep 25, 2017 at 10:29:38AM +0000, Icenowy Zheng wrote:\n> \n> \n> 于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard 写到:\n> >On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n> >> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard\n> > 写到:\n> >> >Hi,\n> >> >\n> >> >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n> >> >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n> >> >> \n> >> >> As the thermal sensor driver is not yet implemented and some\n> >boards\n> >> >> have still no AXP PMIC support, now only two OPPs are present --\n> >> >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n> >> >> \n> >> >> PATCH 1 is a fix to the CCU driver of A64, and the remaining\n> >patches\n> >> >> set up the device tree bits of the DVFS on Pine64.\n> >> >\n> >> >How has this been tested?\n> >> >\n> >> >What tasks did you run, with what governor, etc...\n> >> \n> >> I only tested manual frequency switching between 648MHz and\n> >> 816MHz, and tested the PLL stuck issue by change the OPPs to\n> >> some random value.\n> >\n> >Ideally, we should test that it's actually reliable. Poorly chosen\n> >OPPs might lead to corrupt data that you might not get before a while.\n> \n> These are OPPs from the official sys_config.fex .\n\nAnd the rest of the code isn't, such as the clock or regulator code\nthat is critical as well here.\n\nI'm not asking this out of nowhere, we've had to debug this more than\nonce already.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y110H2xXlz9sNr\n\tfor ;\n\tMon, 25 Sep 2017 20:43:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S934558AbdIYKnl (ORCPT );\n\tMon, 25 Sep 2017 06:43:41 -0400","from mail.free-electrons.com ([62.4.15.54]:39818 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S934211AbdIYKnk (ORCPT\n\t); Mon, 25 Sep 2017 06:43:40 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid A6F1F20866; Mon, 25 Sep 2017 12:43:38 +0200 (CEST)","from localhost (unknown [109.190.253.16])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 1C3F420813;\n\tMon, 25 Sep 2017 12:43:28 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Mon, 25 Sep 2017 12:43:28 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Cc":"Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [linux-sunxi] Re: [PATCH 0/3] Simple DVFS support for Allwinner\n\tA64 SoC","Message-ID":"<20170925104328.jttvrdbptor5zhsr@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>\n\t<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>\n\t<20170925102744.qixfwlheeimemhcf@flea.home>\n\t<1C624335-37C2-4F22-BE78-A94F26D1D248@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"ennmauk36dyn7l5y\"","Content-Disposition":"inline","In-Reply-To":"<1C624335-37C2-4F22-BE78-A94F26D1D248@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1774884,"web_url":"http://patchwork.ozlabs.org/comment/1774884/","msgid":"<4e9af757-0881-cd79-2693-6b979db78ddb@sholland.org>","list_archive_url":null,"date":"2017-09-25T17:38:47","subject":"Re: [linux-sunxi] [PATCH 2/3] arm64: allwinner: a64: add CPU opp\n\ttable","submitter":{"id":72437,"url":"http://patchwork.ozlabs.org/api/people/72437/","name":"Samuel Holland","email":"samuel@sholland.org"},"content":"Hello,\n\nOn 09/22/17 19:15, Icenowy Zheng wrote:\n> Add the operating table for the CPU (ARM cores) on Allwinner A64 SoC.\n> \n> OPPs higher to 816MHz is temporarily dropped, to prevent overheat on\n> boards with AXP803 support and undervoltage on boards without AXP803\n> support.\n> \n> Signed-off-by: Icenowy Zheng \n> ---\n> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++\n> 1 file changed, 24 insertions(+)\n> \n> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi\n> index 20aba7b186aa..0532da4939eb 100644\n> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi\n> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi\n> @@ -52,6 +52,23 @@\n> \t#address-cells = <1>;\n> \t#size-cells = <1>;\n> \n> +\tcpu0_opp_table: opp_table0 {\n> +\t\tcompatible = \"operating-points-v2\";\n> +\t\topp-shared;\n> +\n> +\t\topp-648000000 {\n> +\t\t\topp-hz = /bits/ 64 <648000000>;\n> +\t\t\topp-microvolt = <1040000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\n> +\t\topp-816000000 {\n> +\t\t\topp-hz = /bits/ 64 <816000000>;\n> +\t\t\topp-microvolt = <1100000>;\n> +\t\t\tclock-latency-ns = <244144>; /* 8 32k periods */\n> +\t\t};\n> +\t};\n> +\n> \tcpus {\n> \t\t#address-cells = <1>;\n> \t\t#size-cells = <0>;\n> @@ -61,6 +78,10 @@\n> \t\t\tdevice_type = \"cpu\";\n> \t\t\treg = <0>;\n> \t\t\tenable-method = \"psci\";\n> +\t\t\tclocks = <&ccu CLK_CPUX>;\nCLK_CPUX is not currently exposed in the dt-bindings header, so this\ndoesn't compile.\n\n> +\t\t\tclock-names = \"cpu\";\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> +\t\t\t#cooling-cells = <2>;\n> \t\t};\n> \n> \t\tcpu1: cpu@1 {\n> @@ -68,6 +89,7 @@\n> \t\t\tdevice_type = \"cpu\";\n> \t\t\treg = <1>;\n> \t\t\tenable-method = \"psci\";\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> \t\t};\n> \n> \t\tcpu2: cpu@2 {\n> @@ -75,6 +97,7 @@\n> \t\t\tdevice_type = \"cpu\";\n> \t\t\treg = <2>;\n> \t\t\tenable-method = \"psci\";\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> \t\t};\n> \n> \t\tcpu3: cpu@3 {\n> @@ -82,6 +105,7 @@\n> \t\t\tdevice_type = \"cpu\";\n> \t\t\treg = <3>;\n> \t\t\tenable-method = \"psci\";\n> +\t\t\toperating-points-v2 = <&cpu0_opp_table>;\n> \t\t};\n> \t};\n> \n> \n\nThanks,\nSamuel\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=sholland.org header.i=@sholland.org\n\theader.b=\"Llq8HM55\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=messagingengine.com\n\theader.i=@messagingengine.com\n\theader.b=\"ZNVO9jF9\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1BCW0tTFz9t6N\n\tfor ;\n\tTue, 26 Sep 2017 03:39:03 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S936235AbdIYRiw (ORCPT );\n\tMon, 25 Sep 2017 13:38:52 -0400","from out1-smtp.messagingengine.com ([66.111.4.25]:37771 \"EHLO\n\tout1-smtp.messagingengine.com\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S934132AbdIYRiv (ORCPT\n\t); Mon, 25 Sep 2017 13:38:51 -0400","from compute5.internal (compute5.nyi.internal [10.202.2.45])\n\tby mailout.nyi.internal (Postfix) with ESMTP id 4AAE5216C4;\n\tMon, 25 Sep 2017 13:38:50 -0400 (EDT)","from frontend1 ([10.202.2.160])\n\tby compute5.internal (MEProxy); Mon, 25 Sep 2017 13:38:50 -0400","from [192.168.4.128] (unknown [99.198.199.144])\n\tby mail.messagingengine.com (Postfix) with ESMTPA id 648BD7FA87;\n\tMon, 25 Sep 2017 13:38:49 -0400 (EDT)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h=\n\tcc:content-transfer-encoding:content-type:date:from:in-reply-to\n\t:message-id:mime-version:references:subject:to:x-me-sender\n\t:x-me-sender:x-sasl-enc:x-sasl-enc; s=fm1; bh=X8SQaOOPwsxJQoWxIE\n\tMimLaDaDpTy/NFFjaUWDNhj2A=; b=Llq8HM552Ts0Nj0qzdRZLLrm6hPN7iLI2D\n\tEpdSuJVXWHB9lBcfAGdAA/XgPAlCfjRTU5yoCC3Lg8qFpXHhesk3x5nSk8wtC35W\n\tdySCyxF0PNioT86MSetrOEP1qRptn0DpS8W7en7Uo6fS3a8EqNb/bK6IJtgePGiX\n\t7O3G3FK7d4MlwCKFqt43MF9aTq4QFFxVYQS1dF+PvVgcoRh8ZFu9mC6kAfOt2rg1\n\thX7XYggTyqSU7RZHY2k5n6A/yQaqH//zCcfQLF5/tEocyf19KuwH6s+qzRTDR/Nw\n\tqxmAeiQRJkoJCxAvnrIJcsWBGwyoSCY3A+kh1Sz0KvRsUEMBZMlQ==","v=1; a=rsa-sha256; c=relaxed/relaxed; d=\n\tmessagingengine.com; h=cc:content-transfer-encoding:content-type\n\t:date:from:in-reply-to:message-id:mime-version:references\n\t:subject:to:x-me-sender:x-me-sender:x-sasl-enc:x-sasl-enc; s=\n\tfm1; bh=X8SQaOOPwsxJQoWxIEMimLaDaDpTy/NFFjaUWDNhj2A=; b=ZNVO9jF9\n\tun2/tf2w93caOOhp+YyoCEngKr4G6RRwEOJ9J/Svk0p+roQyWRCnL6HcTa0B+cCQ\n\tb3Dh+i0pwn0ECSjw+RwM1dH4eEjNrG9uTwGn69myx3pVD7hMFz2pj7m6OVkC1/3r\n\tBKqOPAOkr1+lYY4SwCUZFF6EDwfJwpjhHHwK37ts/QqO7lN+d8CO/KhXEZI2jMxa\n\tMg9phcKrowPWvX/wEJXP/s7q6Fgq5SZTaaQ83e4aajAHwhFAXEJBqZNQ9fVdtBxF\n\tVwk17W5YERFYEKpuqNhixj1Ge/RTwUcvEZg1Mbf5qFovcbiZtj65js7leBqzoJfd\n\tSHeNWvJSeP8gTQ=="],"X-ME-Sender":"","X-Sasl-enc":"RE0Ou2rXf+J2EQ6dYnCMmOif6CGFjpQ7TGiWIsxnXLlQ 1506361129","Subject":"Re: [linux-sunxi] [PATCH 2/3] arm64: allwinner: a64: add CPU opp\n\ttable","To":"icenowy@aosc.io, Maxime Ripard ,\n\tChen-Yu Tsai ","Cc":"linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-sunxi@googlegroups.com","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-3-icenowy@aosc.io>","From":"Samuel Holland ","Message-ID":"<4e9af757-0881-cd79-2693-6b979db78ddb@sholland.org>","Date":"Mon, 25 Sep 2017 12:38:47 -0500","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.0","MIME-Version":"1.0","In-Reply-To":"<20170923001531.14285-3-icenowy@aosc.io>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776275,"web_url":"http://patchwork.ozlabs.org/comment/1776275/","msgid":"<9b3aeb6cb155bb2f9a7cee438de82ccb@aosc.io>","list_archive_url":null,"date":"2017-09-27T11:51:30","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"在 2017-09-25 18:27，Maxime Ripard 写道：\n> On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n>> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard \n>> 写到:\n>> >Hi,\n>> >\n>> >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n>> >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n>> >>\n>> >> As the thermal sensor driver is not yet implemented and some boards\n>> >> have still no AXP PMIC support, now only two OPPs are present --\n>> >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n>> >>\n>> >> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n>> >> set up the device tree bits of the DVFS on Pine64.\n>> >\n>> >How has this been tested?\n>> >\n>> >What tasks did you run, with what governor, etc...\n>> \n>> I only tested manual frequency switching between 648MHz and\n>> 816MHz, and tested the PLL stuck issue by change the OPPs to\n>> some random value.\n> \n> Ideally, we should test that it's actually reliable. Poorly chosen\n> OPPs might lead to corrupt data that you might not get before a while.\n> \n> Please test using:\n> https://linux-sunxi.org/Hardware_Reliability_Tests#Reliability_of_cpufreq_voltage.2Ffrequency_settings\n> \n> And post the report.\n\n```\nroot@p64 [ cpuburn-arm@master ] # ./cpuburn-a53 &\n[1] 2543\nroot@p64 [ cpuburn-arm@master ] # ./cpufreq-ljt-stress-test\nCreating './whitenoise-1920x1080.jpg' ... done\nCPU stress test, which is doing JPEG decoding by libjpeg-turbo\nat different cpufreq operating points.\n\nTesting CPU 0\n 816 MHz ............................................................ \nOK\n 648 MHz ............................................................ \nOK\n\nTesting CPU 1\n 816 MHz ............................................................ \nOK\n 648 MHz ............................................................ \nOK\n\nTesting CPU 2\n 816 MHz ............................................................ \nOK\n 648 MHz ............................................................ \nOK\n\nTesting CPU 3\n 816 MHz ............................................................ \nOK\n 648 MHz ............................................................ \nOK\n\nOverall result : PASSED\n```\n\n> \n> Maxime\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2GPg6Rvhz9s7c\n\tfor ;\n\tWed, 27 Sep 2017 21:51:35 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752088AbdI0Lve (ORCPT\n\t);\n\tWed, 27 Sep 2017 07:51:34 -0400","from hermes.aosc.io ([199.195.250.187]:45468 \"EHLO hermes.aosc.io\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751739AbdI0Lvd (ORCPT );\n\tWed, 27 Sep 2017 07:51:33 -0400","from localhost (localhost [127.0.0.1]) (Authenticated sender:\n\ticenowy@aosc.io)\n\tby hermes.aosc.io (Postfix) with ESMTPSA id 25C7E47F71;\n\tWed, 27 Sep 2017 11:51:30 +0000 (UTC)"],"MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8;\n format=flowed","Content-Transfer-Encoding":"8bit","Date":"Wed, 27 Sep 2017 19:51:30 +0800","From":"icenowy@aosc.io","To":"Maxime Ripard ","Cc":"Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","In-Reply-To":"<20170925102744.qixfwlheeimemhcf@flea.home>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>\n\t<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>\n\t<20170925102744.qixfwlheeimemhcf@flea.home>","Message-ID":"<9b3aeb6cb155bb2f9a7cee438de82ccb@aosc.io>","X-Sender":"icenowy@aosc.io","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776937,"web_url":"http://patchwork.ozlabs.org/comment/1776937/","msgid":"<20170928102752.ceo54qccqakb4xyx@flea>","list_archive_url":null,"date":"2017-09-28T10:27:52","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi,\n\nOn Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n> The A64 PLL_CPU clock has the same instability if some factor changed\n> without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n> H3.\n> \n> Add the mux and pll notifiers for A64 CPU clock to workaround the\n> problem.\n> \n> Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n> Signed-off-by: Icenowy Zheng \n> ---\n> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28 +++++++++++++++++++++++++++-\n> 1 file changed, 27 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> index 2bb4cabf802f..b55fa69dd0c1 100644\n> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc sun50i_a64_ccu_desc = {\n> \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n> };\n> \n> +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n> +\t.common\t= &pll_cpux_clk.common,\n> +\t/* copy from pll_cpux_clk */\n> +\t.enable\t= BIT(31),\n> +\t.lock\t= BIT(28),\n> +};\n> +\n> +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n> +\t.common\t\t= &cpux_clk.common,\n> +\t.cm\t\t= &cpux_clk.mux,\n> +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n> +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n> +};\n> +\n>\n> static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n> {\n> \tstruct resource *res;\n> \tvoid __iomem *reg;\n> \tu32 val;\n> +\tint ret;\n> \n> \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> \treg = devm_ioremap_resource(&pdev->dev, res);\n> @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n> \n> \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n> \n> -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n> +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\t/* Gate then ungate PLL CPU after any rate changes */\n> +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n> +\n> +\t/* Reparent CPU during PLL CPU rate changes */\n> +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n> +\t\t\t\t &sun50i_a64_cpu_nb);\n> +\n> +\treturn 0;\n\nSo this is the fourth user of the exact same code, can you turn that\ninto a shared function?\n\nThanks!\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2rVv4fF2z9tXd\n\tfor ;\n\tThu, 28 Sep 2017 20:28:07 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751883AbdI1K2F (ORCPT\n\t);\n\tThu, 28 Sep 2017 06:28:05 -0400","from mail.free-electrons.com ([62.4.15.54]:39853 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751082AbdI1K2F (ORCPT\n\t); Thu, 28 Sep 2017 06:28:05 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 6856E207ED; Thu, 28 Sep 2017 12:28:02 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 3D42A207A1;\n\tThu, 28 Sep 2017 12:27:52 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 28 Sep 2017 12:27:52 +0200","From":"Maxime Ripard ","To":"Icenowy Zheng ","Cc":"Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","Message-ID":"<20170928102752.ceo54qccqakb4xyx@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"fyb5mloqkdqrtwkq\"","Content-Disposition":"inline","In-Reply-To":"<20170923001531.14285-2-icenowy@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776939,"web_url":"http://patchwork.ozlabs.org/comment/1776939/","msgid":"<20170928102830.uuicirbjb5q64vwz@flea>","list_archive_url":null,"date":"2017-09-28T10:28:30","subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"Hi,\n\nOn Wed, Sep 27, 2017 at 11:51:30AM +0000, icenowy@aosc.io wrote:\n> 在 2017-09-25 18:27，Maxime Ripard 写道：\n> > On Mon, Sep 25, 2017 at 10:12:09AM +0000, Icenowy Zheng wrote:\n> > > 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard\n> > > 写到:\n> > > >Hi,\n> > > >\n> > > >On Sat, Sep 23, 2017 at 12:15:28AM +0000, Icenowy Zheng wrote:\n> > > >> This patchset imports simple DVFS support for Allwinner A64 SoC.\n> > > >>\n> > > >> As the thermal sensor driver is not yet implemented and some boards\n> > > >> have still no AXP PMIC support, now only two OPPs are present --\n> > > >> 648MHz@1.04V and 816MHz@1.1V to prevent overheat or undervoltage.\n> > > >>\n> > > >> PATCH 1 is a fix to the CCU driver of A64, and the remaining patches\n> > > >> set up the device tree bits of the DVFS on Pine64.\n> > > >\n> > > >How has this been tested?\n> > > >\n> > > >What tasks did you run, with what governor, etc...\n> > > \n> > > I only tested manual frequency switching between 648MHz and\n> > > 816MHz, and tested the PLL stuck issue by change the OPPs to\n> > > some random value.\n> > \n> > Ideally, we should test that it's actually reliable. Poorly chosen\n> > OPPs might lead to corrupt data that you might not get before a while.\n> > \n> > Please test using:\n> > https://linux-sunxi.org/Hardware_Reliability_Tests#Reliability_of_cpufreq_voltage.2Ffrequency_settings\n> > \n> > And post the report.\n> \n> ```\n> root@p64 [ cpuburn-arm@master ] # ./cpuburn-a53 &\n> [1] 2543\n> root@p64 [ cpuburn-arm@master ] # ./cpufreq-ljt-stress-test\n> Creating './whitenoise-1920x1080.jpg' ... done\n> CPU stress test, which is doing JPEG decoding by libjpeg-turbo\n> at different cpufreq operating points.\n> \n> Testing CPU 0\n> 816 MHz ............................................................ OK\n> 648 MHz ............................................................ OK\n> \n> Testing CPU 1\n> 816 MHz ............................................................ OK\n> 648 MHz ............................................................ OK\n> \n> Testing CPU 2\n> 816 MHz ............................................................ OK\n> 648 MHz ............................................................ OK\n> \n> Testing CPU 3\n> 816 MHz ............................................................ OK\n> 648 MHz ............................................................ OK\n> \n> Overall result : PASSED\n> ```\n\nGreat, thanks!\n\nCan you put that in your cover letter for the next version?\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2rWc5m5Tz9tXj\n\tfor ;\n\tThu, 28 Sep 2017 20:28:44 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751880AbdI1K2n (ORCPT\n\t);\n\tThu, 28 Sep 2017 06:28:43 -0400","from mail.free-electrons.com ([62.4.15.54]:39877 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751129AbdI1K2m (ORCPT\n\t); Thu, 28 Sep 2017 06:28:42 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid ECB77207EE; Thu, 28 Sep 2017 12:28:39 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id BCDD2207ED;\n\tThu, 28 Sep 2017 12:28:29 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 28 Sep 2017 12:28:30 +0200","From":"Maxime Ripard ","To":"icenowy@aosc.io","Cc":"Chen-Yu Tsai , linux-arm-kernel@lists.infradead.org,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-sunxi@googlegroups.com","Subject":"Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC","Message-ID":"<20170928102830.uuicirbjb5q64vwz@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170925101027.lghnnll4h6inreqm@flea.home>\n\t<27EF78BD-6285-4D8D-AA65-8294D797E2FB@aosc.io>\n\t<20170925102744.qixfwlheeimemhcf@flea.home>\n\t<9b3aeb6cb155bb2f9a7cee438de82ccb@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"okv7m74fz5ndo6kz\"","Content-Disposition":"inline","In-Reply-To":"<9b3aeb6cb155bb2f9a7cee438de82ccb@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776950,"web_url":"http://patchwork.ozlabs.org/comment/1776950/","msgid":"<975c0c884d9a83faad6141df474a93af@aosc.io>","list_archive_url":null,"date":"2017-09-28T10:42:39","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"在 2017-09-28 18:27，Maxime Ripard 写道：\n> Hi,\n> \n> On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n>> The A64 PLL_CPU clock has the same instability if some factor changed\n>> without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n>> H3.\n>> \n>> Add the mux and pll notifiers for A64 CPU clock to workaround the\n>> problem.\n>> \n>> Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n>> Signed-off-by: Icenowy Zheng \n>> ---\n>> drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28 \n>> +++++++++++++++++++++++++++-\n>> 1 file changed, 27 insertions(+), 1 deletion(-)\n>> \n>> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c \n>> b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> index 2bb4cabf802f..b55fa69dd0c1 100644\n>> --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc \n>> sun50i_a64_ccu_desc = {\n>> \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n>> };\n>> \n>> +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n>> +\t.common\t= &pll_cpux_clk.common,\n>> +\t/* copy from pll_cpux_clk */\n>> +\t.enable\t= BIT(31),\n>> +\t.lock\t= BIT(28),\n>> +};\n>> +\n>> +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n>> +\t.common\t\t= &cpux_clk.common,\n>> +\t.cm\t\t= &cpux_clk.mux,\n>> +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n>> +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n>> +};\n>> +\n>> \n>> static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n>> {\n>> \tstruct resource *res;\n>> \tvoid __iomem *reg;\n>> \tu32 val;\n>> +\tint ret;\n>> \n>> \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n>> \treg = devm_ioremap_resource(&pdev->dev, res);\n>> @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct \n>> platform_device *pdev)\n>> \n>> \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n>> \n>> -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg, \n>> &sun50i_a64_ccu_desc);\n>> +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n>> +\tif (ret)\n>> +\t\treturn ret;\n>> +\n>> +\t/* Gate then ungate PLL CPU after any rate changes */\n>> +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n>> +\n>> +\t/* Reparent CPU during PLL CPU rate changes */\n>> +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n>> +\t\t\t\t &sun50i_a64_cpu_nb);\n>> +\n>> +\treturn 0;\n> \n> So this is the fourth user of the exact same code, can you turn that\n> into a shared function?\n\nI think it's not so worthful to extract the code, as:\n- the notifier structs contains info of the clocks\n- A31 seems not to need the PLL notifier.\n\n> \n> Thanks!\n> Maxime\n> \n> _______________________________________________\n> linux-arm-kernel mailing list\n> linux-arm-kernel@lists.infradead.org\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2rql4161z9t6K\n\tfor ;\n\tThu, 28 Sep 2017 20:42:43 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751895AbdI1Kmm (ORCPT\n\t);\n\tThu, 28 Sep 2017 06:42:42 -0400","from hermes.aosc.io ([199.195.250.187]:53072 \"EHLO hermes.aosc.io\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751082AbdI1Kml (ORCPT );\n\tThu, 28 Sep 2017 06:42:41 -0400","from localhost (localhost [127.0.0.1]) (Authenticated sender:\n\ticenowy@aosc.io)\n\tby hermes.aosc.io (Postfix) with ESMTPSA id 32BCE47BB2;\n\tThu, 28 Sep 2017 10:42:39 +0000 (UTC)"],"MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8;\n format=flowed","Content-Transfer-Encoding":"8bit","Date":"Thu, 28 Sep 2017 18:42:39 +0800","From":"icenowy@aosc.io","To":"Maxime Ripard ","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","In-Reply-To":"<20170928102752.ceo54qccqakb4xyx@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>\n\t<20170928102752.ceo54qccqakb4xyx@flea>","Message-ID":"<975c0c884d9a83faad6141df474a93af@aosc.io>","X-Sender":"icenowy@aosc.io","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1777053,"web_url":"http://patchwork.ozlabs.org/comment/1777053/","msgid":"<20170928142050.gkbdqlwpfjmpdlg3@flea>","list_archive_url":null,"date":"2017-09-28T14:20:50","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote:\n> > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n> > > The A64 PLL_CPU clock has the same instability if some factor changed\n> > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n> > > H3.\n> > > \n> > > Add the mux and pll notifiers for A64 CPU clock to workaround the\n> > > problem.\n> > > \n> > > Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n> > > Signed-off-by: Icenowy Zheng \n> > > ---\n> > > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28\n> > > +++++++++++++++++++++++++++-\n> > > 1 file changed, 27 insertions(+), 1 deletion(-)\n> > > \n> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > index 2bb4cabf802f..b55fa69dd0c1 100644\n> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc\n> > > sun50i_a64_ccu_desc = {\n> > > \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n> > > };\n> > > \n> > > +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n> > > +\t.common\t= &pll_cpux_clk.common,\n> > > +\t/* copy from pll_cpux_clk */\n> > > +\t.enable\t= BIT(31),\n> > > +\t.lock\t= BIT(28),\n> > > +};\n> > > +\n> > > +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n> > > +\t.common\t\t= &cpux_clk.common,\n> > > +\t.cm\t\t= &cpux_clk.mux,\n> > > +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n> > > +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n> > > +};\n> > > +\n> > > \n> > > static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n> > > {\n> > > \tstruct resource *res;\n> > > \tvoid __iomem *reg;\n> > > \tu32 val;\n> > > +\tint ret;\n> > > \n> > > \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> > > \treg = devm_ioremap_resource(&pdev->dev, res);\n> > > @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct\n> > > platform_device *pdev)\n> > > \n> > > \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n> > > \n> > > -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg,\n> > > &sun50i_a64_ccu_desc);\n> > > +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n> > > +\tif (ret)\n> > > +\t\treturn ret;\n> > > +\n> > > +\t/* Gate then ungate PLL CPU after any rate changes */\n> > > +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n> > > +\n> > > +\t/* Reparent CPU during PLL CPU rate changes */\n> > > +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n> > > +\t\t\t\t &sun50i_a64_cpu_nb);\n> > > +\n> > > +\treturn 0;\n> > \n> > So this is the fourth user of the exact same code, can you turn that\n> > into a shared function?\n> \n> I think it's not so worthful to extract the code, as:\n\nIt does, because the order is important. If you do not register the\nnotifiers in the right order, you have a bug, and:\n\n> - the notifier structs contains info of the clocks\n\nthis should be passed as a parameter anyway,\n\n> - A31 seems not to need the PLL notifier.\n\nAnd you don't care about the ordering in that case, since there's just\none. If was talking about the H3, A64, R40 and A33 that all have that\ncode.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2xgl2wltz9t66\n\tfor ;\n\tFri, 29 Sep 2017 00:21:07 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752017AbdI1OVF (ORCPT\n\t);\n\tThu, 28 Sep 2017 10:21:05 -0400","from mail.free-electrons.com ([62.4.15.54]:48022 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751953AbdI1OVE (ORCPT\n\t); Thu, 28 Sep 2017 10:21:04 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 1B929207D9; Thu, 28 Sep 2017 16:21:02 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id E75B1207BA;\n\tThu, 28 Sep 2017 16:20:51 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT\n\tshortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 28 Sep 2017 16:20:50 +0200","From":"Maxime Ripard ","To":"icenowy@aosc.io","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","Message-ID":"<20170928142050.gkbdqlwpfjmpdlg3@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>\n\t<20170928102752.ceo54qccqakb4xyx@flea>\n\t<975c0c884d9a83faad6141df474a93af@aosc.io>","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"ynwlkhxyx47lxmvj\"","Content-Disposition":"inline","In-Reply-To":"<975c0c884d9a83faad6141df474a93af@aosc.io>","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1777062,"web_url":"http://patchwork.ozlabs.org/comment/1777062/","msgid":"","list_archive_url":null,"date":"2017-09-28T14:24:18","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":71295,"url":"http://patchwork.ozlabs.org/api/people/71295/","name":"Icenowy Zheng","email":"icenowy@aosc.io"},"content":"在 2017-09-28 22:20，Maxime Ripard 写道：\n> On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote:\n>> > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n>> > > The A64 PLL_CPU clock has the same instability if some factor changed\n>> > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n>> > > H3.\n>> > >\n>> > > Add the mux and pll notifiers for A64 CPU clock to workaround the\n>> > > problem.\n>> > >\n>> > > Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n>> > > Signed-off-by: Icenowy Zheng \n>> > > ---\n>> > > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28\n>> > > +++++++++++++++++++++++++++-\n>> > > 1 file changed, 27 insertions(+), 1 deletion(-)\n>> > >\n>> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> > > index 2bb4cabf802f..b55fa69dd0c1 100644\n>> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n>> > > @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc\n>> > > sun50i_a64_ccu_desc = {\n>> > > \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n>> > > };\n>> > >\n>> > > +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n>> > > +\t.common\t= &pll_cpux_clk.common,\n>> > > +\t/* copy from pll_cpux_clk */\n>> > > +\t.enable\t= BIT(31),\n>> > > +\t.lock\t= BIT(28),\n>> > > +};\n>> > > +\n>> > > +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n>> > > +\t.common\t\t= &cpux_clk.common,\n>> > > +\t.cm\t\t= &cpux_clk.mux,\n>> > > +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n>> > > +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n>> > > +};\n>> > > +\n>> > >\n>> > > static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n>> > > {\n>> > > \tstruct resource *res;\n>> > > \tvoid __iomem *reg;\n>> > > \tu32 val;\n>> > > +\tint ret;\n>> > >\n>> > > \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n>> > > \treg = devm_ioremap_resource(&pdev->dev, res);\n>> > > @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct\n>> > > platform_device *pdev)\n>> > >\n>> > > \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n>> > >\n>> > > -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg,\n>> > > &sun50i_a64_ccu_desc);\n>> > > +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n>> > > +\tif (ret)\n>> > > +\t\treturn ret;\n>> > > +\n>> > > +\t/* Gate then ungate PLL CPU after any rate changes */\n>> > > +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n>> > > +\n>> > > +\t/* Reparent CPU during PLL CPU rate changes */\n>> > > +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n>> > > +\t\t\t\t &sun50i_a64_cpu_nb);\n>> > > +\n>> > > +\treturn 0;\n>> >\n>> > So this is the fourth user of the exact same code, can you turn that\n>> > into a shared function?\n>> \n>> I think it's not so worthful to extract the code, as:\n> \n> It does, because the order is important. If you do not register the\n> notifiers in the right order, you have a bug, and:\n> \n>> - the notifier structs contains info of the clocks\n> \n> this should be passed as a parameter anyway,\n\nSo the function only does these two registers?\n\n> \n>> - A31 seems not to need the PLL notifier.\n> \n> And you don't care about the ordering in that case, since there's just\n> one. If was talking about the H3, A64, R40 and A33 that all have that\n> code.\n> \n> Maxime\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2xlW0NGRz9t3C\n\tfor ;\n\tFri, 29 Sep 2017 00:24:23 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752555AbdI1OYV (ORCPT\n\t);\n\tThu, 28 Sep 2017 10:24:21 -0400","from hermes.aosc.io ([199.195.250.187]:59737 \"EHLO hermes.aosc.io\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752357AbdI1OYU (ORCPT );\n\tThu, 28 Sep 2017 10:24:20 -0400","from localhost (localhost [127.0.0.1]) (Authenticated sender:\n\ticenowy@aosc.io)\n\tby hermes.aosc.io (Postfix) with ESMTPSA id E3EF7486EF;\n\tThu, 28 Sep 2017 14:24:18 +0000 (UTC)"],"MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8;\n format=flowed","Content-Transfer-Encoding":"8bit","Date":"Thu, 28 Sep 2017 22:24:18 +0800","From":"icenowy@aosc.io","To":"Maxime Ripard ","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","In-Reply-To":"<20170928142050.gkbdqlwpfjmpdlg3@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>\n\t<20170928102752.ceo54qccqakb4xyx@flea>\n\t<975c0c884d9a83faad6141df474a93af@aosc.io>\n\t<20170928142050.gkbdqlwpfjmpdlg3@flea>","Message-ID":"","X-Sender":"icenowy@aosc.io","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1777066,"web_url":"http://patchwork.ozlabs.org/comment/1777066/","msgid":"<20170928143142.f6wtekvkia3bvoq2@flea>","list_archive_url":null,"date":"2017-09-28T14:31:42","subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","submitter":{"id":12916,"url":"http://patchwork.ozlabs.org/api/people/12916/","name":"Maxime Ripard","email":"maxime.ripard@free-electrons.com"},"content":"On Thu, Sep 28, 2017 at 02:24:18PM +0000, icenowy@aosc.io wrote:\n> 在 2017-09-28 22:20，Maxime Ripard 写道：\n> > On Thu, Sep 28, 2017 at 10:42:39AM +0000, icenowy@aosc.io wrote:\n> > > > On Sat, Sep 23, 2017 at 12:15:29AM +0000, Icenowy Zheng wrote:\n> > > > > The A64 PLL_CPU clock has the same instability if some factor changed\n> > > > > without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33,\n> > > > > H3.\n> > > > >\n> > > > > Add the mux and pll notifiers for A64 CPU clock to workaround the\n> > > > > problem.\n> > > > >\n> > > > > Fixes: c6a0637460c2 (\"clk: sunxi-ng: Add A64 clocks\")\n> > > > > Signed-off-by: Icenowy Zheng \n> > > > > ---\n> > > > > drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 28\n> > > > > +++++++++++++++++++++++++++-\n> > > > > 1 file changed, 27 insertions(+), 1 deletion(-)\n> > > > >\n> > > > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > > > b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > > > index 2bb4cabf802f..b55fa69dd0c1 100644\n> > > > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c\n> > > > > @@ -879,11 +879,26 @@ static const struct sunxi_ccu_desc\n> > > > > sun50i_a64_ccu_desc = {\n> > > > > \t.num_resets\t= ARRAY_SIZE(sun50i_a64_ccu_resets),\n> > > > > };\n> > > > >\n> > > > > +static struct ccu_pll_nb sun50i_a64_pll_cpu_nb = {\n> > > > > +\t.common\t= &pll_cpux_clk.common,\n> > > > > +\t/* copy from pll_cpux_clk */\n> > > > > +\t.enable\t= BIT(31),\n> > > > > +\t.lock\t= BIT(28),\n> > > > > +};\n> > > > > +\n> > > > > +static struct ccu_mux_nb sun50i_a64_cpu_nb = {\n> > > > > +\t.common\t\t= &cpux_clk.common,\n> > > > > +\t.cm\t\t= &cpux_clk.mux,\n> > > > > +\t.delay_us\t= 1, /* > 8 clock cycles at 24 MHz */\n> > > > > +\t.bypass_index\t= 1, /* index of 24 MHz oscillator */\n> > > > > +};\n> > > > > +\n> > > > >\n> > > > > static int sun50i_a64_ccu_probe(struct platform_device *pdev)\n> > > > > {\n> > > > > \tstruct resource *res;\n> > > > > \tvoid __iomem *reg;\n> > > > > \tu32 val;\n> > > > > +\tint ret;\n> > > > >\n> > > > > \tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> > > > > \treg = devm_ioremap_resource(&pdev->dev, res);\n> > > > > @@ -897,7 +912,18 @@ static int sun50i_a64_ccu_probe(struct\n> > > > > platform_device *pdev)\n> > > > >\n> > > > > \twritel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);\n> > > > >\n> > > > > -\treturn sunxi_ccu_probe(pdev->dev.of_node, reg,\n> > > > > &sun50i_a64_ccu_desc);\n> > > > > +\tret = sunxi_ccu_probe(pdev->dev.of_node, reg, &sun50i_a64_ccu_desc);\n> > > > > +\tif (ret)\n> > > > > +\t\treturn ret;\n> > > > > +\n> > > > > +\t/* Gate then ungate PLL CPU after any rate changes */\n> > > > > +\tccu_pll_notifier_register(&sun50i_a64_pll_cpu_nb);\n> > > > > +\n> > > > > +\t/* Reparent CPU during PLL CPU rate changes */\n> > > > > +\tccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,\n> > > > > +\t\t\t\t &sun50i_a64_cpu_nb);\n> > > > > +\n> > > > > +\treturn 0;\n> > > >\n> > > > So this is the fourth user of the exact same code, can you turn that\n> > > > into a shared function?\n> > > \n> > > I think it's not so worthful to extract the code, as:\n> > \n> > It does, because the order is important. If you do not register the\n> > notifiers in the right order, you have a bug, and:\n> > \n> > > - the notifier structs contains info of the clocks\n> > \n> > this should be passed as a parameter anyway,\n> \n> So the function only does these two registers?\n\nYes.\n\nMaxime","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2xw22LPJz9t5x\n\tfor ;\n\tFri, 29 Sep 2017 00:31:46 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753138AbdI1Obo (ORCPT\n\t);\n\tThu, 28 Sep 2017 10:31:44 -0400","from mail.free-electrons.com ([62.4.15.54]:48450 \"EHLO\n\tmail.free-electrons.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752484AbdI1Obo (ORCPT\n\t); Thu, 28 Sep 2017 10:31:44 -0400","by mail.free-electrons.com (Postfix, from userid 110)\n\tid 9E9502091A; Thu, 28 Sep 2017 16:31:41 +0200 (CEST)","from localhost (unknown [195.81.232.10])\n\tby mail.free-electrons.com (Postfix) with ESMTPSA id 7040E207FD;\n\tThu, 28 Sep 2017 16:31:41 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tmail.free-electrons.com","X-Spam-Level":"","X-Spam-Status":"No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT,\n\tURIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0","Date":"Thu, 28 Sep 2017 16:31:42 +0200","From":"Maxime Ripard ","To":"icenowy@aosc.io","Cc":"devicetree@vger.kernel.org, linux-sunxi@googlegroups.com,\n\tlinux-kernel@vger.kernel.org, Chen-Yu Tsai ,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org","Subject":"Re: [PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU\n\tclock","Message-ID":"<20170928143142.f6wtekvkia3bvoq2@flea>","References":"<20170923001531.14285-1-icenowy@aosc.io>\n\t<20170923001531.14285-2-icenowy@aosc.io>\n\t<20170928102752.ceo54qccqakb4xyx@flea>\n\t<975c0c884d9a83faad6141df474a93af@aosc.io>\n\t<20170928142050.gkbdqlwpfjmpdlg3@flea>\n\t","MIME-Version":"1.0","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\"; boundary=\"7hlrtk67smbc4grp\"","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"NeoMutt/20170914 (1.9.0)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]