[{"id":1784906,"web_url":"http://patchwork.ozlabs.org/comment/1784906/","msgid":"<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-10-11T19:37:37","subject":"Re: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Fri, Sep 22, 2017 at 03:25:21PM +0800, Zhiqiang Hou wrote:\n> From: Hou Zhiqiang \n> \n> The Freescale PCIe controller advertises the MSI/MSI-X capability\n> in both RC and Endpoint mode, but in RC mode it doesn't support\n> MSI/MSI-X by it self, it can only transfer MSI/MSI-X from downstream\n\ns/it self,/itself;/\n\n> devices. So add this quirk to prevent use of MSI/MSI-X in RC mode.\n> \n> Signed-off-by: Hou Zhiqiang \n> ---\n> drivers/pci/quirks.c | 8 ++++++++\n> 1 file changed, 8 insertions(+)\n> \n> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c\n> index a4d33619a7bb..c1063a420f0c 100644\n> --- a/drivers/pci/quirks.c\n> +++ b/drivers/pci/quirks.c\n> @@ -4799,3 +4799,11 @@ static void quirk_no_ats(struct pci_dev *pdev)\n> /* AMD Stoney platform GPU */\n> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);\n> #endif /* CONFIG_PCI_ATS */\n> +\n> +/* Freescale PCIe doesn't support MSI in RC mode */\n> +static void quirk_fsl_no_msi(struct pci_dev *pdev)\n> +{\n> +\tif (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)\n> +\t\tpdev->no_msi = 1;\n> +}\n> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);\n\nThis disables MSI for all Freescale root ports, past, present, and\nfuture. Is that really what you want? This is a bug (the root port\nshouldn't advertise MSI if it doesn't support it), and presumably it\nmight be fixed in some future device?\n\nThis needs an ack from Minghuan or Mingkai (based on MAINTAINERS).\n\nBjorn","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"nm/CUPUN\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yC45h4Tdvz9t2V\n\tfor ;\n\tThu, 12 Oct 2017 06:38:09 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2MpP-0003ed-PS; Wed, 11 Oct 2017 19:38:03 +0000","from mail.kernel.org ([198.145.29.99])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2MpM-0003Xw-AU for linux-arm-kernel@lists.infradead.org;\n\tWed, 11 Oct 2017 19:38:01 +0000","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 3C34D21483;\n\tWed, 11 Oct 2017 19:37:39 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=55dIOhplc/qzlcFJsKy0nE8RWfkk1VWHfIbrIZRmlEs=;\n\tb=nm/CUPUNKUrxpF\n\tihn92l2sCy2+fjc+jAG9jVW1JlJiHv/96MHEK0BvFc5jwojQpRAc0t0Sf/zWM/4Ns6OoY/t5R3V0E\n\ta0Tm+ROOm7wTOxTBgLAYD5PIwDaHaZUY3lbgJKv+c1XCKG3KU8SjtHGrtncB/lfHkbiZ1pwVG5ocT\n\tQv4urUqAs9JrNPsDuEt6W/Li6NgiPJV4zzOv03MIL8VzPn7haVngbw+jCwGdbuL3IfP01rjce0kgJ\n\ty7PD4LMIGd8vcp/86lVPSTEzEjCU/e9WD/5K8ndLG66IsEq5jmO30RsGl/nnhGwyI3zEDYCHIvi5S\n\tT23XZZxqgIKET5K1U77Q==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 3C34D21483","Date":"Wed, 11 Oct 2017 14:37:37 -0500","From":"Bjorn Helgaas ","To":"Zhiqiang Hou ","Subject":"Re: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Message-ID":"<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>\n\t<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171011_123800_412138_5DE9642F ","X-CRM114-Status":"GOOD ( 13.62 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [198.145.29.99 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"roy.zang@nxp.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tminghuan.lian@nxp.com, linux-arm-kernel@lists.infradead.org,\n\tbhelgaas@google.com, mingkai.hu@nxp.com","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1784909,"web_url":"http://patchwork.ozlabs.org/comment/1784909/","msgid":"<20171011194129.GQ25517@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-10-11T19:41:29","subject":"Re: [PATCH 2/2] pci/layerscape: change the default error response\n\tbehavior","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"On Fri, Sep 22, 2017 at 03:25:22PM +0800, Zhiqiang Hou wrote:\n> From: Minghuan Lian \n> \n> By default, when the PCIe controller experiences an erroneous\n> completion from an external completer for its outbound non-posted\n> request, it always sends an OKAY response to the device's internal\n> AXI slave system interface. However, such default system error\n> response behavior cannot be used for other types of outbound\n> non-posted requests. For example, the outbound memory read\n> transaction requires an actual ERROR response, like UR completion\n> or completion timeout. The patch is to fix it by forwarding\n> the error response of the non-posted request.\n> \n> Signed-off-by: Minghuan Lian \n> Signed-off-by: Hou Zhiqiang \n> ---\n> drivers/pci/dwc/pci-layerscape.c | 25 +++++++++++++++++++++++++\n> 1 file changed, 25 insertions(+)\n> \n> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c\n> index 3b01e309a55e..a647090c140e 100644\n> --- a/drivers/pci/dwc/pci-layerscape.c\n> +++ b/drivers/pci/dwc/pci-layerscape.c\n> @@ -33,6 +33,8 @@\n> \n> /* PEX Internal Configuration Registers */\n> #define PCIE_STRFMR1\t\t0x71c /* Symbol Timer & Filter Mask Register1 */\n> +#define PCIE_ABSERR\t\t0x8d0 /* Bridge Slave Error Response Register */\n> +#define PCIE_ABSERR_SETTING\t0x9401 /* Forward error of non-posted request */\n> \n> #define PCIE_IATU_NUM\t\t6\n> \n> @@ -54,6 +56,19 @@ struct ls_pcie {\n> \n> #define to_ls_pcie(x)\tdev_get_drvdata((x)->dev)\n> \n> +static int err_response_flag = 1;\n> +\n> +static int __init ls_pcie_param(char *p)\n> +{\n> +\tif (p && strncmp(p, \"no-err-response\", 15) == 0)\n> +\t\terr_response_flag = 0;\n> +\telse\n> +\t\terr_response_flag = 1;\n> +\n> +\treturn 0;\n> +}\n> +early_param(\"ls_pcie\", ls_pcie_param);\n\nWhat's the point of this parameter? If it's for debugging, it's not\nclear that we need it upstream. If it's for debugging and we *do*\nneed it upstream, there should be some sort of comment to that effect.\n\nI assume you never expect an end user to need this parameter.\n\n> static bool ls_pcie_is_bridge(struct ls_pcie *pcie)\n> {\n> \tstruct dw_pcie *pci = pcie->pci;\n> @@ -124,6 +139,14 @@ static int ls_pcie_link_up(struct dw_pcie *pci)\n> \treturn 1;\n> }\n> \n> +/* Forward error response of outbound non-posted requests */\n> +static void ls_pcie_fix_error_response(struct ls_pcie *pcie)\n> +{\n> +\tstruct dw_pcie *pci = pcie->pci;\n> +\n> +\tiowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);\n> +}\n> +\n> static int ls_pcie_host_init(struct pcie_port *pp)\n> {\n> \tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp);\n> @@ -135,6 +158,8 @@ static int ls_pcie_host_init(struct pcie_port *pp)\n> \t * dw_pcie_setup_rc() will reconfigure the outbound windows.\n> \t */\n> \tls_pcie_disable_outbound_atus(pcie);\n> +\tif (err_response_flag)\n> +\t\tls_pcie_fix_error_response(pcie);\n> \n> \tdw_pcie_dbi_ro_wr_en(pci);\n> \tls_pcie_clear_multifunction(pcie);\n> -- \n> 2.14.1\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"M/jkbtb0\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yC4B56gnHz9t2V\n\tfor ;\n\tThu, 12 Oct 2017 06:42:02 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2Mt9-0006H2-BP; Wed, 11 Oct 2017 19:41:55 +0000","from mail.kernel.org ([198.145.29.99])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2Mt5-00068M-PZ for linux-arm-kernel@lists.infradead.org;\n\tWed, 11 Oct 2017 19:41:53 +0000","from localhost (unknown [69.71.4.159])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 0077D21902;\n\tWed, 11 Oct 2017 19:41:30 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=RMAUemoBaUxVYNVPL2x+7rgA863XfvAwu56O3uMXX9s=;\n\tb=M/jkbtb0SUV4wd\n\tw71G0IqRFqpAWReYdNle8BK10bD1hyWKdBBPz7WWU8fiBR3GGJHHRF8bfYh/VdbWLI5xtmGVIQ1zi\n\tNezhMtWs9+NtbTArYCnr9SZojtm3BxOFqa9QO1gt9+ugN/qX0ouW+kdmD0aSnsKsxCbXVn/Z8CLGZ\n\tW1tYPRW2iRlubzUjTYEfMWKLK/6hMLNNR8znLqa+mu1fnfBeBtc5QLXePyEk/NTnKgd7t+mTNK7pS\n\tv8hazCHZeUglD6fA5ukBxggyKP9tpI/zZJUoAakVlrPETTP4ZIfQyTzF/zfm8cp7p0oKpBr2S3trI\n\tFg7Hu6VIYe6KvBUxnmkQ==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 0077D21902","Date":"Wed, 11 Oct 2017 14:41:29 -0500","From":"Bjorn Helgaas ","To":"Zhiqiang Hou ","Subject":"Re: [PATCH 2/2] pci/layerscape: change the default error response\n\tbehavior","Message-ID":"<20171011194129.GQ25517@bhelgaas-glaptop.roam.corp.google.com>","References":"<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>\n\t<20170922072522.36306-3-Zhiqiang.Hou@nxp.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170922072522.36306-3-Zhiqiang.Hou@nxp.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171011_124151_939643_418283A4 ","X-CRM114-Status":"GOOD ( 19.50 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [198.145.29.99 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"roy.zang@nxp.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tminghuan.lian@nxp.com, linux-arm-kernel@lists.infradead.org,\n\tbhelgaas@google.com, mingkai.hu@nxp.com","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1785109,"web_url":"http://patchwork.ozlabs.org/comment/1785109/","msgid":"","list_archive_url":null,"date":"2017-10-12T03:01:19","subject":"RE: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","submitter":{"id":68016,"url":"http://patchwork.ozlabs.org/api/people/68016/","name":"M.h. Lian","email":"Minghuan.Lian@nxp.com"},"content":"Hi Bjorn,\n\nThanks for your review.\nYes. All the freescale's PCIe controllers do not support to generate MSI interrupt.\nThe PCIe controllers developed for the next generation SoC do not support it either.\n\nAcked-by: Minghuan Lian \n\n> -----Original Message-----\n> From: Bjorn Helgaas [mailto:helgaas@kernel.org]\n> Sent: Thursday, October 12, 2017 3:38 AM\n> To: Z.q. Hou \n> Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-\n> pci@vger.kernel.org; bhelgaas@google.com; Roy Zang ;\n> Mingkai Hu ; M.h. Lian \n> Subject: Re: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode\n> \n> On Fri, Sep 22, 2017 at 03:25:21PM +0800, Zhiqiang Hou wrote:\n> > From: Hou Zhiqiang \n> >\n> > The Freescale PCIe controller advertises the MSI/MSI-X capability in\n> > both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X\n> > by it self, it can only transfer MSI/MSI-X from downstream\n> \n> s/it self,/itself;/\n> \n> > devices. So add this quirk to prevent use of MSI/MSI-X in RC mode.\n> >\n> > Signed-off-by: Hou Zhiqiang \n> > ---\n> > drivers/pci/quirks.c | 8 ++++++++\n> > 1 file changed, 8 insertions(+)\n> >\n> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index\n> > a4d33619a7bb..c1063a420f0c 100644\n> > --- a/drivers/pci/quirks.c\n> > +++ b/drivers/pci/quirks.c\n> > @@ -4799,3 +4799,11 @@ static void quirk_no_ats(struct pci_dev *pdev)\n> > /* AMD Stoney platform GPU */\n> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);\n> > #endif /* CONFIG_PCI_ATS */\n> > +\n> > +/* Freescale PCIe doesn't support MSI in RC mode */ static void\n> > +quirk_fsl_no_msi(struct pci_dev *pdev) {\n> > +\tif (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)\n> > +\t\tpdev->no_msi = 1;\n> > +}\n> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,\n> > +quirk_fsl_no_msi);\n> \n> This disables MSI for all Freescale root ports, past, present, and future. Is that\n> really what you want? This is a bug (the root port shouldn't advertise MSI if it\n> doesn't support it), and presumably it might be fixed in some future device?\n> \n> This needs an ack from Minghuan or Mingkai (based on MAINTAINERS).\n> \n> Bjorn","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"IMf8fcOp\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"wAAwLce0\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=minghuan.lian@nxp.com; "],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yCFxX5SNHz9sBd\n\tfor ;\n\tThu, 12 Oct 2017 14:01:52 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2Tkr-0004Q9-5R; Thu, 12 Oct 2017 03:01:49 +0000","from mail-eopbgr10060.outbound.protection.outlook.com\n\t([40.107.1.60] helo=EUR02-HE1-obe.outbound.protection.outlook.com)\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2Tkm-0004B5-Ch for linux-arm-kernel@lists.infradead.org;\n\tThu, 12 Oct 2017 03:01:46 +0000","from VI1PR04MB1615.eurprd04.prod.outlook.com (10.164.84.149) by\n\tVI1PR04MB3088.eurprd04.prod.outlook.com (10.170.229.10) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Thu, 12 Oct 2017 03:01:20 +0000","from VI1PR04MB1615.eurprd04.prod.outlook.com\n\t([fe80::a974:309e:c04:2ec7]) by\n\tVI1PR04MB1615.eurprd04.prod.outlook.com\n\t([fe80::a974:309e:c04:2ec7%13]) with mapi id 15.20.0077.020;\n\tThu, 12 Oct 2017 03:01:19 +0000"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=FC/dgT3rpz88A8Wt9MeN+jOXWxopwxI/C3kmNR/X6BY=;\n\tb=IMf8fcOpYFnxB4\n\tLqV2gUlQvHNTg1xQSmlhMwevYOU2K02bdCjyJ7CXzgads/RQuFsfBUkY1zrhvae/G86zJOLEgPbFL\n\tmY3Qu3gpGpgxmaNvSsMoTtSSgTHsr0qE6OrzCdNkgcMA0Ui48lYZ3Lr0A9NfweODDjua0wtt0HUWK\n\tg3NoVvKuGI7zBmylVTKf08ea9LcB1MEqlIFZNV5st9H5iWfv2YK9XkEUwF36E7g29jaZYRakEo3KH\n\tKWkwRnZD+DIwPZifa8Svs5mFgv4DmSZpDYDVkVPx0KLGPXsAFw3eNwDtmAmLbhSSGNH7gYQGIvZI4\n\tZosNj2gQ3EkJHZjkVNGA==;","v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=kCfiuY/fnEZ7uconod5CXkMK2RszxyL9fda+2XNXeFM=;\n\tb=wAAwLce05K044jGO3gEL6Q6fKpxwpTJLvUPPdaj1eSn9QBibCpkuGQBCxHUUa0307564jQi9Jy3pKC0pbCiLShG1fGtHdLjgXLKazhAgvRASqghICc6S9gciUuDZje3EUN1Vw90MpMuTPmUURSUnKv87i2jIkjNs/D6Drn5TQV0="],"From":"\"M.h. Lian\" ","To":"Bjorn Helgaas , \"Z.q. Hou\" ","Subject":"RE: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Thread-Topic":"[PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Thread-Index":"AQHTM3Zo2+0/F1OX0k+TniS4lz+8BaLfKdyAgAB313A=","Date":"Thu, 12 Oct 2017 03:01:19 +0000","Message-ID":"","References":"<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>\n\t<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>\n\t<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","In-Reply-To":"<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","Accept-Language":"zh-CN, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"IMf8fcOp\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1785120,"web_url":"http://patchwork.ozlabs.org/comment/1785120/","msgid":"","list_archive_url":null,"date":"2017-10-12T03:17:57","subject":"RE: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","submitter":{"id":67929,"url":"http://patchwork.ozlabs.org/api/people/67929/","name":"Z.Q. Hou","email":"zhiqiang.hou@nxp.com"},"content":"Hi Bjorn,\r\n\r\nThanks a lot for your comments!\r\n\r\n> -----Original Message-----\r\n> From: Bjorn Helgaas [mailto:helgaas@kernel.org]\r\n> Sent: 2017年10月12日 3:38\r\n> To: Z.q. Hou \r\n> Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;\r\n> linux-pci@vger.kernel.org; bhelgaas@google.com; Roy Zang\r\n> ; Mingkai Hu ; M.h. Lian\r\n> \r\n> Subject: Re: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode\r\n> \r\n> On Fri, Sep 22, 2017 at 03:25:21PM +0800, Zhiqiang Hou wrote:\r\n> > From: Hou Zhiqiang \r\n> >\r\n> > The Freescale PCIe controller advertises the MSI/MSI-X capability in\r\n> > both RC and Endpoint mode, but in RC mode it doesn't support MSI/MSI-X\r\n> > by it self, it can only transfer MSI/MSI-X from downstream\r\n> \r\n> s/it self,/itself;/\r\n\r\nI'll fix this typo in next version.\r\n\r\n> > devices. So add this quirk to prevent use of MSI/MSI-X in RC mode.\r\n> >\r\n> > Signed-off-by: Hou Zhiqiang \r\n> > ---\r\n> > drivers/pci/quirks.c | 8 ++++++++\r\n> > 1 file changed, 8 insertions(+)\r\n> >\r\n> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index\r\n> > a4d33619a7bb..c1063a420f0c 100644\r\n> > --- a/drivers/pci/quirks.c\r\n> > +++ b/drivers/pci/quirks.c\r\n> > @@ -4799,3 +4799,11 @@ static void quirk_no_ats(struct pci_dev *pdev)\r\n> > /* AMD Stoney platform GPU */\r\n> > DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);\r\n> > #endif /* CONFIG_PCI_ATS */\r\n> > +\r\n> > +/* Freescale PCIe doesn't support MSI in RC mode */ static void\r\n> > +quirk_fsl_no_msi(struct pci_dev *pdev) {\r\n> > +\tif (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)\r\n> > +\t\tpdev->no_msi = 1;\r\n> > +}\r\n> > +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,\r\n> > +quirk_fsl_no_msi);\r\n> \r\n> This disables MSI for all Freescale root ports, past, present, and future. Is\r\n> that really what you want? This is a bug (the root port shouldn't advertise\r\n> MSI if it doesn't support it), and presumably it might be fixed in some future\r\n> device?\r\n\r\nFor the past and present, there isn't Freescale root ports supporting MSI. If the future Freescale root port support MSI, I'll add a patch for it checking the PCI device ID to determine if apply the quirk.\r\nAnd it should be ok for the root ports without this bug.\r\n\r\n> \r\n> This needs an ack from Minghuan or Mingkai (based on MAINTAINERS).\r\n> \r\n\r\nThanks,\r\nZhiqiang","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"aTEWQjuB\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"MzcN/EZX\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; "],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yCGJk0wQBz9t2W\n\tfor ;\n\tThu, 12 Oct 2017 14:18:30 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2U0v-0003Pk-H9; Thu, 12 Oct 2017 03:18:25 +0000","from mail-eopbgr30060.outbound.protection.outlook.com\n\t([40.107.3.60] helo=EUR03-AM5-obe.outbound.protection.outlook.com)\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2U0q-0003BB-B5 for linux-arm-kernel@lists.infradead.org;\n\tThu, 12 Oct 2017 03:18:22 +0000","from AM5PR0402MB2771.eurprd04.prod.outlook.com (10.175.41.13) by\n\tAM4PR04MB1601.eurprd04.prod.outlook.com (10.164.78.147) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Thu, 12 Oct 2017 03:17:57 +0000","from AM5PR0402MB2771.eurprd04.prod.outlook.com\n\t([fe80::1ea:d5af:e18e:3b65]) by\n\tAM5PR0402MB2771.eurprd04.prod.outlook.com\n\t([fe80::1ea:d5af:e18e:3b65%13]) with mapi id 15.20.0077.020;\n\tThu, 12 Oct 2017 03:17:57 +0000"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=Lx42Uf1LmnxF7RDDm33deJ8y9MWo3f3F+aINDlDFGts=;\n\tb=aTEWQjuBsWvJ6Y\n\t03aPgpYBj83//Dww0szy/3TK0VRIDtT3KvhJDvS3oaZLdFmf+/tGi0Aejuz4r8Q6dU4v05fDPSHXh\n\tLVP2qnacLZ4e97mtByf78wu9IQbgtmHg75DQem71aWx/igly75xGkZWMxXBBecbHKARRYeXO01JVJ\n\tYDlEaWhvSIVqtVD+7qYqWFwOlC8bX+LSPbTgMjSiAWG7raqpSX4gSx7zVSirUd6gtKF6GcC9Hgpjt\n\t3B/GcAMT5GzFV0NRivGX/APp8fXeEkO7UYUzLN13DLYLF06ZZ9MciYY87t49VLGQpQlfr7seUy2zr\n\t/hhDdIi263jEUdIdnTEQ==;","v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=NVIHV+XO6V2snbcpiCOQmVZsDPxP6CqAN+Mmy8i24EI=;\n\tb=MzcN/EZXwMFYpasmeJ3Ho8EZh5/sQf1nD0M07X+kxeGpW8nOlJ1Sem0RF55fPjtrzsLxdtNEf3cmaMx0HivbShOnjQq2jVc1kRIHiLqjkLwF2AzRwqWWtDpyRjaEI7Xfi/+kc8BhjRynyR2VSXcHWa5fgzrRbkVyKM52P01JMnw="],"From":"\"Z.q. Hou\" ","To":"Bjorn Helgaas ","Subject":"RE: [PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Thread-Topic":"[PATCH 1/2] PCI: Disable MSI for Freescale PCIe RC mode","Thread-Index":"AQHTM3ZowioOzRa4+k2itj8tgleitqLfKdyAgAB6toA=","Date":"Thu, 12 Oct 2017 03:17:57 +0000","Message-ID":"","References":"<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>\n\t<20170922072522.36306-2-Zhiqiang.Hou@nxp.com>\n\t<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","In-Reply-To":"<20171011193737.GP25517@bhelgaas-glaptop.roam.corp.google.com>","Accept-Language":"zh-CN, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"aTEWQjuB\"; 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Lian\" ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t, \n\t\"bhelgaas@google.com\" ,\n\tMingkai Hu ","Content-Type":"text/plain; charset=\"gb2312\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1785127,"web_url":"http://patchwork.ozlabs.org/comment/1785127/","msgid":"","list_archive_url":null,"date":"2017-10-12T03:33:15","subject":"RE: [PATCH 2/2] pci/layerscape: change the default error response\n\tbehavior","submitter":{"id":67929,"url":"http://patchwork.ozlabs.org/api/people/67929/","name":"Z.Q. Hou","email":"zhiqiang.hou@nxp.com"},"content":"Hi Bjorn,\r\n\r\nThanks a lot for your review!\r\n\r\n> -----Original Message-----\r\n> From: Bjorn Helgaas [mailto:helgaas@kernel.org]\r\n> Sent: 2017年10月12日 3:41\r\n> To: Z.q. Hou \r\n> Cc: linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org;\r\n> linux-pci@vger.kernel.org; bhelgaas@google.com; Roy Zang\r\n> ; Mingkai Hu ; M.h. Lian\r\n> \r\n> Subject: Re: [PATCH 2/2] pci/layerscape: change the default error response\r\n> behavior\r\n> \r\n> On Fri, Sep 22, 2017 at 03:25:22PM +0800, Zhiqiang Hou wrote:\r\n> > From: Minghuan Lian \r\n> >\r\n> > By default, when the PCIe controller experiences an erroneous\r\n> > completion from an external completer for its outbound non-posted\r\n> > request, it always sends an OKAY response to the device's internal AXI\r\n> > slave system interface. However, such default system error response\r\n> > behavior cannot be used for other types of outbound non-posted\r\n> > requests. For example, the outbound memory read transaction requires\r\n> > an actual ERROR response, like UR completion or completion timeout.\r\n> > The patch is to fix it by forwarding the error response of the\r\n> > non-posted request.\r\n> >\r\n> > Signed-off-by: Minghuan Lian \r\n> > Signed-off-by: Hou Zhiqiang \r\n> > ---\r\n> > drivers/pci/dwc/pci-layerscape.c | 25 +++++++++++++++++++++++++\r\n> > 1 file changed, 25 insertions(+)\r\n> >\r\n> > diff --git a/drivers/pci/dwc/pci-layerscape.c\r\n> > b/drivers/pci/dwc/pci-layerscape.c\r\n> > index 3b01e309a55e..a647090c140e 100644\r\n> > --- a/drivers/pci/dwc/pci-layerscape.c\r\n> > +++ b/drivers/pci/dwc/pci-layerscape.c\r\n> > @@ -33,6 +33,8 @@\r\n> >\r\n> > /* PEX Internal Configuration Registers */\r\n> > #define PCIE_STRFMR1\t\t0x71c /* Symbol Timer & Filter Mask\r\n> Register1 */\r\n> > +#define PCIE_ABSERR\t\t0x8d0 /* Bridge Slave Error Response\r\n> Register */\r\n> > +#define PCIE_ABSERR_SETTING\t0x9401 /* Forward error of non-posted\r\n> request */\r\n> >\r\n> > #define PCIE_IATU_NUM\t\t6\r\n> >\r\n> > @@ -54,6 +56,19 @@ struct ls_pcie {\r\n> >\r\n> > #define to_ls_pcie(x)\tdev_get_drvdata((x)->dev)\r\n> >\r\n> > +static int err_response_flag = 1;\r\n> > +\r\n> > +static int __init ls_pcie_param(char *p) {\r\n> > +\tif (p && strncmp(p, \"no-err-response\", 15) == 0)\r\n> > +\t\terr_response_flag = 0;\r\n> > +\telse\r\n> > +\t\terr_response_flag = 1;\r\n> > +\r\n> > +\treturn 0;\r\n> > +}\r\n> > +early_param(\"ls_pcie\", ls_pcie_param);\r\n> \r\n> What's the point of this parameter? If it's for debugging, it's not clear that\r\n> we need it upstream. If it's for debugging and we *do* need it upstream,\r\n> there should be some sort of comment to that effect.\r\n> \r\n> I assume you never expect an end user to need this parameter.\r\n\r\nIt is for debugging, will drop this parameter next version.\r\n\r\n> \r\n> > static bool ls_pcie_is_bridge(struct ls_pcie *pcie) {\r\n> > \tstruct dw_pcie *pci = pcie->pci;\r\n> > @@ -124,6 +139,14 @@ static int ls_pcie_link_up(struct dw_pcie *pci)\r\n> > \treturn 1;\r\n> > }\r\n> >\r\n> > +/* Forward error response of outbound non-posted requests */ static\r\n> > +void ls_pcie_fix_error_response(struct ls_pcie *pcie) {\r\n> > +\tstruct dw_pcie *pci = pcie->pci;\r\n> > +\r\n> > +\tiowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); }\r\n> > +\r\n> > static int ls_pcie_host_init(struct pcie_port *pp) {\r\n> > \tstruct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -135,6 +158,8 @@\r\n> > static int ls_pcie_host_init(struct pcie_port *pp)\r\n> > \t * dw_pcie_setup_rc() will reconfigure the outbound windows.\r\n> > \t */\r\n> > \tls_pcie_disable_outbound_atus(pcie);\r\n> > +\tif (err_response_flag)\r\n> > +\t\tls_pcie_fix_error_response(pcie);\r\n> >\r\n> > \tdw_pcie_dbi_ro_wr_en(pci);\r\n> > \tls_pcie_clear_multifunction(pcie);\r\n> > --\r\n> > 2.14.1\r\n> >\r\n\r\nThanks,\r\nZhiqiang","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"osbYpZjT\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=nxp.com header.i=@nxp.com header.b=\"PO1UHZUQ\"; \n\tdkim-atps=neutral","spf=none (sender IP is )\n\tsmtp.mailfrom=zhiqiang.hou@nxp.com; "],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yCGfS6Mw1z9t2W\n\tfor ;\n\tThu, 12 Oct 2017 14:33:52 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2UFo-0001iH-KR; Thu, 12 Oct 2017 03:33:48 +0000","from mail-eopbgr10068.outbound.protection.outlook.com\n\t([40.107.1.68] helo=EUR02-HE1-obe.outbound.protection.outlook.com)\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e2UFj-0001UH-Jz for linux-arm-kernel@lists.infradead.org;\n\tThu, 12 Oct 2017 03:33:46 +0000","from AM5PR0402MB2771.eurprd04.prod.outlook.com (10.175.41.13) by\n\tAM5PR04MB3073.eurprd04.prod.outlook.com (10.173.254.152) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id\n\t15.20.77.7; Thu, 12 Oct 2017 03:33:16 +0000","from AM5PR0402MB2771.eurprd04.prod.outlook.com\n\t([fe80::1ea:d5af:e18e:3b65]) by\n\tAM5PR0402MB2771.eurprd04.prod.outlook.com\n\t([fe80::1ea:d5af:e18e:3b65%13]) with mapi id 15.20.0077.020;\n\tThu, 12 Oct 2017 03:33:15 +0000"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=zGQ/p6qa/h1GaoHsHnP+p7ur8hEJy5hhMqCblJmy6Hg=;\n\tb=osbYpZjTsTqbEz\n\tmdTOEIILtSqhhthTwuNH2OPfS8URPe9R9H0xBa02VeIgUsNNkGj8VAaZAPDcu6SKEWI42qzKUVX4Z\n\tp89ijOgLbDmg6em06xfbk3vfMPFAA/8aEp9eZnPni6vKeIcnozElpNBPnTjtdqTRgxji3m0xAO3f6\n\t813VRSbN+/pAHAD7uZfz0ekiBZJyCxbVx1r9oZ42+2uaiRovp0CfgR++ziA/0dIIy8Ub6+5v/pALS\n\t0ipsxC9uKjlQpk+bfAbSfFWNlexk007FmLR9jGYmkwZtYVn8PtRx5G2Cuqhm6t3VXg8mgV7wQtak2\n\tNmnLgJTv2JPmuJ3IzW+A==;","v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=ZXASNCay1jbKCl3B3Tb7WzbYzy2PxmC8HGQ6pQ24Uow=;\n\tb=PO1UHZUQjcUQxM8BYlse4BxIS9tFcjGgi8JhEaak6CYCvTxOVhrNrxGvhhJ1+fgLosqtRHsALYFijghGZ6cOVs4m5Wv2KmuxBDcARu9AhMnWNLqYqCojIICrH4dH45m7S85Vk5g/Wp1cqBUvopAxYdgp0ORLTprZEfbZbDsmIRg="],"From":"\"Z.q. Hou\" ","To":"Bjorn Helgaas ","Subject":"RE: [PATCH 2/2] pci/layerscape: change the default error response\n\tbehavior","Thread-Topic":"[PATCH 2/2] pci/layerscape: change the default error response\n\tbehavior","Thread-Index":"AQHTM3Zt3D+sncPEdE2JYaIs8rzXPaLfKvCAgACC34A=","Date":"Thu, 12 Oct 2017 03:33:15 +0000","Message-ID":"","References":"<20170922072522.36306-1-Zhiqiang.Hou@nxp.com>\n\t<20170922072522.36306-3-Zhiqiang.Hou@nxp.com>\n\t<20171011194129.GQ25517@bhelgaas-glaptop.roam.corp.google.com>","In-Reply-To":"<20171011194129.GQ25517@bhelgaas-glaptop.roam.corp.google.com>","Accept-Language":"zh-CN, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","authentication-results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"osbYpZjT\"; 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Lian\" ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t, \n\t\"bhelgaas@google.com\" ,\n\tMingkai Hu ","Content-Type":"text/plain; charset=\"gb2312\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}}]