[{"id":1775227,"web_url":"http://patchwork.ozlabs.org/comment/1775227/","msgid":"<32e4d8e5-e95c-9048-26b0-4ffe2c36ff02@ti.com>","list_archive_url":null,"date":"2017-09-26T08:03:08","subject":"Re: [RESEND PATCH v5 2/4] dmaengine: Add STM32 DMAMUX driver","submitter":{"id":9142,"url":"http://patchwork.ozlabs.org/api/people/9142/","name":"Peter Ujfalusi","email":"peter.ujfalusi@ti.com"},"content":"\n\n\nTexas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n\nOn 2017-09-22 10:31, Pierre-Yves MORDRET wrote:\n> This patch implements the STM32 DMAMUX driver.\n> \n> The DMAMUX request multiplexer allows routing a DMA request line between\n> the peripherals and the DMA controllers of the product. The routing\n> function is ensured by a programmable multi-channel DMA request line\n> multiplexer. Each channel selects a unique DMA request line,\n> unconditionally or synchronously with events from its DMAMUX\n> synchronization inputs. The DMAMUX may also be used as a DMA request\n> generator from programmable events on its input trigger signals\n> \n> Signed-off-by: M'boumba Cedric Madianga \n> Signed-off-by: Pierre-Yves MORDRET \n\nReviewed-by: Peter Ujfalusi \n\n> ---\n> Version history:\n> v5:\n> * Set selected channel ID within a lock to avoid race condition.\n> Release if any error occurs\n> v4:\n> * Get rid of st,dmamux property and custom API between STM32\n> DMAMUX and DMA.\n> DMAMUX will read DMA masters from Device Tree from now on.\n> Merely one DMAMUX node is needed now.\n> * Only STM32 DMA are allowed to be connected onto DMAMUX\n> * channelID is computed locally within the driver and crafted in\n> dma_psec to be passed toward DMA master.\n> DMAMUX router sorts out which DMA master will serve the\n> request automatically.\n> * This version forbids the use of DMA in standalone and DMAMUX at\n> the same time : all clients need to be connected either on DMA\n> or DMAMUX ; no mix up\n> v3:\n> * change compatible to st,stm32h7-dmamux to be mode SoC specific\n> v2:\n> * Dynamic channelID allocation.\n> * Change of_property_... by device_property.\n> * New clock management.\n> * DMAMUX Configuration API.\n> ---\n> ---\n> drivers/dma/Kconfig | 9 ++\n> drivers/dma/Makefile | 1 +\n> drivers/dma/stm32-dmamux.c | 327 +++++++++++++++++++++++++++++++++++++++++++++\n> 3 files changed, 337 insertions(+)\n> create mode 100644 drivers/dma/stm32-dmamux.c\n> \n> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig\n> index fadc4d8..04e381b 100644\n> --- a/drivers/dma/Kconfig\n> +++ b/drivers/dma/Kconfig\n> @@ -483,6 +483,15 @@ config STM32_DMA\n> \t If you have a board based on such a MCU and wish to use DMA say Y\n> \t here.\n> \n> +config STM32_DMAMUX\n> +\tbool \"STMicroelectronics STM32 dma multiplexer support\"\n> +\tdepends on STM32_DMA || COMPILE_TEST\n> +\thelp\n> +\t Enable support for the on-chip DMA multiplexer on STMicroelectronics\n> +\t STM32 MCUs.\n> +\t If you have a board based on such a MCU and wish to use DMAMUX say Y\n> +\t here.\n> +\n> config S3C24XX_DMAC\n> \tbool \"Samsung S3C24XX DMA support\"\n> \tdepends on ARCH_S3C24XX || COMPILE_TEST\n> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile\n> index f08f8de..a145ad1 100644\n> --- a/drivers/dma/Makefile\n> +++ b/drivers/dma/Makefile\n> @@ -59,6 +59,7 @@ obj-$(CONFIG_RENESAS_DMA) += sh/\n> obj-$(CONFIG_SIRF_DMA) += sirf-dma.o\n> obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o\n> obj-$(CONFIG_STM32_DMA) += stm32-dma.o\n> +obj-$(CONFIG_STM32_DMAMUX) += stm32-dmamux.o\n> obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o\n> obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o\n> obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o\n> diff --git a/drivers/dma/stm32-dmamux.c b/drivers/dma/stm32-dmamux.c\n> new file mode 100644\n> index 0000000..22812e7\n> --- /dev/null\n> +++ b/drivers/dma/stm32-dmamux.c\n> @@ -0,0 +1,327 @@\n> +/*\n> + *\n> + * Copyright (C) STMicroelectronics SA 2017\n> + * Author(s): M'boumba Cedric Madianga \n> + * Pierre-Yves Mordret \n> + *\n> + * License terms: GPL V2.0.\n> + *\n> + * This program is free software; you can redistribute it and/or modify it\n> + * under the terms of the GNU General Public License version 2 as published by\n> + * the Free Software Foundation.\n> + *\n> + * This program is distributed in the hope that it will be useful, but\n> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\n> + * details.\n> + *\n> + * DMA Router driver for STM32 DMA MUX\n> + *\n> + * Based on TI DMA Crossbar driver\n> + *\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define STM32_DMAMUX_CCR(x)\t\t(0x4 * (x))\n> +#define STM32_DMAMUX_MAX_DMA_REQUESTS\t32\n> +#define STM32_DMAMUX_MAX_REQUESTS\t255\n> +\n> +struct stm32_dmamux {\n> +\tu32 master;\n> +\tu32 request;\n> +\tu32 chan_id;\n> +};\n> +\n> +struct stm32_dmamux_data {\n> +\tstruct dma_router dmarouter;\n> +\tstruct clk *clk;\n> +\tstruct reset_control *rst;\n> +\tvoid __iomem *iomem;\n> +\tu32 dma_requests; /* Number of DMA requests connected to DMAMUX */\n> +\tu32 dmamux_requests; /* Number of DMA requests routed toward DMAs */\n> +\tspinlock_t lock; /* Protects register access */\n> +\tunsigned long *dma_inuse; /* Used DMA channel */\n> +\tu32 dma_reqs[]; /* Number of DMA Request per DMA masters.\n> +\t\t\t * [0] holds number of DMA Masters.\n> +\t\t\t * To be kept at very end end of this structure\n> +\t\t\t */\n> +};\n> +\n> +static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)\n> +{\n> +\treturn readl_relaxed(iomem + reg);\n> +}\n> +\n> +static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)\n> +{\n> +\twritel_relaxed(val, iomem + reg);\n> +}\n> +\n> +static void stm32_dmamux_free(struct device *dev, void *route_data)\n> +{\n> +\tstruct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);\n> +\tstruct stm32_dmamux *mux = route_data;\n> +\tunsigned long flags;\n> +\n> +\t/* Clear dma request */\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\n> +\tstm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);\n> +\tclear_bit(mux->chan_id, dmamux->dma_inuse);\n> +\n> +\tif (!IS_ERR(dmamux->clk))\n> +\t\tclk_disable(dmamux->clk);\n> +\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\n> +\tdev_dbg(dev, \"Unmapping DMAMUX(%u) to DMA%u(%u)\\n\",\n> +\t\tmux->request, mux->master, mux->chan_id);\n> +\n> +\tkfree(mux);\n> +}\n> +\n> +static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,\n> +\t\t\t\t\t struct of_dma *ofdma)\n> +{\n> +\tstruct platform_device *pdev = of_find_device_by_node(ofdma->of_node);\n> +\tstruct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);\n> +\tstruct stm32_dmamux *mux;\n> +\tu32 i, min, max;\n> +\tint ret;\n> +\tunsigned long flags;\n> +\n> +\tif (dma_spec->args_count != 3) {\n> +\t\tdev_err(&pdev->dev, \"invalid number of dma mux args\\n\");\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\tif (dma_spec->args[0] > dmamux->dmamux_requests) {\n> +\t\tdev_err(&pdev->dev, \"invalid mux request number: %d\\n\",\n> +\t\t\tdma_spec->args[0]);\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\tmux = kzalloc(sizeof(*mux), GFP_KERNEL);\n> +\tif (!mux)\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\tmux->chan_id = find_first_zero_bit(dmamux->dma_inuse,\n> +\t\t\t\t\t dmamux->dma_requests);\n> +\tset_bit(mux->chan_id, dmamux->dma_inuse);\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\n> +\tif (mux->chan_id == dmamux->dma_requests) {\n> +\t\tdev_err(&pdev->dev, \"Run out of free DMA requests\\n\");\n> +\t\tret = -ENOMEM;\n> +\t\tgoto error;\n> +\t}\n> +\n> +\t/* Look for DMA Master */\n> +\tfor (i = 1, min = 0, max = dmamux->dma_reqs[i];\n> +\t i <= dmamux->dma_reqs[0];\n> +\t min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])\n> +\t\tif (mux->chan_id < max)\n> +\t\t\tbreak;\n> +\tmux->master = i - 1;\n> +\n> +\t/* The of_node_put() will be done in of_dma_router_xlate function */\n> +\tdma_spec->np = of_parse_phandle(ofdma->of_node, \"dma-masters\", i - 1);\n> +\tif (!dma_spec->np) {\n> +\t\tdev_err(&pdev->dev, \"can't get dma master\\n\");\n> +\t\tret = -EINVAL;\n> +\t\tgoto error;\n> +\t}\n> +\n> +\t/* Set dma request */\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\tif (!IS_ERR(dmamux->clk)) {\n> +\t\tret = clk_enable(dmamux->clk);\n> +\t\tif (ret < 0) {\n> +\t\t\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\t\t\tdev_err(&pdev->dev, \"clk_prep_enable issue: %d\\n\", ret);\n> +\t\t\tgoto error;\n> +\t\t}\n> +\t}\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\n> +\tmux->request = dma_spec->args[0];\n> +\n> +\t/* craft DMA spec */\n> +\tdma_spec->args[3] = dma_spec->args[2];\n> +\tdma_spec->args[2] = dma_spec->args[1];\n> +\tdma_spec->args[1] = 0;\n> +\tdma_spec->args[0] = mux->chan_id - min;\n> +\tdma_spec->args_count = 4;\n> +\n> +\tstm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),\n> +\t\t\t mux->request);\n> +\tdev_dbg(&pdev->dev, \"Mapping DMAMUX(%u) to DMA%u(%u)\\n\",\n> +\t\tmux->request, mux->master, mux->chan_id);\n> +\n> +\treturn mux;\n> +\n> +error:\n> +\tclear_bit(mux->chan_id, dmamux->dma_inuse);\n> +\tkfree(mux);\n> +\treturn ERR_PTR(ret);\n> +}\n> +\n> +static const struct of_device_id stm32_stm32dma_master_match[] = {\n> +\t{ .compatible = \"st,stm32-dma\", },\n> +\t{},\n> +};\n> +\n> +static int stm32_dmamux_probe(struct platform_device *pdev)\n> +{\n> +\tstruct device_node *node = pdev->dev.of_node;\n> +\tconst struct of_device_id *match;\n> +\tstruct device_node *dma_node;\n> +\tstruct stm32_dmamux_data *stm32_dmamux;\n> +\tstruct resource *res;\n> +\tvoid __iomem *iomem;\n> +\tint i, count, ret;\n> +\tu32 dma_req;\n> +\n> +\tif (!node)\n> +\t\treturn -ENODEV;\n> +\n> +\tcount = device_property_read_u32_array(&pdev->dev, \"dma-masters\",\n> +\t\t\t\t\t NULL, 0);\n> +\tif (count < 0) {\n> +\t\tdev_err(&pdev->dev, \"Can't get DMA master(s) node\\n\");\n> +\t\treturn -ENODEV;\n> +\t}\n> +\n> +\tstm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) +\n> +\t\t\t\t sizeof(u32) * (count + 1), GFP_KERNEL);\n> +\tif (!stm32_dmamux)\n> +\t\treturn -ENOMEM;\n> +\n> +\tdma_req = 0;\n> +\tfor (i = 1; i <= count; i++) {\n> +\t\tdma_node = of_parse_phandle(node, \"dma-masters\", i - 1);\n> +\n> +\t\tmatch = of_match_node(stm32_stm32dma_master_match, dma_node);\n> +\t\tif (!match) {\n> +\t\t\tdev_err(&pdev->dev, \"DMA master is not supported\\n\");\n> +\t\t\tof_node_put(dma_node);\n> +\t\t\treturn -EINVAL;\n> +\t\t}\n> +\n> +\t\tif (of_property_read_u32(dma_node, \"dma-requests\",\n> +\t\t\t\t\t &stm32_dmamux->dma_reqs[i])) {\n> +\t\t\tdev_info(&pdev->dev,\n> +\t\t\t\t \"Missing MUX output information, using %u.\\n\",\n> +\t\t\t\t STM32_DMAMUX_MAX_DMA_REQUESTS);\n> +\t\t\tstm32_dmamux->dma_reqs[i] =\n> +\t\t\t\tSTM32_DMAMUX_MAX_DMA_REQUESTS;\n> +\t\t}\n> +\t\tdma_req += stm32_dmamux->dma_reqs[i];\n> +\t\tof_node_put(dma_node);\n> +\t}\n> +\n> +\tif (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) {\n> +\t\tdev_err(&pdev->dev, \"Too many DMA Master Requests to manage\\n\");\n> +\t\treturn -ENODEV;\n> +\t}\n> +\n> +\tstm32_dmamux->dma_requests = dma_req;\n> +\tstm32_dmamux->dma_reqs[0] = count;\n> +\tstm32_dmamux->dma_inuse = devm_kcalloc(&pdev->dev,\n> +\t\t\t\t\t BITS_TO_LONGS(dma_req),\n> +\t\t\t\t\t sizeof(unsigned long),\n> +\t\t\t\t\t GFP_KERNEL);\n> +\tif (!stm32_dmamux->dma_inuse)\n> +\t\treturn -ENOMEM;\n> +\n> +\tif (device_property_read_u32(&pdev->dev, \"dma-requests\",\n> +\t\t\t\t &stm32_dmamux->dmamux_requests)) {\n> +\t\tstm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;\n> +\t\tdev_warn(&pdev->dev, \"DMAMUX defaulting on %u requests\\n\",\n> +\t\t\t stm32_dmamux->dmamux_requests);\n> +\t}\n> +\n> +\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> +\tif (!res)\n> +\t\treturn -ENODEV;\n> +\n> +\tiomem = devm_ioremap_resource(&pdev->dev, res);\n> +\tif (!iomem)\n> +\t\treturn -ENOMEM;\n> +\n> +\tspin_lock_init(&stm32_dmamux->lock);\n> +\n> +\tstm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL);\n> +\tif (IS_ERR(stm32_dmamux->clk)) {\n> +\t\tret = PTR_ERR(stm32_dmamux->clk);\n> +\t\tif (ret == -EPROBE_DEFER)\n> +\t\t\tdev_info(&pdev->dev, \"Missing controller clock\\n\");\n> +\t\treturn ret;\n> +\t}\n> +\n> +\tstm32_dmamux->rst = devm_reset_control_get(&pdev->dev, NULL);\n> +\tif (!IS_ERR(stm32_dmamux->rst)) {\n> +\t\treset_control_assert(stm32_dmamux->rst);\n> +\t\tudelay(2);\n> +\t\treset_control_deassert(stm32_dmamux->rst);\n> +\t}\n> +\n> +\tstm32_dmamux->iomem = iomem;\n> +\tstm32_dmamux->dmarouter.dev = &pdev->dev;\n> +\tstm32_dmamux->dmarouter.route_free = stm32_dmamux_free;\n> +\n> +\tplatform_set_drvdata(pdev, stm32_dmamux);\n> +\n> +\tif (!IS_ERR(stm32_dmamux->clk)) {\n> +\t\tret = clk_prepare_enable(stm32_dmamux->clk);\n> +\t\tif (ret < 0) {\n> +\t\t\tdev_err(&pdev->dev, \"clk_prep_enable error: %d\\n\", ret);\n> +\t\t\treturn ret;\n> +\t\t}\n> +\t}\n> +\n> +\t/* Reset the dmamux */\n> +\tfor (i = 0; i < stm32_dmamux->dma_requests; i++)\n> +\t\tstm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);\n> +\n> +\tif (!IS_ERR(stm32_dmamux->clk))\n> +\t\tclk_disable(stm32_dmamux->clk);\n> +\n> +\treturn of_dma_router_register(node, stm32_dmamux_route_allocate,\n> +\t\t\t\t &stm32_dmamux->dmarouter);\n> +}\n> +\n> +static const struct of_device_id stm32_dmamux_match[] = {\n> +\t{ .compatible = \"st,stm32h7-dmamux\" },\n> +\t{},\n> +};\n> +\n> +static struct platform_driver stm32_dmamux_driver = {\n> +\t.probe\t= stm32_dmamux_probe,\n> +\t.driver = {\n> +\t\t.name = \"stm32-dmamux\",\n> +\t\t.of_match_table = stm32_dmamux_match,\n> +\t},\n> +};\n> +\n> +static int __init stm32_dmamux_init(void)\n> +{\n> +\treturn platform_driver_register(&stm32_dmamux_driver);\n> +}\n> +arch_initcall(stm32_dmamux_init);\n> +\n> +MODULE_DESCRIPTION(\"DMA Router driver for STM32 DMA MUX\");\n> +MODULE_AUTHOR(\"M'boumba Cedric Madianga \");\n> +MODULE_AUTHOR(\"Pierre-Yves Mordret \");\n> +MODULE_LICENSE(\"GPL v2\");\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"MXv9U9ol\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1YPx31hFz9sBZ\n\tfor ;\n\tTue, 26 Sep 2017 18:04:21 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S967055AbdIZIET (ORCPT );\n\tTue, 26 Sep 2017 04:04:19 -0400","from fllnx210.ext.ti.com ([198.47.19.17]:31273 \"EHLO\n\tfllnx210.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by 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v8Q82xLv022187;\n\tTue, 26 Sep 2017 03:03:00 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1506412984;\n\tbh=WndnI4fvHcG3SklQMEui2OW70Ka6hSmELHWh9HbiAkU=;\n\th=Subject:To:References:From:Date:In-Reply-To;\n\tb=MXv9U9ol/kfTvXLMWgB31M8EYk71GhKTXsWF4vyap0pPdYXKnxA/W20TiFQcdQcsb\n\tPZRcX2+G0s5jNLAKns2sx0xXl65HHlG/iI3PvrU1c780Z0jEA4NifjLcpC7somVloC\n\thdLBCChW5F2D4ULjjrSaUR0XJqIva962B9BfiDzQ=","Subject":"Re: [RESEND PATCH v5 2/4] dmaengine: Add STM32 DMAMUX driver","To":"Pierre-Yves MORDRET ,\n\tVinod Koul , Rob Herring , \n\tMark Rutland ,\n\tMaxime Coquelin ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\tDan Williams ,\n\t\"M'boumba Cedric Madianga\" ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\t, ,\n\t, ","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1506065492-31478-3-git-send-email-pierre-yves.mordret@st.com>","From":"Peter Ujfalusi ","Message-ID":"<32e4d8e5-e95c-9048-26b0-4ffe2c36ff02@ti.com>","Date":"Tue, 26 Sep 2017 11:03:08 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<1506065492-31478-3-git-send-email-pierre-yves.mordret@st.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"quoted-printable","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1775673,"web_url":"http://patchwork.ozlabs.org/comment/1775673/","msgid":"<20170926164603.GP30097@localhost>","list_archive_url":null,"date":"2017-09-26T16:46:03","subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Fri, Sep 22, 2017 at 09:31:32AM +0200, Pierre-Yves MORDRET wrote:\n> This patch adds DMAMUX support in STM32 defconfig file\n\nNeed ACK from ARM folks on this.\n\n> \n> Signed-off-by: M'boumba Cedric Madianga \n> Signed-off-by: Pierre-Yves MORDRET \n> ---\n> Version history:\n> v5:\n> v4:\n> v3:\n> v2:\n> * None\n> ---\n> ---\n> arch/arm/configs/stm32_defconfig | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig\n> index 90e5c46..988f395 100644\n> --- a/arch/arm/configs/stm32_defconfig\n> +++ b/arch/arm/configs/stm32_defconfig\n> @@ -67,6 +67,7 @@ CONFIG_RTC_CLASS=y\n> CONFIG_RTC_DRV_STM32=y\n> CONFIG_DMADEVICES=y\n> CONFIG_STM32_DMA=y\n> +CONFIG_STM32_DMAMUX=y\n> CONFIG_IIO=y\n> CONFIG_STM32_ADC_CORE=y\n> CONFIG_STM32_ADC=y\n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1mvV3VLpz9sxR\n\tfor ;\n\tWed, 27 Sep 2017 02:42:14 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S968978AbdIZQmM (ORCPT );\n\tTue, 26 Sep 2017 12:42:12 -0400","from mga07.intel.com ([134.134.136.100]:28526 \"EHLO\n\tmga07.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S965823AbdIZQmL (ORCPT );\n\tTue, 26 Sep 2017 12:42:11 -0400","from orsmga004.jf.intel.com ([10.7.209.38])\n\tby orsmga105.jf.intel.com with ESMTP; 26 Sep 2017 09:42:10 -0700","from vkoul-udesk7.iind.intel.com (HELO localhost) ([10.223.84.143])\n\tby orsmga004.jf.intel.com with ESMTP; 26 Sep 2017 09:42:05 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,441,1500966000\"; d=\"scan'208\";a=\"132513683\"","Date":"Tue, 26 Sep 2017 22:16:03 +0530","From":"Vinod Koul ","To":"Pierre-Yves MORDRET ,\n\tArnd Bergmann ","Cc":"Rob Herring , Mark Rutland ,\n\tMaxime Coquelin ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\tDan Williams ,\n\tM'boumba Cedric Madianga ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\tdmaengine@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","Message-ID":"<20170926164603.GP30097@localhost>","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1506065492-31478-5-git-send-email-pierre-yves.mordret@st.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1506065492-31478-5-git-send-email-pierre-yves.mordret@st.com>","User-Agent":"Mutt/1.5.24 (2015-08-30)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776069,"web_url":"http://patchwork.ozlabs.org/comment/1776069/","msgid":"","list_archive_url":null,"date":"2017-09-27T06:59:55","subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","submitter":{"id":68429,"url":"http://patchwork.ozlabs.org/api/people/68429/","name":"Alexandre TORGUE","email":"alexandre.torgue@st.com"},"content":"Hi Vinod\n\nOn 09/26/2017 06:46 PM, Vinod Koul wrote:\n> On Fri, Sep 22, 2017 at 09:31:32AM +0200, Pierre-Yves MORDRET wrote:\n>> This patch adds DMAMUX support in STM32 defconfig file\n> \n> Need ACK from ARM folks on this.\n\nI will take it in my pull request.\n\nRegards\nAlex\n> \n>>\n>> Signed-off-by: M'boumba Cedric Madianga \n>> Signed-off-by: Pierre-Yves MORDRET \n>> ---\n>> Version history:\n>> v5:\n>> v4:\n>> v3:\n>> v2:\n>> * None\n>> ---\n>> ---\n>> arch/arm/configs/stm32_defconfig | 1 +\n>> 1 file changed, 1 insertion(+)\n>>\n>> diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig\n>> index 90e5c46..988f395 100644\n>> --- a/arch/arm/configs/stm32_defconfig\n>> +++ b/arch/arm/configs/stm32_defconfig\n>> @@ -67,6 +67,7 @@ CONFIG_RTC_CLASS=y\n>> CONFIG_RTC_DRV_STM32=y\n>> CONFIG_DMADEVICES=y\n>> CONFIG_STM32_DMA=y\n>> +CONFIG_STM32_DMAMUX=y\n>> CONFIG_IIO=y\n>> CONFIG_STM32_ADC_CORE=y\n>> CONFIG_STM32_ADC=y\n>> -- \n>> 2.7.4\n>>\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y27yv689Kz9t4Z\n\tfor ;\n\tWed, 27 Sep 2017 17:01:27 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751524AbdI0HBZ (ORCPT\n\t);\n\tWed, 27 Sep 2017 03:01:25 -0400","from mx07-00178001.pphosted.com ([62.209.51.94]:64213 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1751136AbdI0HBY (ORCPT\n\t); Wed, 27 Sep 2017 03:01:24 -0400","from pps.filterd (m0046668.ppops.net [127.0.0.1])\n\tby mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8R6x5CF003106; Wed, 27 Sep 2017 09:00:21 +0200","from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx07-00178001.pphosted.com with ESMTP id 2d872m01x2-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tWed, 27 Sep 2017 09:00:21 +0200","from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9A34C31;\n\tWed, 27 Sep 2017 07:00:19 +0000 (GMT)","from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 46AA31456;\n\tWed, 27 Sep 2017 07:00:19 +0000 (GMT)","from [10.201.22.135] (10.75.127.46) by SFHDAG3NODE2.st.com\n\t(10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tWed, 27 Sep 2017 09:00:18 +0200"],"Subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","To":"Vinod Koul ,\n\tPierre-Yves MORDRET ,\n\tArnd Bergmann ","CC":"Rob Herring , Mark Rutland ,\n\tMaxime Coquelin ,\n\tRussell King ,\n\tDan Williams ,\n\t\"M'boumba Cedric Madianga\" ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\t, ,\n\t, ","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1506065492-31478-5-git-send-email-pierre-yves.mordret@st.com>\n\t<20170926164603.GP30097@localhost>","From":"Alexandre Torgue ","Message-ID":"","Date":"Wed, 27 Sep 2017 08:59:55 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170926164603.GP30097@localhost>","Content-Type":"text/plain; charset=\"utf-8\"; format=flowed","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.75.127.46]","X-ClientProxiedBy":"SFHDAG7NODE3.st.com (10.75.127.21) To SFHDAG3NODE2.st.com\n\t(10.75.127.8)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-27_02:, , signatures=0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776229,"web_url":"http://patchwork.ozlabs.org/comment/1776229/","msgid":"<20170927103631.GL30097@localhost>","list_archive_url":null,"date":"2017-09-27T10:36:31","subject":"Re: [RESEND PATCH v5 0/4] Add STM32 DMAMUX support","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Fri, Sep 22, 2017 at 09:31:28AM +0200, Pierre-Yves MORDRET wrote:\n> This patchset adds support for the STM32 DMA multiplexer.\n> It allows to map any peripheral DMA request to any channel of the product\n> DMAs.\n> This IP has been introduced with STM32H7 SoC.\n\nApplied first three patches, thanks\n\n> ---\n> Version history:\n> v5:\n> * Set selected channel ID within a lock to avoid race condition.\n> Release if any error occurs\n> v4:\n> * Add multi-master ability for STM32 DMAMUX\n> * Get rid of st,dmamux property and custom API between STM32\n> DMAMUX and DMA. Bindings has changed.\n> DMAMUX will read DMA masters from Device Tree from now on.\n> Merely one DMAMUX node is needed now.\n> * Only STM32 DMA are allowed to be connected onto DMAMUX\n> * channelID is computed locally within the driver and crafted in\n> dma_psec to be passed toward DMA master.\n> DMAMUX router sorts out which DMA master will serve the\n> request automatically.\n> * This version forbids the use of DMA in standalone and DMAMUX at\n> the same time : all clients need to be connected either on DMA\n> or DMAMUX ; no mix up\n> v3:\n> * change compatible to st,stm32h7-dmamux to be mode Soc specific\n> * add verbosity in dma-cells\n> ---\n> \n> Pierre-Yves MORDRET (4):\n> dt-bindings: Document the STM32 DMAMUX bindings\n> dmaengine: Add STM32 DMAMUX driver\n> dt-bindings: stm32-dma: add a property to handle STM32 DMAMUX\n> ARM: configs: stm32: Add DMAMUX support in STM32 defconfig\n> \n> .../devicetree/bindings/dma/stm32-dma.txt | 4 +-\n> .../devicetree/bindings/dma/stm32-dmamux.txt | 84 ++++++\n> arch/arm/configs/stm32_defconfig | 1 +\n> drivers/dma/Kconfig | 9 +\n> drivers/dma/Makefile | 1 +\n> drivers/dma/stm32-dmamux.c | 327 +++++++++++++++++++++\n> 6 files changed, 425 insertions(+), 1 deletion(-)\n> create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt\n> create mode 100644 drivers/dma/stm32-dmamux.c\n> \n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2Dfd6RnMz9tXQ\n\tfor ;\n\tWed, 27 Sep 2017 20:32:41 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751563AbdI0Kck (ORCPT\n\t);\n\tWed, 27 Sep 2017 06:32:40 -0400","from mga01.intel.com ([192.55.52.88]:2308 \"EHLO mga01.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750854AbdI0Kcj (ORCPT );\n\tWed, 27 Sep 2017 06:32:39 -0400","from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Sep 2017 03:32:37 -0700","from vkoul-udesk7.iind.intel.com (HELO localhost) ([10.223.84.143])\n\tby orsmga004.jf.intel.com with ESMTP; 27 Sep 2017 03:32:32 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,444,1500966000\"; d=\"scan'208\";a=\"132802932\"","Date":"Wed, 27 Sep 2017 16:06:31 +0530","From":"Vinod Koul ","To":"Pierre-Yves MORDRET ","Cc":"Rob Herring , Mark Rutland ,\n\tMaxime Coquelin ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\tDan Williams ,\n\tM'boumba Cedric Madianga ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\tdmaengine@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [RESEND PATCH v5 0/4] Add STM32 DMAMUX support","Message-ID":"<20170927103631.GL30097@localhost>","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>","User-Agent":"Mutt/1.5.24 (2015-08-30)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776230,"web_url":"http://patchwork.ozlabs.org/comment/1776230/","msgid":"<20170927103655.GM30097@localhost>","list_archive_url":null,"date":"2017-09-27T10:36:55","subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Wed, Sep 27, 2017 at 08:59:55AM +0200, Alexandre Torgue wrote:\n> Hi Vinod\n> \n> On 09/26/2017 06:46 PM, Vinod Koul wrote:\n> >On Fri, Sep 22, 2017 at 09:31:32AM +0200, Pierre-Yves MORDRET wrote:\n> >>This patch adds DMAMUX support in STM32 defconfig file\n> >\n> >Need ACK from ARM folks on this.\n> \n> I will take it in my pull request.\n\nsure, other are applied now","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2Dg52mDDz9tXf\n\tfor ;\n\tWed, 27 Sep 2017 20:33:05 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752331AbdI0KdD (ORCPT\n\t);\n\tWed, 27 Sep 2017 06:33:03 -0400","from mga03.intel.com ([134.134.136.65]:24175 \"EHLO mga03.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1752317AbdI0KdC (ORCPT );\n\tWed, 27 Sep 2017 06:33:02 -0400","from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Sep 2017 03:33:01 -0700","from vkoul-udesk7.iind.intel.com (HELO localhost) ([10.223.84.143])\n\tby fmsmga005.fm.intel.com with ESMTP; 27 Sep 2017 03:32:57 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,444,1500966000\"; d=\"scan'208\";a=\"156076466\"","Date":"Wed, 27 Sep 2017 16:06:55 +0530","From":"Vinod Koul ","To":"Alexandre Torgue ","Cc":"Pierre-Yves MORDRET ,\n\tArnd Bergmann , Rob Herring ,\n\tMark Rutland ,\n\tMaxime Coquelin ,\n\tRussell King ,\n\tDan Williams ,\n\tM'boumba Cedric Madianga ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\tdmaengine@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","Message-ID":"<20170927103655.GM30097@localhost>","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1506065492-31478-5-git-send-email-pierre-yves.mordret@st.com>\n\t<20170926164603.GP30097@localhost>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.5.24 (2015-08-30)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1776303,"web_url":"http://patchwork.ozlabs.org/comment/1776303/","msgid":"<3bda21bc-26e9-cc15-7227-8ed1523ab4fa@st.com>","list_archive_url":null,"date":"2017-09-27T12:31:03","subject":"Re: [RESEND PATCH v5 0/4] Add STM32 DMAMUX support","submitter":{"id":71499,"url":"http://patchwork.ozlabs.org/api/people/71499/","name":"Pierre Yves MORDRET","email":"pierre-yves.mordret@st.com"},"content":"Thanks Vinod.\nThe fourth is going to be managed by ARM team.\n\nRegards\n\nOn 09/27/2017 12:36 PM, Vinod Koul wrote:\n> On Fri, Sep 22, 2017 at 09:31:28AM +0200, Pierre-Yves MORDRET wrote:\n>> This patchset adds support for the STM32 DMA multiplexer.\n>> It allows to map any peripheral DMA request to any channel of the product\n>> DMAs.\n>> This IP has been introduced with STM32H7 SoC.\n> \n> Applied first three patches, thanks\n> \n>> ---\n>> Version history:\n>> v5:\n>> * Set selected channel ID within a lock to avoid race condition.\n>> Release if any error occurs\n>> v4:\n>> * Add multi-master ability for STM32 DMAMUX\n>> * Get rid of st,dmamux property and custom API between STM32\n>> DMAMUX and DMA. Bindings has changed.\n>> DMAMUX will read DMA masters from Device Tree from now on.\n>> Merely one DMAMUX node is needed now.\n>> * Only STM32 DMA are allowed to be connected onto DMAMUX\n>> * channelID is computed locally within the driver and crafted in\n>> dma_psec to be passed toward DMA master.\n>> DMAMUX router sorts out which DMA master will serve the\n>> request automatically.\n>> * This version forbids the use of DMA in standalone and DMAMUX at\n>> the same time : all clients need to be connected either on DMA\n>> or DMAMUX ; no mix up\n>> v3:\n>> * change compatible to st,stm32h7-dmamux to be mode Soc specific\n>> * add verbosity in dma-cells\n>> ---\n>>\n>> Pierre-Yves MORDRET (4):\n>> dt-bindings: Document the STM32 DMAMUX bindings\n>> dmaengine: Add STM32 DMAMUX driver\n>> dt-bindings: stm32-dma: add a property to handle STM32 DMAMUX\n>> ARM: configs: stm32: Add DMAMUX support in STM32 defconfig\n>>\n>> .../devicetree/bindings/dma/stm32-dma.txt | 4 +-\n>> .../devicetree/bindings/dma/stm32-dmamux.txt | 84 ++++++\n>> arch/arm/configs/stm32_defconfig | 1 +\n>> drivers/dma/Kconfig | 9 +\n>> drivers/dma/Makefile | 1 +\n>> drivers/dma/stm32-dmamux.c | 327 +++++++++++++++++++++\n>> 6 files changed, 425 insertions(+), 1 deletion(-)\n>> create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt\n>> create mode 100644 drivers/dma/stm32-dmamux.c\n>>\n>> -- \n>> 2.7.4\n>>\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y2HJk0TKCz9tXT\n\tfor ;\n\tWed, 27 Sep 2017 22:32:22 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752794AbdI0McH (ORCPT\n\t);\n\tWed, 27 Sep 2017 08:32:07 -0400","from mx07-00178001.pphosted.com ([62.209.51.94]:11369 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1752780AbdI0McE (ORCPT\n\t); Wed, 27 Sep 2017 08:32:04 -0400","from pps.filterd (m0046037.ppops.net [127.0.0.1])\n\tby mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv8RCSmbB007120; Wed, 27 Sep 2017 14:31:09 +0200","from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx07-00178001.pphosted.com with ESMTP id 2d8bngr66n-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tWed, 27 Sep 2017 14:31:09 +0200","from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C26DE31;\n\tWed, 27 Sep 2017 12:31:08 +0000 (GMT)","from Webmail-eu.st.com (sfhdag5node2.st.com [10.75.127.14])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 883D62792;\n\tWed, 27 Sep 2017 12:31:08 +0000 (GMT)","from [10.201.23.236] (10.75.127.44) by SFHDAG5NODE2.st.com\n\t(10.75.127.14) with Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tWed, 27 Sep 2017 14:31:07 +0200"],"Subject":"Re: [RESEND PATCH v5 0/4] Add STM32 DMAMUX support","To":"Vinod Koul ","CC":"Rob Herring , Mark Rutland ,\n\tMaxime Coquelin ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\tDan Williams ,\n\t\"M'boumba Cedric Madianga\" ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\t, ,\n\t, ","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<20170927103631.GL30097@localhost>","From":"Pierre Yves MORDRET ","Message-ID":"<3bda21bc-26e9-cc15-7227-8ed1523ab4fa@st.com>","Date":"Wed, 27 Sep 2017 14:31:03 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170927103631.GL30097@localhost>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.75.127.44]","X-ClientProxiedBy":"SFHDAG3NODE1.st.com (10.75.127.7) To SFHDAG5NODE2.st.com\n\t(10.75.127.14)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-27_03:, , signatures=0","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1781611,"web_url":"http://patchwork.ozlabs.org/comment/1781611/","msgid":"<5dfb2dc4-a286-b810-3707-82d39ab07ae5@st.com>","list_archive_url":null,"date":"2017-10-06T13:01:50","subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","submitter":{"id":68429,"url":"http://patchwork.ozlabs.org/api/people/68429/","name":"Alexandre TORGUE","email":"alexandre.torgue@st.com"},"content":"Hi,\n\nOn 09/22/2017 09:31 AM, Pierre-Yves MORDRET wrote:\n> This patch adds DMAMUX support in STM32 defconfig file\n> \n> Signed-off-by: M'boumba Cedric Madianga \n> Signed-off-by: Pierre-Yves MORDRET \n> ---\n> Version history:\n> v5:\n> v4:\n> v3:\n> v2:\n> * None\n> ---\n> ---\n> arch/arm/configs/stm32_defconfig | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig\n> index 90e5c46..988f395 100644\n> --- a/arch/arm/configs/stm32_defconfig\n> +++ b/arch/arm/configs/stm32_defconfig\n> @@ -67,6 +67,7 @@ CONFIG_RTC_CLASS=y\n> CONFIG_RTC_DRV_STM32=y\n> CONFIG_DMADEVICES=y\n> CONFIG_STM32_DMA=y\n> +CONFIG_STM32_DMAMUX=y\n> CONFIG_IIO=y\n> CONFIG_STM32_ADC_CORE=y\n> CONFIG_STM32_ADC=y\n> \n\nApplied on stm32-defconfig-for-v4.15 branch.\n\nThanks\nAlex\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y7qYt0prVz9sPt\n\tfor ;\n\tSat, 7 Oct 2017 00:02:58 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752020AbdJFNC4 (ORCPT\n\t);\n\tFri, 6 Oct 2017 09:02:56 -0400","from mx08-00178001.pphosted.com ([91.207.212.93]:47263 \"EHLO\n\tmx07-00178001.pphosted.com\" rhost-flags-OK-OK-OK-FAIL)\n\tby vger.kernel.org with ESMTP id S1751989AbdJFNCy (ORCPT\n\t); Fri, 6 Oct 2017 09:02:54 -0400","from pps.filterd (m0046661.ppops.net [127.0.0.1])\n\tby mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv96Cx18R027388; Fri, 6 Oct 2017 15:02:09 +0200","from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35])\n\tby mx08-00178001.pphosted.com with ESMTP id 2da25edu0u-1\n\t(version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT);\n\tFri, 06 Oct 2017 15:02:09 +0200","from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9])\n\tby beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id D46D338;\n\tFri, 6 Oct 2017 13:02:08 +0000 (GMT)","from Webmail-eu.st.com (sfhdag3node2.st.com [10.75.127.8])\n\tby zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id ABD8325CA;\n\tFri, 6 Oct 2017 13:02:08 +0000 (GMT)","from [10.201.22.135] (10.75.127.46) by SFHDAG3NODE2.st.com\n\t(10.75.127.8) with Microsoft SMTP Server (TLS) id 15.0.1178.4;\n\tFri, 6 Oct 2017 15:02:07 +0200"],"Subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","To":"Pierre-Yves MORDRET ,\n\tVinod Koul , Rob Herring , \n\tMark Rutland ,\n\tMaxime Coquelin ,\n\tRussell King ,\n\tDan Williams ,\n\t\"M'boumba Cedric Madianga\" ,\n\tFabrice GASNIER ,\n\tHerbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay ,\n\t, ,\n\t, ","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1506065492-31478-5-git-send-email-pierre-yves.mordret@st.com>","From":"Alexandre Torgue ","Message-ID":"<5dfb2dc4-a286-b810-3707-82d39ab07ae5@st.com>","Date":"Fri, 6 Oct 2017 15:01:50 +0200","User-Agent":"Mozilla/5.0 (X11; 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