[{"id":1775226,"web_url":"http://patchwork.ozlabs.org/comment/1775226/","msgid":"<32e4d8e5-e95c-9048-26b0-4ffe2c36ff02@ti.com>","list_archive_url":null,"date":"2017-09-26T08:03:08","subject":"Re: [RESEND PATCH v5 2/4] dmaengine: Add STM32 DMAMUX driver","submitter":{"id":9142,"url":"http://patchwork.ozlabs.org/api/people/9142/","name":"Peter Ujfalusi","email":"peter.ujfalusi@ti.com"},"content":"\n\n\nTexas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki\n\nOn 2017-09-22 10:31, Pierre-Yves MORDRET wrote:\n> This patch implements the STM32 DMAMUX driver.\n> \n> The DMAMUX request multiplexer allows routing a DMA request line between\n> the peripherals and the DMA controllers of the product. The routing\n> function is ensured by a programmable multi-channel DMA request line\n> multiplexer. Each channel selects a unique DMA request line,\n> unconditionally or synchronously with events from its DMAMUX\n> synchronization inputs. The DMAMUX may also be used as a DMA request\n> generator from programmable events on its input trigger signals\n> \n> Signed-off-by: M'boumba Cedric Madianga \n> Signed-off-by: Pierre-Yves MORDRET \n\nReviewed-by: Peter Ujfalusi \n\n> ---\n> Version history:\n> v5:\n> * Set selected channel ID within a lock to avoid race condition.\n> Release if any error occurs\n> v4:\n> * Get rid of st,dmamux property and custom API between STM32\n> DMAMUX and DMA.\n> DMAMUX will read DMA masters from Device Tree from now on.\n> Merely one DMAMUX node is needed now.\n> * Only STM32 DMA are allowed to be connected onto DMAMUX\n> * channelID is computed locally within the driver and crafted in\n> dma_psec to be passed toward DMA master.\n> DMAMUX router sorts out which DMA master will serve the\n> request automatically.\n> * This version forbids the use of DMA in standalone and DMAMUX at\n> the same time : all clients need to be connected either on DMA\n> or DMAMUX ; no mix up\n> v3:\n> * change compatible to st,stm32h7-dmamux to be mode SoC specific\n> v2:\n> * Dynamic channelID allocation.\n> * Change of_property_... by device_property.\n> * New clock management.\n> * DMAMUX Configuration API.\n> ---\n> ---\n> drivers/dma/Kconfig | 9 ++\n> drivers/dma/Makefile | 1 +\n> drivers/dma/stm32-dmamux.c | 327 +++++++++++++++++++++++++++++++++++++++++++++\n> 3 files changed, 337 insertions(+)\n> create mode 100644 drivers/dma/stm32-dmamux.c\n> \n> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig\n> index fadc4d8..04e381b 100644\n> --- a/drivers/dma/Kconfig\n> +++ b/drivers/dma/Kconfig\n> @@ -483,6 +483,15 @@ config STM32_DMA\n> \t If you have a board based on such a MCU and wish to use DMA say Y\n> \t here.\n> \n> +config STM32_DMAMUX\n> +\tbool \"STMicroelectronics STM32 dma multiplexer support\"\n> +\tdepends on STM32_DMA || COMPILE_TEST\n> +\thelp\n> +\t Enable support for the on-chip DMA multiplexer on STMicroelectronics\n> +\t STM32 MCUs.\n> +\t If you have a board based on such a MCU and wish to use DMAMUX say Y\n> +\t here.\n> +\n> config S3C24XX_DMAC\n> \tbool \"Samsung S3C24XX DMA support\"\n> \tdepends on ARCH_S3C24XX || COMPILE_TEST\n> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile\n> index f08f8de..a145ad1 100644\n> --- a/drivers/dma/Makefile\n> +++ b/drivers/dma/Makefile\n> @@ -59,6 +59,7 @@ obj-$(CONFIG_RENESAS_DMA) += sh/\n> obj-$(CONFIG_SIRF_DMA) += sirf-dma.o\n> obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o\n> obj-$(CONFIG_STM32_DMA) += stm32-dma.o\n> +obj-$(CONFIG_STM32_DMAMUX) += stm32-dmamux.o\n> obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o\n> obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o\n> obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o\n> diff --git a/drivers/dma/stm32-dmamux.c b/drivers/dma/stm32-dmamux.c\n> new file mode 100644\n> index 0000000..22812e7\n> --- /dev/null\n> +++ b/drivers/dma/stm32-dmamux.c\n> @@ -0,0 +1,327 @@\n> +/*\n> + *\n> + * Copyright (C) STMicroelectronics SA 2017\n> + * Author(s): M'boumba Cedric Madianga \n> + * Pierre-Yves Mordret \n> + *\n> + * License terms: GPL V2.0.\n> + *\n> + * This program is free software; you can redistribute it and/or modify it\n> + * under the terms of the GNU General Public License version 2 as published by\n> + * the Free Software Foundation.\n> + *\n> + * This program is distributed in the hope that it will be useful, but\n> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more\n> + * details.\n> + *\n> + * DMA Router driver for STM32 DMA MUX\n> + *\n> + * Based on TI DMA Crossbar driver\n> + *\n> + */\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#define STM32_DMAMUX_CCR(x)\t\t(0x4 * (x))\n> +#define STM32_DMAMUX_MAX_DMA_REQUESTS\t32\n> +#define STM32_DMAMUX_MAX_REQUESTS\t255\n> +\n> +struct stm32_dmamux {\n> +\tu32 master;\n> +\tu32 request;\n> +\tu32 chan_id;\n> +};\n> +\n> +struct stm32_dmamux_data {\n> +\tstruct dma_router dmarouter;\n> +\tstruct clk *clk;\n> +\tstruct reset_control *rst;\n> +\tvoid __iomem *iomem;\n> +\tu32 dma_requests; /* Number of DMA requests connected to DMAMUX */\n> +\tu32 dmamux_requests; /* Number of DMA requests routed toward DMAs */\n> +\tspinlock_t lock; /* Protects register access */\n> +\tunsigned long *dma_inuse; /* Used DMA channel */\n> +\tu32 dma_reqs[]; /* Number of DMA Request per DMA masters.\n> +\t\t\t * [0] holds number of DMA Masters.\n> +\t\t\t * To be kept at very end end of this structure\n> +\t\t\t */\n> +};\n> +\n> +static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)\n> +{\n> +\treturn readl_relaxed(iomem + reg);\n> +}\n> +\n> +static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)\n> +{\n> +\twritel_relaxed(val, iomem + reg);\n> +}\n> +\n> +static void stm32_dmamux_free(struct device *dev, void *route_data)\n> +{\n> +\tstruct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);\n> +\tstruct stm32_dmamux *mux = route_data;\n> +\tunsigned long flags;\n> +\n> +\t/* Clear dma request */\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\n> +\tstm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);\n> +\tclear_bit(mux->chan_id, dmamux->dma_inuse);\n> +\n> +\tif (!IS_ERR(dmamux->clk))\n> +\t\tclk_disable(dmamux->clk);\n> +\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\n> +\tdev_dbg(dev, \"Unmapping DMAMUX(%u) to DMA%u(%u)\\n\",\n> +\t\tmux->request, mux->master, mux->chan_id);\n> +\n> +\tkfree(mux);\n> +}\n> +\n> +static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,\n> +\t\t\t\t\t struct of_dma *ofdma)\n> +{\n> +\tstruct platform_device *pdev = of_find_device_by_node(ofdma->of_node);\n> +\tstruct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);\n> +\tstruct stm32_dmamux *mux;\n> +\tu32 i, min, max;\n> +\tint ret;\n> +\tunsigned long flags;\n> +\n> +\tif (dma_spec->args_count != 3) {\n> +\t\tdev_err(&pdev->dev, \"invalid number of dma mux args\\n\");\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\tif (dma_spec->args[0] > dmamux->dmamux_requests) {\n> +\t\tdev_err(&pdev->dev, \"invalid mux request number: %d\\n\",\n> +\t\t\tdma_spec->args[0]);\n> +\t\treturn ERR_PTR(-EINVAL);\n> +\t}\n> +\n> +\tmux = kzalloc(sizeof(*mux), GFP_KERNEL);\n> +\tif (!mux)\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\tmux->chan_id = find_first_zero_bit(dmamux->dma_inuse,\n> +\t\t\t\t\t dmamux->dma_requests);\n> +\tset_bit(mux->chan_id, dmamux->dma_inuse);\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\n> +\tif (mux->chan_id == dmamux->dma_requests) {\n> +\t\tdev_err(&pdev->dev, \"Run out of free DMA requests\\n\");\n> +\t\tret = -ENOMEM;\n> +\t\tgoto error;\n> +\t}\n> +\n> +\t/* Look for DMA Master */\n> +\tfor (i = 1, min = 0, max = dmamux->dma_reqs[i];\n> +\t i <= dmamux->dma_reqs[0];\n> +\t min += dmamux->dma_reqs[i], max += dmamux->dma_reqs[++i])\n> +\t\tif (mux->chan_id < max)\n> +\t\t\tbreak;\n> +\tmux->master = i - 1;\n> +\n> +\t/* The of_node_put() will be done in of_dma_router_xlate function */\n> +\tdma_spec->np = of_parse_phandle(ofdma->of_node, \"dma-masters\", i - 1);\n> +\tif (!dma_spec->np) {\n> +\t\tdev_err(&pdev->dev, \"can't get dma master\\n\");\n> +\t\tret = -EINVAL;\n> +\t\tgoto error;\n> +\t}\n> +\n> +\t/* Set dma request */\n> +\tspin_lock_irqsave(&dmamux->lock, flags);\n> +\tif (!IS_ERR(dmamux->clk)) {\n> +\t\tret = clk_enable(dmamux->clk);\n> +\t\tif (ret < 0) {\n> +\t\t\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\t\t\tdev_err(&pdev->dev, \"clk_prep_enable issue: %d\\n\", ret);\n> +\t\t\tgoto error;\n> +\t\t}\n> +\t}\n> +\tspin_unlock_irqrestore(&dmamux->lock, flags);\n> +\n> +\tmux->request = dma_spec->args[0];\n> +\n> +\t/* craft DMA spec */\n> +\tdma_spec->args[3] = dma_spec->args[2];\n> +\tdma_spec->args[2] = dma_spec->args[1];\n> +\tdma_spec->args[1] = 0;\n> +\tdma_spec->args[0] = mux->chan_id - min;\n> +\tdma_spec->args_count = 4;\n> +\n> +\tstm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),\n> +\t\t\t mux->request);\n> +\tdev_dbg(&pdev->dev, \"Mapping DMAMUX(%u) to DMA%u(%u)\\n\",\n> +\t\tmux->request, mux->master, mux->chan_id);\n> +\n> +\treturn mux;\n> +\n> +error:\n> +\tclear_bit(mux->chan_id, dmamux->dma_inuse);\n> +\tkfree(mux);\n> +\treturn ERR_PTR(ret);\n> +}\n> +\n> +static const struct of_device_id stm32_stm32dma_master_match[] = {\n> +\t{ .compatible = \"st,stm32-dma\", },\n> +\t{},\n> +};\n> +\n> +static int stm32_dmamux_probe(struct platform_device *pdev)\n> +{\n> +\tstruct device_node *node = pdev->dev.of_node;\n> +\tconst struct of_device_id *match;\n> +\tstruct device_node *dma_node;\n> +\tstruct stm32_dmamux_data *stm32_dmamux;\n> +\tstruct resource *res;\n> +\tvoid __iomem *iomem;\n> +\tint i, count, ret;\n> +\tu32 dma_req;\n> +\n> +\tif (!node)\n> +\t\treturn -ENODEV;\n> +\n> +\tcount = device_property_read_u32_array(&pdev->dev, \"dma-masters\",\n> +\t\t\t\t\t NULL, 0);\n> +\tif (count < 0) {\n> +\t\tdev_err(&pdev->dev, \"Can't get DMA master(s) node\\n\");\n> +\t\treturn -ENODEV;\n> +\t}\n> +\n> +\tstm32_dmamux = devm_kzalloc(&pdev->dev, sizeof(*stm32_dmamux) +\n> +\t\t\t\t sizeof(u32) * (count + 1), GFP_KERNEL);\n> +\tif (!stm32_dmamux)\n> +\t\treturn -ENOMEM;\n> +\n> +\tdma_req = 0;\n> +\tfor (i = 1; i <= count; i++) {\n> +\t\tdma_node = of_parse_phandle(node, \"dma-masters\", i - 1);\n> +\n> +\t\tmatch = of_match_node(stm32_stm32dma_master_match, dma_node);\n> +\t\tif (!match) {\n> +\t\t\tdev_err(&pdev->dev, \"DMA master is not supported\\n\");\n> +\t\t\tof_node_put(dma_node);\n> +\t\t\treturn -EINVAL;\n> +\t\t}\n> +\n> +\t\tif (of_property_read_u32(dma_node, \"dma-requests\",\n> +\t\t\t\t\t &stm32_dmamux->dma_reqs[i])) {\n> +\t\t\tdev_info(&pdev->dev,\n> +\t\t\t\t \"Missing MUX output information, using %u.\\n\",\n> +\t\t\t\t STM32_DMAMUX_MAX_DMA_REQUESTS);\n> +\t\t\tstm32_dmamux->dma_reqs[i] =\n> +\t\t\t\tSTM32_DMAMUX_MAX_DMA_REQUESTS;\n> +\t\t}\n> +\t\tdma_req += stm32_dmamux->dma_reqs[i];\n> +\t\tof_node_put(dma_node);\n> +\t}\n> +\n> +\tif (dma_req > STM32_DMAMUX_MAX_DMA_REQUESTS) {\n> +\t\tdev_err(&pdev->dev, \"Too many DMA Master Requests to manage\\n\");\n> +\t\treturn -ENODEV;\n> +\t}\n> +\n> +\tstm32_dmamux->dma_requests = dma_req;\n> +\tstm32_dmamux->dma_reqs[0] = count;\n> +\tstm32_dmamux->dma_inuse = devm_kcalloc(&pdev->dev,\n> +\t\t\t\t\t BITS_TO_LONGS(dma_req),\n> +\t\t\t\t\t sizeof(unsigned long),\n> +\t\t\t\t\t GFP_KERNEL);\n> +\tif (!stm32_dmamux->dma_inuse)\n> +\t\treturn -ENOMEM;\n> +\n> +\tif (device_property_read_u32(&pdev->dev, \"dma-requests\",\n> +\t\t\t\t &stm32_dmamux->dmamux_requests)) {\n> +\t\tstm32_dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;\n> +\t\tdev_warn(&pdev->dev, \"DMAMUX defaulting on %u requests\\n\",\n> +\t\t\t stm32_dmamux->dmamux_requests);\n> +\t}\n> +\n> +\tres = platform_get_resource(pdev, IORESOURCE_MEM, 0);\n> +\tif (!res)\n> +\t\treturn -ENODEV;\n> +\n> +\tiomem = devm_ioremap_resource(&pdev->dev, res);\n> +\tif (!iomem)\n> +\t\treturn -ENOMEM;\n> +\n> +\tspin_lock_init(&stm32_dmamux->lock);\n> +\n> +\tstm32_dmamux->clk = devm_clk_get(&pdev->dev, NULL);\n> +\tif (IS_ERR(stm32_dmamux->clk)) {\n> +\t\tret = PTR_ERR(stm32_dmamux->clk);\n> +\t\tif (ret == -EPROBE_DEFER)\n> +\t\t\tdev_info(&pdev->dev, \"Missing controller clock\\n\");\n> +\t\treturn ret;\n> +\t}\n> +\n> +\tstm32_dmamux->rst = devm_reset_control_get(&pdev->dev, NULL);\n> +\tif (!IS_ERR(stm32_dmamux->rst)) {\n> +\t\treset_control_assert(stm32_dmamux->rst);\n> +\t\tudelay(2);\n> +\t\treset_control_deassert(stm32_dmamux->rst);\n> +\t}\n> +\n> +\tstm32_dmamux->iomem = iomem;\n> +\tstm32_dmamux->dmarouter.dev = &pdev->dev;\n> +\tstm32_dmamux->dmarouter.route_free = stm32_dmamux_free;\n> +\n> +\tplatform_set_drvdata(pdev, stm32_dmamux);\n> +\n> +\tif (!IS_ERR(stm32_dmamux->clk)) {\n> +\t\tret = clk_prepare_enable(stm32_dmamux->clk);\n> +\t\tif (ret < 0) {\n> +\t\t\tdev_err(&pdev->dev, \"clk_prep_enable error: %d\\n\", ret);\n> +\t\t\treturn ret;\n> +\t\t}\n> +\t}\n> +\n> +\t/* Reset the dmamux */\n> +\tfor (i = 0; i < stm32_dmamux->dma_requests; i++)\n> +\t\tstm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);\n> +\n> +\tif (!IS_ERR(stm32_dmamux->clk))\n> +\t\tclk_disable(stm32_dmamux->clk);\n> +\n> +\treturn of_dma_router_register(node, stm32_dmamux_route_allocate,\n> +\t\t\t\t &stm32_dmamux->dmarouter);\n> +}\n> +\n> +static const struct of_device_id stm32_dmamux_match[] = {\n> +\t{ .compatible = \"st,stm32h7-dmamux\" },\n> +\t{},\n> +};\n> +\n> +static struct platform_driver stm32_dmamux_driver = {\n> +\t.probe\t= stm32_dmamux_probe,\n> +\t.driver = {\n> +\t\t.name = \"stm32-dmamux\",\n> +\t\t.of_match_table = stm32_dmamux_match,\n> +\t},\n> +};\n> +\n> +static int __init stm32_dmamux_init(void)\n> +{\n> +\treturn platform_driver_register(&stm32_dmamux_driver);\n> +}\n> +arch_initcall(stm32_dmamux_init);\n> +\n> +MODULE_DESCRIPTION(\"DMA Router driver for STM32 DMA MUX\");\n> +MODULE_AUTHOR(\"M'boumba Cedric Madianga \");\n> +MODULE_AUTHOR(\"Pierre-Yves Mordret \");\n> +MODULE_LICENSE(\"GPL v2\");","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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t=1506412984;\n\tbh=WndnI4fvHcG3SklQMEui2OW70Ka6hSmELHWh9HbiAkU=;\n\th=Subject:To:References:From:Date:In-Reply-To;\n\tb=MXv9U9ol/kfTvXLMWgB31M8EYk71GhKTXsWF4vyap0pPdYXKnxA/W20TiFQcdQcsb\n\tPZRcX2+G0s5jNLAKns2sx0xXl65HHlG/iI3PvrU1c780Z0jEA4NifjLcpC7somVloC\n\thdLBCChW5F2D4ULjjrSaUR0XJqIva962B9BfiDzQ="],"Subject":"Re: [RESEND PATCH v5 2/4] dmaengine: Add STM32 DMAMUX driver","To":"Pierre-Yves MORDRET , Vinod Koul\n\t, Rob Herring , Mark Rutland\n\t, Maxime Coquelin , \n\tAlexandre Torgue , Russell King\n\t, Dan Williams ,\n\t\"M'boumba Cedric Madianga\" , Fabrice GASNIER\n\t, Herbert Xu ,\n\tFabien DESSENNE ,\n\tAmelie Delaunay , ,\n\t, , \n\t","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1506065492-31478-3-git-send-email-pierre-yves.mordret@st.com>","From":"Peter Ujfalusi ","Message-ID":"<32e4d8e5-e95c-9048-26b0-4ffe2c36ff02@ti.com>","Date":"Tue, 26 Sep 2017 11:03:08 +0300","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.8.0","MIME-Version":"1.0","In-Reply-To":"<1506065492-31478-3-git-send-email-pierre-yves.mordret@st.com>","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170926_010356_503402_6B1B108C ","X-CRM114-Status":"GOOD ( 30.11 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [198.47.19.17 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1775674,"web_url":"http://patchwork.ozlabs.org/comment/1775674/","msgid":"<20170926164603.GP30097@localhost>","list_archive_url":null,"date":"2017-09-26T16:46:03","subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Fri, Sep 22, 2017 at 09:31:32AM +0200, Pierre-Yves MORDRET wrote:\n> This patch adds DMAMUX support in STM32 defconfig file\n\nNeed ACK from ARM folks on this.\n\n> \n> Signed-off-by: M'boumba Cedric Madianga \n> Signed-off-by: Pierre-Yves MORDRET \n> ---\n> Version history:\n> v5:\n> v4:\n> v3:\n> v2:\n> * None\n> ---\n> ---\n> arch/arm/configs/stm32_defconfig | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig\n> index 90e5c46..988f395 100644\n> --- a/arch/arm/configs/stm32_defconfig\n> +++ b/arch/arm/configs/stm32_defconfig\n> @@ -67,6 +67,7 @@ CONFIG_RTC_CLASS=y\n> CONFIG_RTC_DRV_STM32=y\n> CONFIG_DMADEVICES=y\n> CONFIG_STM32_DMA=y\n> +CONFIG_STM32_DMAMUX=y\n> CONFIG_IIO=y\n> CONFIG_STM32_ADC_CORE=y\n> CONFIG_STM32_ADC=y\n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"KU3IFnHT\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y1mx02WSNz9t3B\n\tfor ;\n\tWed, 27 Sep 2017 02:43:32 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwsxE-0006Dz-B9; Tue, 26 Sep 2017 16:43:28 +0000","from mga09.intel.com ([134.134.136.24])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dwswo-0005dF-Nv for linux-arm-kernel@lists.infradead.org;\n\tTue, 26 Sep 2017 16:43:04 +0000","from orsmga004.jf.intel.com ([10.7.209.38])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Sep 2017 09:42:12 -0700","from vkoul-udesk7.iind.intel.com (HELO localhost) ([10.223.84.143])\n\tby orsmga004.jf.intel.com with ESMTP; 26 Sep 2017 09:42:05 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=HExktRdm60nT7B041uLK02D9aW89Zfw0YObCP6IY/zg=;\n\tb=KU3IFnHTUgj+22\n\t+XF2SrpTyQrWI9K+kIk/szg2WlMAh19nZWCx33c2cdWlLAQ6gcgNMgItSlBvzs4G2OKloePM/7HTx\n\tFNzNRmcfz+6psUPHH4Ss6fjwA2ej/wUXEgZQ/W6gy6Y2vpt+mqGLvIFM3c+70fFwckN10xm4LlrbV\n\tNyqllCGwsg51oMl8xK+6ZSoyBJRJJTrpuKRJZty5OZ196lGrpU9KwFW4+jSIdZS4993DMiQutwYn4\n\tRyqJ32ftDHG1p1kMhj0Ha3PLRM0IEedAlz+ChGOdSa9KcObKzUVthS+3+9zkxoXQcrXxZn88hglkF\n\t4YlbxoN5CSovfktSbbtw==;","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,441,1500966000\"; d=\"scan'208\";a=\"132513683\"","Date":"Tue, 26 Sep 2017 22:16:03 +0530","From":"Vinod Koul ","To":"Pierre-Yves MORDRET ,\n\tArnd Bergmann ","Subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","Message-ID":"<20170926164603.GP30097@localhost>","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1506065492-31478-5-git-send-email-pierre-yves.mordret@st.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<1506065492-31478-5-git-send-email-pierre-yves.mordret@st.com>","User-Agent":"Mutt/1.5.24 (2015-08-30)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170926_094302_973863_55090964 ","X-CRM114-Status":"GOOD ( 12.10 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [134.134.136.24 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[134.134.136.24 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , devicetree@vger.kernel.org,\n\tAmelie Delaunay ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\tFabien DESSENNE , \n\tlinux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n\tRob Herring ,\n\tMaxime Coquelin , \n\tM'boumba Cedric Madianga ,\n\tDan Williams ,\n\tFabrice GASNIER ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tHerbert Xu ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776070,"web_url":"http://patchwork.ozlabs.org/comment/1776070/","msgid":"","list_archive_url":null,"date":"2017-09-27T06:59:55","subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","submitter":{"id":68429,"url":"http://patchwork.ozlabs.org/api/people/68429/","name":"Alexandre TORGUE","email":"alexandre.torgue@st.com"},"content":"Hi Vinod\n\nOn 09/26/2017 06:46 PM, Vinod Koul wrote:\n> On Fri, Sep 22, 2017 at 09:31:32AM +0200, Pierre-Yves MORDRET wrote:\n>> This patch adds DMAMUX support in STM32 defconfig file\n> \n> Need ACK from ARM folks on this.\n\nI will take it in my pull request.\n\nRegards\nAlex\n> \n>>\n>> Signed-off-by: M'boumba Cedric Madianga \n>> Signed-off-by: Pierre-Yves MORDRET \n>> ---\n>> Version history:\n>> v5:\n>> v4:\n>> v3:\n>> v2:\n>> * None\n>> ---\n>> ---\n>> arch/arm/configs/stm32_defconfig | 1 +\n>> 1 file changed, 1 insertion(+)\n>>\n>> diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig\n>> index 90e5c46..988f395 100644\n>> --- a/arch/arm/configs/stm32_defconfig\n>> +++ b/arch/arm/configs/stm32_defconfig\n>> @@ -67,6 +67,7 @@ CONFIG_RTC_CLASS=y\n>> CONFIG_RTC_DRV_STM32=y\n>> CONFIG_DMADEVICES=y\n>> CONFIG_STM32_DMA=y\n>> +CONFIG_STM32_DMAMUX=y\n>> CONFIG_IIO=y\n>> CONFIG_STM32_ADC_CORE=y\n>> CONFIG_STM32_ADC=y\n>> -- \n>> 2.7.4\n>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From:\n\tReferences:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=OSXIXFk1Zmb7g3sRs/ESU8XjcWn2DFbTtsKqrOz8BGk=;\n\tb=RCFxYytoT/VGnLj/aD2ZrN/ts\n\tJpcRl0jjIdZGKtFp8GvYuAo48aeBocNXeYOikzyW4VlMox4ath7ld6iW48HuPKIaxycemzrgHFKmI\n\tNSpsFN9GjcsMWsT537JFCtGL4q2PxT9SzGHHNpVVzg59e8GEsacw5zQfrtEa1IIK3xqHLA0F0MjIw\n\tMhTrKtCzPGG3ZoWngu6+sTbNORwJj5Y1onpFKyKRbCi9Hny9vV2DY6JF3fVnV749FVpAXP7Zwo7Rj\n\t6cweWETL7kQHNX17LkUNezwdao3+WKMALvcXYB7FbaA0aaENNA8hLt2vB2mm+oj2auxX7x/llJSji\n\tKHyE40BsQ==;","Subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","To":"Vinod Koul , Pierre-Yves MORDRET\n\t, Arnd Bergmann ","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1506065492-31478-5-git-send-email-pierre-yves.mordret@st.com>\n\t<20170926164603.GP30097@localhost>","From":"Alexandre Torgue ","Message-ID":"","Date":"Wed, 27 Sep 2017 08:59:55 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170926164603.GP30097@localhost>","Content-Language":"en-US","X-Originating-IP":"[10.75.127.46]","X-ClientProxiedBy":"SFHDAG7NODE3.st.com (10.75.127.21) To SFHDAG3NODE2.st.com\n\t(10.75.127.8)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-27_02:, , signatures=0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170927_000117_124179_6116025E ","X-CRM114-Status":"GOOD ( 10.17 )","X-Spam-Score":"-2.6 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.6 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [62.209.51.94 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , devicetree@vger.kernel.org,\n\tAmelie Delaunay ,\n\tHerbert Xu ,\n\tRussell King , \n\tFabien DESSENNE , linux-kernel@vger.kernel.org,\n\tdmaengine@vger.kernel.org, Rob Herring ,\n\tMaxime Coquelin , M'boumba\n\tCedric Madianga ,\n\tDan Williams ,\n\tFabrice GASNIER ,\n\tlinux-arm-kernel@lists.infradead.org","Content-Transfer-Encoding":"7bit","Content-Type":"text/plain; charset=\"us-ascii\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776231,"web_url":"http://patchwork.ozlabs.org/comment/1776231/","msgid":"<20170927103631.GL30097@localhost>","list_archive_url":null,"date":"2017-09-27T10:36:31","subject":"Re: [RESEND PATCH v5 0/4] Add STM32 DMAMUX support","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Fri, Sep 22, 2017 at 09:31:28AM +0200, Pierre-Yves MORDRET wrote:\n> This patchset adds support for the STM32 DMA multiplexer.\n> It allows to map any peripheral DMA request to any channel of the product\n> DMAs.\n> This IP has been introduced with STM32H7 SoC.\n\nApplied first three patches, thanks\n\n> ---\n> Version history:\n> v5:\n> * Set selected channel ID within a lock to avoid race condition.\n> Release if any error occurs\n> v4:\n> * Add multi-master ability for STM32 DMAMUX\n> * Get rid of st,dmamux property and custom API between STM32\n> DMAMUX and DMA. Bindings has changed.\n> DMAMUX will read DMA masters from Device Tree from now on.\n> Merely one DMAMUX node is needed now.\n> * Only STM32 DMA are allowed to be connected onto DMAMUX\n> * channelID is computed locally within the driver and crafted in\n> dma_psec to be passed toward DMA master.\n> DMAMUX router sorts out which DMA master will serve the\n> request automatically.\n> * This version forbids the use of DMA in standalone and DMAMUX at\n> the same time : all clients need to be connected either on DMA\n> or DMAMUX ; no mix up\n> v3:\n> * change compatible to st,stm32h7-dmamux to be mode Soc specific\n> * add verbosity in dma-cells\n> ---\n> \n> Pierre-Yves MORDRET (4):\n> dt-bindings: Document the STM32 DMAMUX bindings\n> dmaengine: Add STM32 DMAMUX driver\n> dt-bindings: stm32-dma: add a property to handle STM32 DMAMUX\n> ARM: configs: stm32: Add DMAMUX support in STM32 defconfig\n> \n> .../devicetree/bindings/dma/stm32-dma.txt | 4 +-\n> .../devicetree/bindings/dma/stm32-dmamux.txt | 84 ++++++\n> arch/arm/configs/stm32_defconfig | 1 +\n> drivers/dma/Kconfig | 9 +\n> drivers/dma/Makefile | 1 +\n> drivers/dma/stm32-dmamux.c | 327 +++++++++++++++++++++\n> 6 files changed, 425 insertions(+), 1 deletion(-)\n> create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt\n> create mode 100644 drivers/dma/stm32-dmamux.c\n> \n> -- \n> 2.7.4\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776232,"web_url":"http://patchwork.ozlabs.org/comment/1776232/","msgid":"<20170927103655.GM30097@localhost>","list_archive_url":null,"date":"2017-09-27T10:36:55","subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Wed, Sep 27, 2017 at 08:59:55AM +0200, Alexandre Torgue wrote:\n> Hi Vinod\n> \n> On 09/26/2017 06:46 PM, Vinod Koul wrote:\n> >On Fri, Sep 22, 2017 at 09:31:32AM +0200, Pierre-Yves MORDRET wrote:\n> >>This patch adds DMAMUX support in STM32 defconfig file\n> >\n> >Need ACK from ARM folks on this.\n> \n> I will take it in my pull request.\n\nsure, other are applied now","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Gnqg8x1V\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2Dgf3HsNz9tXQ\n\tfor ;\n\tWed, 27 Sep 2017 20:33:34 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dx9ek-0006Nd-M1; Wed, 27 Sep 2017 10:33:30 +0000","from mga11.intel.com ([192.55.52.93])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dx9ec-00064I-3R for linux-arm-kernel@lists.infradead.org;\n\tWed, 27 Sep 2017 10:33:29 +0000","from fmsmga005.fm.intel.com ([10.253.24.32])\n\tby fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Sep 2017 03:33:01 -0700","from vkoul-udesk7.iind.intel.com (HELO localhost) ([10.223.84.143])\n\tby fmsmga005.fm.intel.com with ESMTP; 27 Sep 2017 03:32:57 -0700"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=g/xGfnKMBfH/RJlfEbUgPyQcTSnl1qppy8CFZCAfr1E=;\n\tb=Gnqg8x1VecC8P9\n\tHQHWuuTBGF3M0vI2+9QNzW+cK+OKfv14gKi0rk2k1hfPn/GG0NzTOIkg72cv8PN53tjQXr+pdsAYD\n\tj41FfMPuEfwPOGbxLgNwaWCAZlLo8b0MjOK2cm4xMhoxmgVZwvc2OOhvjtYF5Bw2l1E1F1bEDO/E5\n\teYcbJU3pHqrpksUAu9jX+4wVzsdrSbPuZ5uInkL/lZRIix4oD7gKqqZK17qJoD92UtLF2HGaUQ2b8\n\ts2lOnWNC+WHLoEdylBYNmq5RO3uCBByzxhzuEke2HbvETb5iZX1G9Nd4zFeCo1fAzBDiWjewF7yJK\n\tO1nK7WwqgN5gwGT4JRrA==;","X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,444,1500966000\"; d=\"scan'208\";a=\"156076466\"","Date":"Wed, 27 Sep 2017 16:06:55 +0530","From":"Vinod Koul ","To":"Alexandre Torgue ","Subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","Message-ID":"<20170927103655.GM30097@localhost>","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<1506065492-31478-5-git-send-email-pierre-yves.mordret@st.com>\n\t<20170926164603.GP30097@localhost>\n\t","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.5.24 (2015-08-30)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170927_033322_346920_95258131 ","X-CRM114-Status":"UNSURE ( 9.65 )","X-CRM114-Notice":"Please train this message.","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [192.55.52.93 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , devicetree@vger.kernel.org,\n\tAmelie Delaunay ,\n\tHerbert Xu , Arnd Bergmann , \n\tRussell King ,\n\tPierre-Yves MORDRET ,\n\tlinux-kernel@vger.kernel.org, \n\tdmaengine@vger.kernel.org, Rob Herring ,\n\tFabien DESSENNE ,\n\tMaxime Coquelin ,\n\tM'boumba Cedric Madianga ,\n\tDan Williams ,\n\tFabrice GASNIER ,\n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776302,"web_url":"http://patchwork.ozlabs.org/comment/1776302/","msgid":"<3bda21bc-26e9-cc15-7227-8ed1523ab4fa@st.com>","list_archive_url":null,"date":"2017-09-27T12:31:03","subject":"Re: [RESEND PATCH v5 0/4] Add STM32 DMAMUX support","submitter":{"id":71499,"url":"http://patchwork.ozlabs.org/api/people/71499/","name":"Pierre Yves MORDRET","email":"pierre-yves.mordret@st.com"},"content":"Thanks Vinod.\nThe fourth is going to be managed by ARM team.\n\nRegards\n\nOn 09/27/2017 12:36 PM, Vinod Koul wrote:\n> On Fri, Sep 22, 2017 at 09:31:28AM +0200, Pierre-Yves MORDRET wrote:\n>> This patchset adds support for the STM32 DMA multiplexer.\n>> It allows to map any peripheral DMA request to any channel of the product\n>> DMAs.\n>> This IP has been introduced with STM32H7 SoC.\n> \n> Applied first three patches, thanks\n> \n>> ---\n>> Version history:\n>> v5:\n>> * Set selected channel ID within a lock to avoid race condition.\n>> Release if any error occurs\n>> v4:\n>> * Add multi-master ability for STM32 DMAMUX\n>> * Get rid of st,dmamux property and custom API between STM32\n>> DMAMUX and DMA. Bindings has changed.\n>> DMAMUX will read DMA masters from Device Tree from now on.\n>> Merely one DMAMUX node is needed now.\n>> * Only STM32 DMA are allowed to be connected onto DMAMUX\n>> * channelID is computed locally within the driver and crafted in\n>> dma_psec to be passed toward DMA master.\n>> DMAMUX router sorts out which DMA master will serve the\n>> request automatically.\n>> * This version forbids the use of DMA in standalone and DMAMUX at\n>> the same time : all clients need to be connected either on DMA\n>> or DMAMUX ; no mix up\n>> v3:\n>> * change compatible to st,stm32h7-dmamux to be mode Soc specific\n>> * add verbosity in dma-cells\n>> ---\n>>\n>> Pierre-Yves MORDRET (4):\n>> dt-bindings: Document the STM32 DMAMUX bindings\n>> dmaengine: Add STM32 DMAMUX driver\n>> dt-bindings: stm32-dma: add a property to handle STM32 DMAMUX\n>> ARM: configs: stm32: Add DMAMUX support in STM32 defconfig\n>>\n>> .../devicetree/bindings/dma/stm32-dma.txt | 4 +-\n>> .../devicetree/bindings/dma/stm32-dmamux.txt | 84 ++++++\n>> arch/arm/configs/stm32_defconfig | 1 +\n>> drivers/dma/Kconfig | 9 +\n>> drivers/dma/Makefile | 1 +\n>> drivers/dma/stm32-dmamux.c | 327 +++++++++++++++++++++\n>> 6 files changed, 425 insertions(+), 1 deletion(-)\n>> create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt\n>> create mode 100644 drivers/dma/stm32-dmamux.c\n>>\n>> -- \n>> 2.7.4\n>>\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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bh=KGwRGEvaoz3M4gfPtQIxZS+Myr7q6if0rd2mnqI4+0U=;\n\tb=sANBNueb7dowZA\n\tJ3zVfAfloOhHKsy4UmVI95LjE23bSy3btSj+1/nHJLuqTQkn1PcDEQAC5wlPrKUyu18EZLUE7iNwh\n\tIvbZPUT3iKgSB/UMteXYTo2aefOeItqcND/hEFS2SqM7LdKBAerati0Z+JCJErmPUmAJQzxDlpOnd\n\tdkPYedlv4FCeKaniMVrFBgorqFIlGUfr3g3nyoEJL9UTlgiY7Jx8c8LCLWnwDZwvfo/UdkU84nRk9\n\tZBS0kyvPZpnOtvlqYCUVZXZplGcEJ12MFYRT8r05Xf6yLsq+Vf6VFt2Si0cerhqpIA/LdM/yIjaDy\n\tfrRO9UKUjgeyTFQUT5eQ==;","Subject":"Re: [RESEND PATCH v5 0/4] Add STM32 DMAMUX support","To":"Vinod Koul ","References":"<1506065492-31478-1-git-send-email-pierre-yves.mordret@st.com>\n\t<20170927103631.GL30097@localhost>","From":"Pierre Yves MORDRET ","Message-ID":"<3bda21bc-26e9-cc15-7227-8ed1523ab4fa@st.com>","Date":"Wed, 27 Sep 2017 14:31:03 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170927103631.GL30097@localhost>","Content-Language":"en-US","X-Originating-IP":"[10.75.127.44]","X-ClientProxiedBy":"SFHDAG3NODE1.st.com (10.75.127.7) To SFHDAG5NODE2.st.com\n\t(10.75.127.14)","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-09-27_03:, , signatures=0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170927_053156_599425_12A77F92 ","X-CRM114-Status":"GOOD ( 12.93 )","X-Spam-Score":"-2.6 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.6 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [62.209.51.94 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Mark Rutland , devicetree@vger.kernel.org,\n\tAmelie Delaunay ,\n\tAlexandre Torgue ,\n\tRussell King ,\n\tFabien DESSENNE , \n\tlinux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,\n\tRob Herring ,\n\tMaxime Coquelin , \n\tM'boumba Cedric Madianga ,\n\tDan Williams ,\n\tFabrice GASNIER ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tHerbert Xu ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1781632,"web_url":"http://patchwork.ozlabs.org/comment/1781632/","msgid":"<5dfb2dc4-a286-b810-3707-82d39ab07ae5@st.com>","list_archive_url":null,"date":"2017-10-06T13:01:50","subject":"Re: [RESEND PATCH v5 4/4] ARM: configs: stm32: Add DMAMUX support in\n\tSTM32 defconfig","submitter":{"id":68429,"url":"http://patchwork.ozlabs.org/api/people/68429/","name":"Alexandre TORGUE","email":"alexandre.torgue@st.com"},"content":"Hi,\n\nOn 09/22/2017 09:31 AM, Pierre-Yves MORDRET wrote:\n> This patch adds DMAMUX support in STM32 defconfig file\n> \n> Signed-off-by: M'boumba Cedric Madianga \n> Signed-off-by: Pierre-Yves MORDRET \n> ---\n> Version history:\n> v5:\n> v4:\n> v3:\n> v2:\n> * None\n> ---\n> ---\n> arch/arm/configs/stm32_defconfig | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig\n> index 90e5c46..988f395 100644\n> --- a/arch/arm/configs/stm32_defconfig\n> +++ b/arch/arm/configs/stm32_defconfig\n> @@ -67,6 +67,7 @@ CONFIG_RTC_CLASS=y\n> CONFIG_RTC_DRV_STM32=y\n> CONFIG_DMADEVICES=y\n> CONFIG_STM32_DMA=y\n> +CONFIG_STM32_DMAMUX=y\n> CONFIG_IIO=y\n> CONFIG_STM32_ADC_CORE=y\n> CONFIG_STM32_ADC=y\n> \n\nApplied on stm32-defconfig-for-v4.15 branch.\n\nThanks\nAlex","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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