[{"id":1774398,"web_url":"http://patchwork.ozlabs.org/comment/1774398/","msgid":"<1506310811.30138.15.camel@aj.id.au>","list_archive_url":null,"date":"2017-09-25T03:40:11","subject":"Re: [PATCH v2 1/5] clk: Add clock driver for ASPEED BMC SoCs","submitter":{"id":68332,"url":"http://patchwork.ozlabs.org/api/people/68332/","name":"Andrew Jeffery","email":"andrew@aj.id.au"},"content":"On Thu, 2017-09-21 at 13:56 +0930, Joel Stanley wrote:\n> This adds the stub of a driver for the ASPEED SoCs. The clocks are\n> defined and the static registration is set up.\n> \n> Signed-off-by: Joel Stanley \n> ---\n>  drivers/clk/Kconfig                      |  12 +++\n>  drivers/clk/Makefile                     |   1 +\n>  drivers/clk/clk-aspeed.c                 | 162 +++++++++++++++++++++++++++++++\n>  include/dt-bindings/clock/aspeed-clock.h |  43 ++++++++\n>  4 files changed, 218 insertions(+)\n>  create mode 100644 drivers/clk/clk-aspeed.c\n>  create mode 100644 include/dt-bindings/clock/aspeed-clock.h\n> \n> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig\n> index 1c4e1aa6767e..9abe063ef8d2 100644\n> --- a/drivers/clk/Kconfig\n> +++ b/drivers/clk/Kconfig\n> @@ -142,6 +142,18 @@ config COMMON_CLK_GEMINI\n>  \t  This driver supports the SoC clocks on the Cortina Systems Gemini\n>  \t  platform, also known as SL3516 or CS3516.\n>  \n> +config COMMON_CLK_ASPEED\n> +\tbool \"Clock driver for Aspeed BMC SoCs\"\n> +\tdepends on ARCH_ASPEED || COMPILE_TEST\n> +\tdefault ARCH_ASPEED\n> +\tselect MFD_SYSCON\n> +\tselect RESET_CONTROLLER\n> +\t---help---\n> +\t  This driver supports the SoC clocks on the Aspeed BMC platforms.\n>\n> +\t  The G4 and G5 series, including the ast2400 and ast2500, are supported\n> +\t  by this driver.\n> +\n>  config COMMON_CLK_S2MPS11\n>  \ttristate \"Clock driver for S2MPS1X/S5M8767 MFD\"\n>  \tdepends on MFD_SEC_CORE || COMPILE_TEST\n> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\n> index c99f363826f0..575c68919d9b 100644\n> --- a/drivers/clk/Makefile\n> +++ b/drivers/clk/Makefile\n> @@ -26,6 +26,7 @@ obj-$(CONFIG_ARCH_CLPS711X)\t\t+= clk-clps711x.o\n>  obj-$(CONFIG_COMMON_CLK_CS2000_CP)\t+= clk-cs2000-cp.o\n>  obj-$(CONFIG_ARCH_EFM32)\t\t+= clk-efm32gg.o\n>  obj-$(CONFIG_COMMON_CLK_GEMINI)\t\t+= clk-gemini.o\n> +obj-$(CONFIG_COMMON_CLK_ASPEED)\t\t+= clk-aspeed.o\n>  obj-$(CONFIG_ARCH_HIGHBANK)\t\t+= clk-highbank.o\n>  obj-$(CONFIG_CLK_HSDK)\t\t\t+= clk-hsdk-pll.o\n>  obj-$(CONFIG_COMMON_CLK_MAX77686)\t+= clk-max77686.o\n> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c\n> new file mode 100644\n> index 000000000000..824c54767009\n> --- /dev/null\n> +++ b/drivers/clk/clk-aspeed.c\n> @@ -0,0 +1,162 @@\n> +/*\n> + * Copyright 2017 IBM Corporation\n> + *\n> + * Joel Stanley \n> + *\n> + * This program is free software; you can redistribute it and/or\n> + * modify it under the terms of the GNU General Public License\n> + * as published by the Free Software Foundation; either version\n> + * 2 of the License, or (at your option) any later version.\n> + */\n> +\n> +#define pr_fmt(fmt) \"clk-aspeed: \" fmt\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +\n> +#include \n> +\n> +#define ASPEED_RESET_CTRL\t0x04\n> +#define ASPEED_CLK_SELECTION\t0x08\n> +#define ASPEED_CLK_STOP_CTRL\t0x0c\n> +#define ASPEED_MPLL_PARAM\t0x20\n> +#define ASPEED_HPLL_PARAM\t0x24\n> +#define ASPEED_MISC_CTRL\t0x2c\n> +#define ASPEED_STRAP\t\t0x70\n> +\n> +/* Keeps track of all clocks */\n> +static struct clk_hw_onecell_data *aspeed_clk_data;\n> +\n> +static void __iomem *scu_base;\n> +\n> +/**\n> + * struct aspeed_gate_data - Aspeed gated clocks\n> + * @clock_idx: bit used to gate this clock in the clock register\n> + * @reset_idx: bit used to reset this IP in the reset register. -1 if no\n> + *             reset is required when enabling the clock\n> + * @name: the clock name\n> + * @parent_name: the name of the parent clock\n> + * @flags: standard clock framework flags\n> + */\n> +struct aspeed_gate_data {\n> +\tu8\t\tclock_idx;\n> +\ts8\t\treset_idx;\n> +\tconst char\t*name;\n> +\tconst char\t*parent_name;\n> +\tunsigned long\tflags;\n> +};\n> +\n> +/**\n> + * struct aspeed_clk_gate - Aspeed specific clk_gate structure\n> + * @hw:\t\thandle between common and hardware-specific interfaces\n> + * @reg:\tregister controlling gate\n> + * @clock_idx:\tbit used to gate this clock in the clock register\n> + * @reset_idx:\tbit used to reset this IP in the reset register. -1 if no\n> + *\t\treset is required when enabling the clock\n> + * @flags:\thardware-specific flags\n> + * @lock:\tregister lock\n> + *\n> + * Some of the clocks in the Aspeed SoC must be put in reset before enabling.\n> + * This modified version of clk_gate allows an optional reset bit to be\n> + * specified.\n> + */\n> +struct aspeed_clk_gate {\n> +\tstruct clk_hw\thw;\n> +\tstruct regmap\t*map;\n> +\tu8\t\tclock_idx;\n> +\ts8\t\treset_idx;\n> +\tu8\t\tflags;\n> +\tspinlock_t\t*lock;\n> +};\n\nIt feels like the two structures could be unified, but the result turns into a\nbit of a mess with a union of structs to limit the space impact, so perhaps we\nshouldn't go there?\n\n> +\n> +#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)\n> +\n> +/* TODO: ask Aspeed about the actual parent data */\n> +static const struct aspeed_gate_data aspeed_gates[] __initconst = {\n> +/*\t clk rst   name\t\t\tparent\t\tflags\t*/\n> +\t{  0, -1, \"eclk-gate\",\t\t\"eclk\",\t\t0 }, /* Video Engine */\n> +\t{  1,  7, \"gclk-gate\",\t\tNULL,\t\t0 }, /* 2D engine */\n> +\t{  2, -1, \"mclk-gate\",\t\t\"mpll\",\t\tCLK_IS_CRITICAL }, /* SDRAM */\n> +\t{  3,  6, \"vclk-gate\",\t\tNULL,\t\t0 }, /* Video Capture */\n> +\t{  4, 10, \"bclk-gate\",\t\t\"bclk\",\t\t0 }, /* PCIe/PCI */\n> +\t{  5, -1, \"dclk-gate\",\t\tNULL,\t\t0 }, /* DAC */\n> +\t{  6, -1, \"refclk-gate\",\t\"clkin\",\tCLK_IS_CRITICAL },\n> +\t{  7,  3, \"usb-port2-gate\",\tNULL,\t\t0 }, /* USB2.0 Host port 2 */\n> +\t{  8,  5, \"lclk-gate\",\t\tNULL,\t\t0 }, /* LPC */\n> +\t{  9, 15, \"usb-uhci-gate\",\tNULL,\t\t0 }, /* USB1.1 (requires port 2 enabled) */\n> +\t{ 10, 13, \"d1clk-gate\",\t\tNULL,\t\t0 }, /* GFX CRT */\n\nIs there a typo in the AST2400 datasheet? It claims bit 10 is \"D2CLK\".\n\n> +\t/* 11: reserved */\n> +\t/* 12: reserved */\n> +\t{ 13, 4,  \"yclk-gate\",\t\tNULL,\t\t0 }, /* HAC */\n> +\t{ 14, 14, \"usb-port1-gate\",\tNULL,\t\t0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */\n> +\t{ 15, -1, \"uart1clk-gate\",\t\"uart\",\t\t0 }, /* UART1 */\n> +\t{ 16, -1, \"uart2clk-gate\",\t\"uart\",\t\t0 }, /* UART2 */\n> +\t{ 17, -1, \"uart5clk-gate\",\t\"uart\",\t\t0 }, /* UART5 */\n> +\t/* 18: reserved */\n> +\t{ 19, -1, \"espiclk-gate\",\tNULL,\t\t0 }, /* eSPI */\n\n19 is reserved on the AST2400, and must be kept at '1'.\n\n> +\t{ 20, 11, \"mac1clk-gate\",\t\"clkin\",\t0 }, /* MAC1 */\n> +\t{ 21, 12, \"mac2clk-gate\",\t\"clkin\",\t0 }, /* MAC2 */\n> +\t/* 22: reserved */\n> +\t/* 23: reserved */\n> +\t{ 24, -1, \"rsaclk-gate\",\tNULL,\t\t0 }, /* RSA */\n> +\t{ 25, -1, \"uart3clk-gate\",\t\"uart\",\t\t0 }, /* UART3 */\n> +\t{ 26, -1, \"uart4clk-gate\",\t\"uart\",\t\t0 }, /* UART4 */\n> +\t{ 27, 16, \"sdclk-gate\",\t\tNULL,\t\t0 }, /* SDIO/SD */\n> +\t{ 28, -1, \"lhclk-gate\",\t\t\"lhclk\",\t0 }, /* LPC master/LPC+ */\n> +\t/* 29: reserved */\n> +\t/* 30: reserved */\n> +\t/* 31: reserved */\n\nInterestingly bits 29-30 are reserved in both the AST2400 and AST2500\ndatasheets, but are reserved-clear in the AST2400 datasheet and reserved-set in\nthe AST2500 datasheet. This may affect how we write register.\n\nSeparately, at one point I mistook the clk column for the index the entry\nshould appear at, which isn't the case. Do you think designated intializers\nmight help?\n\n> +};\n> +\n> +static void __init aspeed_cc_init(struct device_node *np)\n> +{\n> +\tstruct regmap *map;\n> +\tu32 val;\n> +\tint ret;\n> +\tint i;\n>\n> +\tscu_base = of_iomap(np, 0);\n> +\tif (IS_ERR(scu_base))\n> +\t\treturn;\n> +\n> +\taspeed_clk_data = kzalloc(sizeof(*aspeed_clk_data) +\n> +\t\t\tsizeof(*aspeed_clk_data->hws) * ASPEED_NUM_CLKS,\n> +\t\t\tGFP_KERNEL);\n> +\tif (!aspeed_clk_data)\n> +\t\treturn;\n> +\n> +\t/*\n> +\t * This way all clock fetched before the platform device probes,\n\nTypo: \"clocks\"\n\n> +\t * except those we assign here for early use, will be deferred.\n> +\t */\n> +\tfor (i = 0; i < ASPEED_NUM_CLKS; i++)\n> +\t\taspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);\n> +\n> +\tmap = syscon_node_to_regmap(np);\n> +\tif (IS_ERR(map)) {\n> +\t\tpr_err(\"no syscon regmap\\n\");\n> +\t\treturn;\n> +\t}\n> +\t/*\n> +\t * We check that the regmap works on this very first access,\n> +\t * but as this is an MMIO-backed regmap, subsequent regmap\n> +\t * access is not going to fail and we skip error checks from\n> +\t * this point.\n> +\t */\n> +\tret = regmap_read(map, ASPEED_STRAP, &val);\n> +\tif (ret) {\n> +\t\tpr_err(\"failed to read strapping register\\n\");\n> +\t\treturn;\n> +\t}\n> +\n> +\taspeed_clk_data->num = ASPEED_NUM_CLKS;\n> +\tret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);\n> +\tif (ret)\n> +\t\tpr_err(\"failed to add DT provider: %d\\n\", ret);\n> +};\n> +CLK_OF_DECLARE_DRIVER(aspeed_cc_g5, \"aspeed,ast2500-scu\", aspeed_cc_init);\n> +CLK_OF_DECLARE_DRIVER(aspeed_cc_g4, \"aspeed,ast2400-scu\", aspeed_cc_init);\n> diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h\n> new file mode 100644\n> index 000000000000..afe06b77562d\n> --- /dev/null\n> +++ b/include/dt-bindings/clock/aspeed-clock.h\n> @@ -0,0 +1,43 @@\n> +#ifndef DT_BINDINGS_ASPEED_CLOCK_H\n> +#define DT_BINDINGS_ASPEED_CLOCK_H\n> +\n> +#define ASPEED_NUM_CLKS\t34\n\nThis is a bit of a nit pick: Do the constants below represent all the\nclocks in the SoC(s)? Maybe if not it's better to define\nASPEED_NUM_CLKS in terms of (n + ASPEED_CLK_GATES) at the bottom - that\nway when a clock or gate is added ASPEED_NUM_CLKS has better locality and\nbetter visual progression in context.\n\nAs a note, and as a clk noob but as someone with access to the Aspeed\ndatasheet, I was wondering whether the clocks and gates need to be represented\nin the same number space. However it seems to be so by how it's used with\nrespect to struct clk_hw_onecell_data.\n\n> +\n> +#define ASPEED_CLK_HPLL\t\t\t0\n> +#define ASPEED_CLK_AHB\t\t\t1\n> +#define ASPEED_CLK_APB\t\t\t2\n> +#define ASPEED_CLK_UART\t\t\t3\n> +#define ASPEED_CLK_SDIO\t\t\t4\n> +#define ASPEED_CLK_ECLK\t\t\t5\n> +#define ASPEED_CLK_ECLK_MUX\t\t6\n> +#define ASPEED_CLK_LHCLK\t\t7\n> +#define ASPEED_CLK_MAC\t\t\t8\n> +#define ASPEED_CLK_BCLK\t\t\t9\n> +#define ASPEED_CLK_MPLL\t\t\t10\n> +#define ASPEED_CLK_GATES\t\t11\n> +#define ASPEED_CLK_GATE_ECLK\t\t(0 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_GCLK\t\t(1 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_MCLK\t\t(2 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_VCLK\t\t(3 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_BCLK\t\t(4 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_DCLK\t\t(5 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_REFCLK\t\t(6 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_USBPORT2CLK\t(7 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_LCLK\t\t(8 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_USBUHCICLK\t(9 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_D1CLK\t\t(10 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_YCLK\t\t(11 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_USBPORT1CLK\t(12 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_UART1CLK\t(13 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_UART2CLK\t(14 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_UART5CLK\t(15 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_ESPICLK\t\t(16 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_MAC1CLK\t\t(17 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_MAC2CLK\t\t(18 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_RSACLK\t\t(19 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_UART3CLK\t(20 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_UART4CLK\t(21 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_SDCLKCLK\t(22 + ASPEED_CLK_GATES)\n> +#define ASPEED_CLK_GATE_LHCCLK\t\t(23 + ASPEED_CLK_GATES)\n\nLooks like there's an off-by-one error here: ASPEED_NUM_CLKS should be (23 +\nASPEED_CLK_GATES + 1) = 35.\n\nCheers,\n\nAndrew\n\n> +\n> +#endif","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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those which are required to calculate\n> the rate of the timer periperhal so the system can load a clocksource\n> driver.\n> \n> Signed-off-by: Joel Stanley \n> ---\n>  drivers/clk/clk-aspeed.c | 152 ++++++++++++++++++++++++++++++++++++++++++++++-\n>  1 file changed, 149 insertions(+), 3 deletions(-)\n> \n> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c\n> index 824c54767009..e614c61b82d2 100644\n> --- a/drivers/clk/clk-aspeed.c\n> +++ b/drivers/clk/clk-aspeed.c\n> @@ -11,12 +11,12 @@\n>  \n>  #define pr_fmt(fmt) \"clk-aspeed: \" fmt\n>  \n> -#include \n> -#include \n>  #include \n> +#include \n> +#include \n>  #include \n> +#include \n>  #include \n> -#include \n>  \n>  #include \n>  \n> @@ -28,6 +28,9 @@\n>  #define ASPEED_MISC_CTRL\t0x2c\n>  #define ASPEED_STRAP\t\t0x70\n>  \n> +/* Globally visible clocks */\n> +static DEFINE_SPINLOCK(aspeed_clk_lock);\n> +\n>  /* Keeps track of all clocks */\n>  static struct clk_hw_onecell_data *aspeed_clk_data;\n>  \n> @@ -112,9 +115,137 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = {\n>  \t/* 31: reserved */\n>  };\n>  \n> +static const struct clk_div_table ast2400_div_table[] = {\n> +\t{ 0x0, 2 },\n> +\t{ 0x1, 4 },\n> +\t{ 0x2, 6 },\n> +\t{ 0x3, 8 },\n> +\t{ 0x4, 10 },\n> +\t{ 0x5, 12 },\n> +\t{ 0x6, 14 },\n> +\t{ 0x7, 16 },\n> +\t{ 0 }\n> +};\n> +\n> +static const struct clk_div_table ast2500_div_table[] = {\n> +\t{ 0x0, 4 },\n> +\t{ 0x1, 8 },\n> +\t{ 0x2, 12 },\n> +\t{ 0x3, 16 },\n> +\t{ 0x4, 20 },\n> +\t{ 0x5, 24 },\n> +\t{ 0x6, 28 },\n> +\t{ 0x7, 32 },\n> +\t{ 0 }\n> +};\n\nast2500_div_table is unused?\n\n> +\n> +static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n> +{\n> +\tunsigned int mult, div;\n> +\n> +\tif (val & BIT(20)) {\n> +\t\t/* Pass through mode */\n> +\t\tmult = div = 1;\n> +\t} else {\n> +\t\t/* F = clkin * [(M+1) / (N+1)] / (P + 1) */\n> +\t\tu32 p = (val >> 13) & 0x3f;\n> +\t\tu32 m = (val >> 5) & 0xff;\n> +\t\tu32 n = val & 0x1f;\n> +\n> +\t\tmult = (m + 1) / (n + 1);\n> +\t\tdiv = p + 1;\n> +\t}\n> +\n> +\treturn clk_hw_register_fixed_factor(NULL, name, \"clkin\", 0,\n> +\t\t\tmult, div);\n> +}\n> +\n> +static void __init aspeed_ast2400_cc(struct regmap *map)\n> +{\n> +\tstruct clk_hw *hw;\n> +\tu32 val, div, mult;\n> +\n> +\t/*\n> +\t * High-speed PLL clock derived from the crystal. This the CPU clock,\n> +\t * and we assume that it is enabled\n> +\t */\n> +\tregmap_read(map, ASPEED_HPLL_PARAM, &val);\n> +\tWARN(val & BIT(18), \"clock is strapped not configured\");\n\nI don't quite understand the intent of the warning - are we just trying to say\nthat the defaults have been assumed and they may not match reality? It's\nprobably not a great idea to not strap the board properly, but you could get\naway with it for a given configuration (Numerator = 20, H-PLL Output Divider\nset, H-PLL denominator = 1)\n\n> +\tif (val & BIT(17)) {\n> +\t\t/* Pass through mode */\n> +\t\tmult = div = 1;\n> +\t} else {\n> +\t\t/* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */\n> +\t\tu32 n = (val >> 5) & 0x3f;\n> +\t\tu32 od = (val >> 4) & 0x1;\n> +\t\tu32 d = val & 0xf;\n> +\n> +\t\tmult = (2 - od) * (n + 2);\n> +\t\tdiv = d + 1;\n> +\t}\n> +\thw = clk_hw_register_fixed_factor(NULL, \"hpll\", \"clkin\", 0, mult, div);\n> +\taspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw;\n> +\n> +\t/*\n> +\t * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)\n> +\t *   00: Select CPU:AHB = 1:1\n> +\t *   01: Select CPU:AHB = 2:1\n> +\t *   10: Select CPU:AHB = 4:1\n> +\t *   11: Select CPU:AHB = 3:1\n> +\t */\n> +\tregmap_read(map, ASPEED_STRAP, &val);\n> +\tval = (val >> 10) & 0x3;\n\nHow do the calculations below line up with the comment above? I can't see the\nconnection and I feel like I've missed something.\n\n> +\tdiv = val + 1;\n\nThis is only a valid mapping for 0b00 and 0b01?\n\n> +\tif (div == 2)\n> +\t\tdiv = 3;\n\nIf (div == 2) after adding 1, then the original value was 0b01, and so div\nshould remain 2?\n\n> +\telse if (div == 3)\n> +\t\tdiv = 2;\n\nIf (div == 3) after adding 1, then the original value was 0b10, and so div\nshould be 4?\n\n> +\thw = clk_hw_register_fixed_factor(NULL, \"ahb\", \"hpll\", 0, 1, div);\n> +\taspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;\n> +\n> +\t/* APB clock clock selection register SCU08 (aka PCLK) */\n> +\thw = clk_hw_register_divider_table(NULL, \"apb\", \"hpll\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 23, 3, 0,\n> +\t\t\tast2400_div_table,\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_APB] = hw;\n> +}\n> +\n> +static void __init aspeed_ast2500_cc(struct regmap *map)\n> +{\n> +\tstruct clk_hw *hw;\n> +\tu32 val, div;\n> +\n> +\t/*\n> +\t * High-speed PLL clock derived from the crystal. This the CPU clock,\n> +\t * and we assume that it is enabled\n> +\t */\n> +\tregmap_read(map, ASPEED_HPLL_PARAM, &val);\n> +\taspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_calc_pll(\"hpll\", val);\n\nWhy did you extract the aspeed_calc_pll() implementation for the ast2500 but\nnot the ast2400?\n\n> +\n> +\t/* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/\n> +\tregmap_read(map, ASPEED_STRAP, &val);\n> +\tval = (val >> 9) & 0x7;\n> +\tWARN_ON(val == 0);\n\nMaybe WARN() would be better here to explain what's going wrong (zero is an\nundefined value)?\n\n> +\tdiv = 2 * (val + 1);\n> +\thw = clk_hw_register_fixed_factor(NULL, \"ahb\", \"hpll\", 0, 1, div);\n> +\taspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;\n> +\n> +\t/* APB clock clock selection register SCU08 (aka PCLK) */\n> +\t/* TODO: this is wrong! */\n\nWhy is this wrong?\n\n> +\tregmap_read(map, ASPEED_CLK_SELECTION, &val);\n> +\tval = (val >> 23) & 0x7;\n> +\tdiv = 4 * (val + 1);\n> +\thw = clk_hw_register_fixed_factor(NULL, \"apb\", \"hpll\", 0, 1, div);\n> +\taspeed_clk_data->hws[ASPEED_CLK_APB] = hw;\n> +};\n> +\n> +\n>  static void __init aspeed_cc_init(struct device_node *np)\n>  {\n>  \tstruct regmap *map;\n> +\tunsigned long freq;\n> +\tstruct clk_hw *hw;\n>  \tu32 val;\n>  \tint ret;\n>  \tint i;\n> @@ -153,6 +284,21 @@ static void __init aspeed_cc_init(struct device_node *np)\n>  \t\treturn;\n>  \t}\n>  \n> +\t/* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */\n> +\tif (val & BIT(23))\n> +\t\tfreq = 25000000;\n> +\telse\n> +\t\tfreq = 24000000;\n\nThis isn't true on the AST2400, where CLKIN could be 24 OR 48MHz when BIT(23) is\nclear. You need to test BIT(18) as well on the AST2400 to disambiguate.\n\n> +\thw = clk_hw_register_fixed_rate(NULL, \"clkin\", NULL, 0, freq);\n> +\tpr_debug(\"clkin @%lu MHz\\n\", freq / 1000000);\n> +\n> +\tif (of_device_is_compatible(np, \"aspeed,ast2400-scu\"))\n> +\t\taspeed_ast2400_cc(map);\n> +\telse if (of_device_is_compatible(np, \"aspeed,ast2500-scu\"))\n> +\t\taspeed_ast2500_cc(map);\n> +\telse\n> +\t\tpr_err(\"unknown platform, failed to add clocks\\n\");\n\nI'm not confident that \"borrowing\" the SCU compatible like this is entirely in\nthe spirit of its MFD nature, but maybe others can chime in.\n\nCheers,\n\nAndrew\n\n> +\n>  \taspeed_clk_data->num = ASPEED_NUM_CLKS;\n>  \tret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, aspeed_clk_data);\n>  \tif (ret)","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Aspeed confirmed this is correct */\n> +\t{ 0x1, 4 },\n> +\t{ 0x2, 6 },\n> +\t{ 0x3, 8 },\n> +\t{ 0x4, 10 },\n> +\t{ 0x5, 12 },\n> +\t{ 0x6, 14 },\n> +\t{ 0x7, 16 },\n> +\t{ 0 }\n> +};\n> +\n>  static const struct clk_div_table ast2400_div_table[] = {\n>  \t{ 0x0, 2 },\n>  \t{ 0x1, 4 },\n> @@ -139,6 +155,21 @@ static const struct clk_div_table ast2500_div_table[] = {\n>  \t{ 0 }\n>  };\n>  \n> +struct aspeed_clk_soc_data {\n> +\tconst struct clk_div_table *div_table;\n> +\tconst struct clk_div_table *mac_div_table;\n> +};\n> +\n> +static const struct aspeed_clk_soc_data ast2500_data = {\n> +\t.div_table = ast2500_div_table,\n> +\t.mac_div_table = ast2500_mac_div_table,\n> +};\n> +\n> +static const struct aspeed_clk_soc_data ast2400_data = {\n> +\t.div_table = ast2400_div_table,\n> +\t.mac_div_table = ast2400_div_table,\n> +};\n> +\n>  static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n>  {\n>  \tunsigned int mult, div;\n> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n>  \t\t\tmult, div);\n>  }\n>  \n> +static int __init aspeed_clk_probe(struct platform_device *pdev)\n> +{\n> +\tconst struct aspeed_clk_soc_data *soc_data;\n> +\tconst struct clk_div_table *mac_div_table;\n> +\tconst struct clk_div_table *div_table;\n> +\tstruct device *dev = &pdev->dev;\n> +\tstruct regmap *map;\n> +\tstruct clk_hw *hw;\n> +\tu32 val, rate;\n> +\n> +\tmap = syscon_node_to_regmap(dev->of_node);\n> +\tif (IS_ERR(map)) {\n> +\t\tdev_err(dev, \"no syscon regmap\\n\");\n> +\t\treturn PTR_ERR(map);\n> +\t}\n> +\n> +\t/* SoC generations share common layouts but have different divisors */\n> +\tsoc_data = of_device_get_match_data(&pdev->dev);\n> +\tdiv_table = soc_data->div_table;\n> +\tmac_div_table = soc_data->mac_div_table;\n> +\n> +\t/* UART clock div13 setting */\n> +\tregmap_read(map, ASPEED_MISC_CTRL, &val);\n> +\tif (val & BIT(12))\n> +\t\trate = 24000000 / 13;\n> +\telse\n> +\t\trate = 24000000;\n> +\t/* TODO: Find the parent data for the uart clock */\n> +\thw = clk_hw_register_fixed_rate(NULL, \"uart\", NULL, 0, rate);\n> +\taspeed_clk_data->hws[ASPEED_CLK_UART] = hw;\n> +\n> +\t/*\n> +\t * Memory controller (M-PLL) PLL. This clock is configured by the\n> +\t * bootloader, and is exposed to Linux as a read-only clock rate.\n> +\t */\n> +\tregmap_read(map, ASPEED_MPLL_PARAM, &val);\n> +\taspeed_clk_data->hws[ASPEED_CLK_MPLL] =\taspeed_calc_pll(\"mpll\", val);\n\nIIRC the calculation in aspeed_calc_pll() is appropriate for the AST2500, but\nnot the AST2400.\n\n> +\n> +\t/* SD/SDIO clock divider (TODO: There's a gate too) */\n> +\thw = clk_hw_register_divider_table(NULL, \"sdio\", \"hpll\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 12, 3, 0,\n> +\t\t\tdiv_table,\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;\n> +\n> +\t/* MAC AHB bus clock divider */\n> +\thw = clk_hw_register_divider_table(NULL, \"mac\", \"hpll\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 16, 3, 0,\n> +\t\t\tmac_div_table,\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;\n> +\n> +\t/* LPC Host (LHCLK) clock divider */\n> +\thw = clk_hw_register_divider_table(NULL, \"lhclk\", \"hpll\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 20, 3, 0,\n> +\t\t\tdiv_table,\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;\n> +\n> +\t/* Video Engine (ECLK) mux and clock divider */\n> +\thw = clk_hw_register_mux(NULL, \"eclk_mux\",\n> +\t\t\teclk_parents, ARRAY_SIZE(eclk_parents), 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 2, 2,\n> +\t\t\t0, &aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;\n> +\thw = clk_hw_register_divider_table(NULL, \"eclk\", \"eclk_mux\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 20, 3, 0,\n\nOn the AST2500 it looks like this should start at bit 28 for 3 bits, not bit\n20. Separately, I'm not sure how to interpret the AST2400 datasheet here -\nmaybe it's similar but with different wording (\"clock slow down\" rather than\n\"divisor\"?).\n\n> +\t\t\tdiv_table,\n\nThis doesn't seem to be correct. There's the problem of 0b000 and 0b001 mapping\nthe same value of 2 for the AST2500, whose table then increments in steps of 1.\nThe AST2400 mapping on the otherhand is multiples of 2 starting at 2, with no\ninconsistency for 0b000 vs 0b001.\n\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;\n> +\n> +\t/* P-Bus (BCLK) clock divider */\n> +\thw = clk_hw_register_divider_table(NULL, \"bclk\", \"hpll\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 0, 2, 0,\n\nBit 0 in SCU08 is a 1-bit field \"CPU/AHB clock dynamic slow down enable\". BCLK\nis actually in SCU*D*8, but (perhaps confusingly) documented immediately below\nSCU*0*8.\n\nCheers,\n\nAndrew\n\n> +\t\t\tdiv_table,\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;\n> +\n> +\treturn 0;\n> +};\n> +\n> +static const struct of_device_id aspeed_clk_dt_ids[] = {\n> +\t{ .compatible = \"aspeed,ast2400-scu\", .data = &ast2400_data },\n> +\t{ .compatible = \"aspeed,ast2500-scu\", .data = &ast2500_data },\n> +\t{ },\n> +};\n> +\n> +static struct platform_driver aspeed_clk_driver = {\n> +\t.probe  = aspeed_clk_probe,\n> +\t.driver = {\n> +\t\t.name = \"aspeed-clk\",\n> +\t\t.of_match_table = aspeed_clk_dt_ids,\n> +\t\t.suppress_bind_attrs = true,\n> +\t},\n> +};\n> +builtin_platform_driver(aspeed_clk_driver);\n> +\n> +\n>  static void __init aspeed_ast2400_cc(struct regmap *map)\n>  {\n>  \tstruct clk_hw *hw;","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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These are\n> represented by a reset controller.\n> \n> Signed-off-by: Joel Stanley \n> ---\n>  drivers/clk/clk-aspeed.c                 | 82 +++++++++++++++++++++++++++++++-\n>  include/dt-bindings/clock/aspeed-clock.h |  9 ++++\n>  2 files changed, 90 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c\n> index dec9db4ec47b..db97c0f9f99e 100644\n> --- a/drivers/clk/clk-aspeed.c\n> +++ b/drivers/clk/clk-aspeed.c\n> @@ -17,6 +17,7 @@\n>  #include \n>  #include \n>  #include \n> +#include \n>  #include \n>  #include \n>  \n> @@ -256,6 +257,68 @@ static const struct clk_ops aspeed_clk_gate_ops = {\n>  \t.is_enabled = aspeed_clk_is_enabled,\n>  };\n>  \n> +/**\n> + * struct aspeed_reset - Aspeed reset controller\n> + * @map: regmap to access the containing system controller\n> + * @rcdev: reset controller device\n> + */\n> +struct aspeed_reset {\n> +\tstruct regmap\t\t\t*map;\n> +\tstruct reset_controller_dev\trcdev;\n> +};\n> +\n> +#define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)\n> +\n> +static const u8 aspeed_resets[] = {\n> +\t25, /* x-dma */\n> +\t24, /* mctp */\n> +\t23, /* adc */\n> +\t22, /* jtag-master */\n> +\t18, /* mic */\n> +\t 9, /* pwm */\n> +\t 8, /* pci-vga */\n> +\t 2, /* i2c */\n> +\t 1, /* ahb */\n\nBit of a nit, but given you define macros for the indices, maybe use designated\ninitialisers and drop the comments.\n\n> +};\n> +\n> +static int aspeed_reset_deassert(struct reset_controller_dev *rcdev,\n> +\t\t\t\t unsigned long id)\n> +{\n> +\tstruct aspeed_reset *ar = to_aspeed_reset(rcdev);\n> +\tu32 rst = BIT(aspeed_resets[id]);\n> +\n> +\treturn regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, 0);\n> +}\n> +\n> +static int aspeed_reset_assert(struct reset_controller_dev *rcdev,\n> +\t\t\t       unsigned long id)\n> +{\n> +\tstruct aspeed_reset *ar = to_aspeed_reset(rcdev);\n> +\tu32 rst = BIT(aspeed_resets[id]);\n> +\n> +\treturn regmap_update_bits(ar->map, ASPEED_RESET_CTRL, rst, rst);\n> +}\n> +\n> +static int aspeed_reset_status(struct reset_controller_dev *rcdev,\n> +\t\t\t       unsigned long id)\n> +{\n> +\tstruct aspeed_reset *ar = to_aspeed_reset(rcdev);\n> +\tu32 val, rst = BIT(aspeed_resets[id]);\n> +\tint ret;\n> +\n> +\tret = regmap_read(ar->map, ASPEED_RESET_CTRL, &val);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\treturn !!(val & rst);\n> +}\n> +\n> +static const struct reset_control_ops aspeed_reset_ops = {\n> +\t.assert = aspeed_reset_assert,\n> +\t.deassert = aspeed_reset_deassert,\n> +\t.status = aspeed_reset_status,\n> +};\n> +\n>  static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,\n>  \t\tconst char *name, const char *parent_name, unsigned long flags,\n>  \t\tstruct regmap *map, u8 clock_idx, u8 reset_idx,\n> @@ -299,10 +362,11 @@ static int __init aspeed_clk_probe(struct platform_device *pdev)\n>  \tconst struct clk_div_table *mac_div_table;\n>  \tconst struct clk_div_table *div_table;\n>  \tstruct device *dev = &pdev->dev;\n> +\tstruct aspeed_reset *ar;\n>  \tstruct regmap *map;\n>  \tstruct clk_hw *hw;\n>  \tu32 val, rate;\n> -\tint i;\n> +\tint i, ret;\n>  \n>  \tmap = syscon_node_to_regmap(dev->of_node);\n>  \tif (IS_ERR(map)) {\n> @@ -310,6 +374,22 @@ static int __init aspeed_clk_probe(struct platform_device *pdev)\n>  \t\treturn PTR_ERR(map);\n>  \t}\n>  \n> +\tar = devm_kzalloc(dev, sizeof(*ar), GFP_KERNEL);\n> +\tif (!ar)\n> +\t\treturn -ENOMEM;\n> +\n> +\tar->map = map;\n> +\tar->rcdev.owner = THIS_MODULE;\n> +\tar->rcdev.nr_resets = ARRAY_SIZE(aspeed_resets);\n> +\tar->rcdev.ops = &aspeed_reset_ops;\n> +\tar->rcdev.of_node = dev->of_node;\n> +\n> +\tret = devm_reset_controller_register(dev, &ar->rcdev);\n> +\tif (ret) {\n> +\t\tdev_err(dev, \"could not register reset controller\\n\");\n> +\t\treturn ret;\n> +\t}\n> +\n>  \t/* SoC generations share common layouts but have different divisors */\n>  \tsoc_data = of_device_get_match_data(&pdev->dev);\n>  \tdiv_table = soc_data->div_table;\n> diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h\n> index afe06b77562d..a9d552b6bbd2 100644\n> --- a/include/dt-bindings/clock/aspeed-clock.h\n> +++ b/include/dt-bindings/clock/aspeed-clock.h\n> @@ -40,4 +40,13 @@\n>  #define ASPEED_CLK_GATE_SDCLKCLK\t(22 + ASPEED_CLK_GATES)\n>  #define ASPEED_CLK_GATE_LHCCLK\t\t(23 + ASPEED_CLK_GATES)\n>  \n> +#define ASPEED_RESET_XDMA\t\t0\n> +#define ASPEED_RESET_MCTP\t\t1\n> +#define ASPEED_RESET_JTAG_MASTER\t2\n> +#define ASPEED_RESET_MIC\t\t3\n> +#define ASPEED_RESET_PWM\t\t4\n> +#define ASPEED_RESET_PCIVGA\t\t5\n> +#define ASPEED_RESET_I2C\t\t6\n> +#define ASPEED_RESET_AHB\t\t7\n> +\n>  #endif","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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it's not going to make it any easier to read so lets leave it as is.\n\n>\n>> +\n>> +#define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)\n>> +\n>> +/* TODO: ask Aspeed about the actual parent data */\n>> +static const struct aspeed_gate_data aspeed_gates[] __initconst = {\n>> +/* clk rst name parent flags */\n>> + { 0, -1, \"eclk-gate\", \"eclk\", 0 }, /* Video Engine */\n>> + { 1, 7, \"gclk-gate\", NULL, 0 }, /* 2D engine */\n>> + { 2, -1, \"mclk-gate\", \"mpll\", CLK_IS_CRITICAL }, /* SDRAM */\n>> + { 3, 6, \"vclk-gate\", NULL, 0 }, /* Video Capture */\n>> + { 4, 10, \"bclk-gate\", \"bclk\", 0 }, /* PCIe/PCI */\n>> + { 5, -1, \"dclk-gate\", NULL, 0 }, /* DAC */\n>> + { 6, -1, \"refclk-gate\", \"clkin\", CLK_IS_CRITICAL },\n>> + { 7, 3, \"usb-port2-gate\", NULL, 0 }, /* USB2.0 Host port 2 */\n>> + { 8, 5, \"lclk-gate\", NULL, 0 }, /* LPC */\n>> + { 9, 15, \"usb-uhci-gate\", NULL, 0 }, /* USB1.1 (requires port 2 enabled) */\n>> + { 10, 13, \"d1clk-gate\", NULL, 0 }, /* GFX CRT */\n>\n> Is there a typo in the AST2400 datasheet? It claims bit 10 is \"D2CLK\".\n\nThe ast2500 says d1clk, and the ast2400 says d2clk. Both call it the\nGFX CRT clock. Normally changes between the two are in a different\ncolour, but we don't have that here :(\n\nI'll ask Ryan if he knows what's going on.\n\n>\n>> + /* 11: reserved */\n>> + /* 12: reserved */\n>> + { 13, 4, \"yclk-gate\", NULL, 0 }, /* HAC */\n>> + { 14, 14, \"usb-port1-gate\", NULL, 0 }, /* USB2 hub/USB2 host port 1/USB1.1 dev */\n>> + { 15, -1, \"uart1clk-gate\", \"uart\", 0 }, /* UART1 */\n>> + { 16, -1, \"uart2clk-gate\", \"uart\", 0 }, /* UART2 */\n>> + { 17, -1, \"uart5clk-gate\", \"uart\", 0 }, /* UART5 */\n>> + /* 18: reserved */\n>> + { 19, -1, \"espiclk-gate\", NULL, 0 }, /* eSPI */\n>\n> 19 is reserved on the AST2400, and must be kept at '1'.\n\nYeah. This is another difference between the SoCs that isn't called\nout by the \"this has changed\" colouring of the datasheet.\n\nI'd suggest it's not worth adding the code to make the driver return\nan error when requesting this one. If anyone feels strongly about it\nwe could skip the registration of this one at probe time on the\nast2400.\n\n>\n>> + { 20, 11, \"mac1clk-gate\", \"clkin\", 0 }, /* MAC1 */\n>> + { 21, 12, \"mac2clk-gate\", \"clkin\", 0 }, /* MAC2 */\n>> + /* 22: reserved */\n>> + /* 23: reserved */\n>> + { 24, -1, \"rsaclk-gate\", NULL, 0 }, /* RSA */\n>> + { 25, -1, \"uart3clk-gate\", \"uart\", 0 }, /* UART3 */\n>> + { 26, -1, \"uart4clk-gate\", \"uart\", 0 }, /* UART4 */\n>> + { 27, 16, \"sdclk-gate\", NULL, 0 }, /* SDIO/SD */\n>> + { 28, -1, \"lhclk-gate\", \"lhclk\", 0 }, /* LPC master/LPC+ */\n>> + /* 29: reserved */\n>> + /* 30: reserved */\n>> + /* 31: reserved */\n>\n> Interestingly bits 29-30 are reserved in both the AST2400 and AST2500\n> datasheets, but are reserved-clear in the AST2400 datasheet and reserved-set in\n> the AST2500 datasheet. This may affect how we write register.\n\nThe driver doesn't change the value, so I think we're safe.\n\n> Separately, at one point I mistook the clk column for the index the entry\n> should appear at, which isn't the case. Do you think designated intializers\n> might help?\n\nWill make the table a bit awkward, but it's a good suggestion. I'll\ngive it a go for v3.\n\n>> + /*\n>> + * This way all clock fetched before the platform device probes,\n>\n> Typo: \"clocks\"\n\nNice catch. It's a typo in the Gemini driver as well ;)\n\n>\n>> + * except those we assign here for early use, will be deferred.\n>> + */\n>> + for (i = 0; i < ASPEED_NUM_CLKS; i++)\n>> + aspeed_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);\n\n>> +++ b/include/dt-bindings/clock/aspeed-clock.h\n>> @@ -0,0 +1,43 @@\n>> +#ifndef DT_BINDINGS_ASPEED_CLOCK_H\n>> +#define DT_BINDINGS_ASPEED_CLOCK_H\n>> +\n>> +#define ASPEED_NUM_CLKS 34\n>\n> This is a bit of a nit pick: Do the constants below represent all the\n> clocks in the SoC(s)? Maybe if not it's better to define\n> ASPEED_NUM_CLKS in terms of (n + ASPEED_CLK_GATES) at the bottom - that\n> way when a clock or gate is added ASPEED_NUM_CLKS has better locality and\n> better visual progression in context.\n\nOkay, I put it at the bottom.\n\n>> +#define ASPEED_CLK_GATE_LHCCLK (23 + ASPEED_CLK_GATES)\n>\n> Looks like there's an off-by-one error here: ASPEED_NUM_CLKS should be (23 +\n> ASPEED_CLK_GATES + 1) = 35.\n\nThanks, fixed.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"iszC+wbR\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"uTqZVnrU\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776047,"web_url":"http://patchwork.ozlabs.org/comment/1776047/","msgid":"","list_archive_url":null,"date":"2017-09-27T06:13:07","subject":"Re: [PATCH v2 2/5] clk: aspeed: Register core clocks","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"On Mon, Sep 25, 2017 at 10:02 PM, Andrew Jeffery wrote:\n\n>> +static const struct clk_div_table ast2400_div_table[] = {\n>> + { 0x0, 2 },\n>> + { 0x1, 4 },\n>> + { 0x2, 6 },\n>> + { 0x3, 8 },\n>> + { 0x4, 10 },\n>> + { 0x5, 12 },\n>> + { 0x6, 14 },\n>> + { 0x7, 16 },\n>> + { 0 }\n>> +};\n>> +\n>> +static const struct clk_div_table ast2500_div_table[] = {\n>> + { 0x0, 4 },\n>> + { 0x1, 8 },\n>> + { 0x2, 12 },\n>> + { 0x3, 16 },\n>> + { 0x4, 20 },\n>> + { 0x5, 24 },\n>> + { 0x6, 28 },\n>> + { 0x7, 32 },\n>> + { 0 }\n>> +};\n>\n> ast2500_div_table is unused?\n\nIn this patch, yeah. It gets used in the next one. I defined it next\nto the ast2400_div_table so that it is clear why we need the separate\nones.\n\n>> +static void __init aspeed_ast2400_cc(struct regmap *map)\n>> +{\n>> + struct clk_hw *hw;\n>> + u32 val, div, mult;\n>> +\n>> + /*\n>> + * High-speed PLL clock derived from the crystal. This the CPU clock,\n>> + * and we assume that it is enabled\n>> + */\n>> + regmap_read(map, ASPEED_HPLL_PARAM, &val);\n>> + WARN(val & BIT(18), \"clock is strapped not configured\");\n>\n> I don't quite understand the intent of the warning - are we just trying to say\n> that the defaults have been assumed and they may not match reality? It's\n> probably not a great idea to not strap the board properly, but you could get\n> away with it for a given configuration (Numerator = 20, H-PLL Output Divider\n> set, H-PLL denominator = 1)\n\nThe vlaue of the PLL can be configured in two different ways; one is\nvia the strapping registers and the other is configured via the\nASPEED_HPLL_PARAM.\n\nI added this warning as the driver does not support reading the value\nof hpll from the strapping.\n\n>\n>> + if (val & BIT(17)) {\n>> + /* Pass through mode */\n>> + mult = div = 1;\n>> + } else {\n>> + /* F = 24Mhz * (2-OD) * [(N + 2) / (D + 1)] */\n>> + u32 n = (val >> 5) & 0x3f;\n>> + u32 od = (val >> 4) & 0x1;\n>> + u32 d = val & 0xf;\n>> +\n>> + mult = (2 - od) * (n + 2);\n>> + div = d + 1;\n>> + }\n>> + hw = clk_hw_register_fixed_factor(NULL, \"hpll\", \"clkin\", 0, mult, div);\n>> + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw;\n>> +\n>> + /*\n>> + * Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)\n>> + * 00: Select CPU:AHB = 1:1\n>> + * 01: Select CPU:AHB = 2:1\n>> + * 10: Select CPU:AHB = 4:1\n>> + * 11: Select CPU:AHB = 3:1\n>> + */\n>> + regmap_read(map, ASPEED_STRAP, &val);\n>> + val = (val >> 10) & 0x3;\n>\n> How do the calculations below line up with the comment above? I can't see the\n> connection and I feel like I've missed something.\n>\n\nThe code should read like this:\n\nif (div == 3)\n div = 4;\nelse if (div == 3)\n div = 4;\n\nFixed in v3.\n\n>\n>> + hw = clk_hw_register_fixed_factor(NULL, \"ahb\", \"hpll\", 0, 1, div);\n>> + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;\n>> +\n>> + /* APB clock clock selection register SCU08 (aka PCLK) */\n>> + hw = clk_hw_register_divider_table(NULL, \"apb\", \"hpll\", 0,\n>> + scu_base + ASPEED_CLK_SELECTION, 23, 3, 0,\n>> + ast2400_div_table,\n>> + &aspeed_clk_lock);\n>> + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;\n>> +}\n>> +\n>> +static void __init aspeed_ast2500_cc(struct regmap *map)\n>> +{\n>> + struct clk_hw *hw;\n>> + u32 val, div;\n>> +\n>> + /*\n>> + * High-speed PLL clock derived from the crystal. This the CPU clock,\n>> + * and we assume that it is enabled\n>> + */\n>> + regmap_read(map, ASPEED_HPLL_PARAM, &val);\n>> + aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_calc_pll(\"hpll\", val);\n>\n> Why did you extract the aspeed_calc_pll() implementation for the ast2500 but\n> not the ast2400?\n\nIt was used more than once for the ast2500, but only once for the\nast2400. That's changed it v3 so I broke it out again.\n\n>> +\n>> + /* Strap bits 11:9 define the AXI/AHB clock frequency ratio (aka HCLK)*/\n>> + regmap_read(map, ASPEED_STRAP, &val);\n>> + val = (val >> 9) & 0x7;\n>> + WARN_ON(val == 0);\n>\n> Maybe WARN() would be better here to explain what's going wrong (zero is an\n> undefined value)?\n\nDone.\n\n>\n>> + div = 2 * (val + 1);\n>> + hw = clk_hw_register_fixed_factor(NULL, \"ahb\", \"hpll\", 0, 1, div);\n>> + aspeed_clk_data->hws[ASPEED_CLK_AHB] = hw;\n>> +\n>> + /* APB clock clock selection register SCU08 (aka PCLK) */\n>> + /* TODO: this is wrong! */\n>\n> Why is this wrong?\n\nI think I must have been looking at the ast2400 data sheet and gotten\nconfused. It looks good to me. I removed the comment in v3.\n\n>\n>> + regmap_read(map, ASPEED_CLK_SELECTION, &val);\n>> + val = (val >> 23) & 0x7;\n>> + div = 4 * (val + 1);\n>> + hw = clk_hw_register_fixed_factor(NULL, \"apb\", \"hpll\", 0, 1, div);\n>> + aspeed_clk_data->hws[ASPEED_CLK_APB] = hw;\n>> +};\n>> +\n>> +\n>> static void __init aspeed_cc_init(struct device_node *np)\n>> {\n>> struct regmap *map;\n>> + unsigned long freq;\n>> + struct clk_hw *hw;\n>> u32 val;\n>> int ret;\n>> int i;\n>> @@ -153,6 +284,21 @@ static void __init aspeed_cc_init(struct device_node *np)\n>> return;\n>> }\n>>\n>> + /* CLKIN is the crystal oscillator, 24 or 25MHz selected by strapping */\n>> + if (val & BIT(23))\n>> + freq = 25000000;\n>> + else\n>> + freq = 24000000;\n>\n> This isn't true on the AST2400, where CLKIN could be 24 OR 48MHz when BIT(23) is\n> clear. You need to test BIT(18) as well on the AST2400 to disambiguate.\n\nFixed. I moved the clkin calcs into the soc specific functions.\n\n>\n>> + hw = clk_hw_register_fixed_rate(NULL, \"clkin\", NULL, 0, freq);\n>> + pr_debug(\"clkin @%lu MHz\\n\", freq / 1000000);\n>> +\n>> + if (of_device_is_compatible(np, \"aspeed,ast2400-scu\"))\n>> + aspeed_ast2400_cc(map);\n>> + else if (of_device_is_compatible(np, \"aspeed,ast2500-scu\"))\n>> + aspeed_ast2500_cc(map);\n>> + else\n>> + pr_err(\"unknown platform, failed to add clocks\\n\");\n>\n> I'm not confident that \"borrowing\" the SCU compatible like this is entirely in\n> the spirit of its MFD nature, but maybe others can chime in.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776048,"web_url":"http://patchwork.ozlabs.org/comment/1776048/","msgid":"","list_archive_url":null,"date":"2017-09-27T06:13:38","subject":"Re: [PATCH v2 5/5] clk: aspeed: Add reset controller","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"On Mon, Sep 25, 2017 at 10:54 PM, Andrew Jeffery wrote:\n> On Thu, 2017-09-21 at 13:56 +0930, Joel Stanley wrote:\n>> +static const u8 aspeed_resets[] = {\n>> + 25, /* x-dma */\n>> + 24, /* mctp */\n>> + 23, /* adc */\n>> + 22, /* jtag-master */\n>> + 18, /* mic */\n>> + 9, /* pwm */\n>> + 8, /* pci-vga */\n>> + 2, /* i2c */\n>> + 1, /* ahb */\n>\n> Bit of a nit, but given you define macros for the indices, maybe use designated\n> initialisers and drop the comments.\n\nDone. And that way I'd notice that I missed the define for the ADC :)\n\nCheers,\n\nJoel","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"jTwP9tGu\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"pdsG1tY2\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y26x002dmz9s9Y\n\tfor ;\n\tWed, 27 Sep 2017 16:14:44 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dx5cD-0002lu-9o; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776051,"web_url":"http://patchwork.ozlabs.org/comment/1776051/","msgid":"","list_archive_url":null,"date":"2017-09-27T06:13:30","subject":"Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register\n\tPLLs","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"On Mon, Sep 25, 2017 at 10:40 PM, Andrew Jeffery wrote:\n> On Thu, 2017-09-21 at 13:56 +0930, Joel Stanley wrote:\n\n>> + /*\n>> + * Memory controller (M-PLL) PLL. This clock is configured by the\n>> + * bootloader, and is exposed to Linux as a read-only clock rate.\n>> + */\n>> + regmap_read(map, ASPEED_MPLL_PARAM, &val);\n>> + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = aspeed_calc_pll(\"mpll\", val);\n>\n> IIRC the calculation in aspeed_calc_pll() is appropriate for the AST2500, but\n> not the AST2400.\n\nAh ha. I knew there was a reason why I created an ast2400_calc_pll. I\nwill add it back in in the previous patch so we can use it here.\n\n>> + /* Video Engine (ECLK) mux and clock divider */\n>> + hw = clk_hw_register_mux(NULL, \"eclk_mux\",\n>> + eclk_parents, ARRAY_SIZE(eclk_parents), 0,\n>> + scu_base + ASPEED_CLK_SELECTION, 2, 2,\n>> + 0, &aspeed_clk_lock);\n>> + aspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;\n>> + hw = clk_hw_register_divider_table(NULL, \"eclk\", \"eclk_mux\", 0,\n>> + scu_base + ASPEED_CLK_SELECTION, 20, 3, 0,\n>\n> On the AST2500 it looks like this should start at bit 28 for 3 bits, not bit\n\nGood catch. Fixed in v3.\n\n> 20. Separately, I'm not sure how to interpret the AST2400 datasheet here -\n> maybe it's similar but with different wording (\"clock slow down\" rather than\n> \"divisor\"?).\n>\n>> + div_table,\n>\n> This doesn't seem to be correct. There's the problem of 0b000 and 0b001 mapping\n> the same value of 2 for the AST2500, whose table then increments in steps of 1.\n> The AST2400 mapping on the otherhand is multiples of 2 starting at 2, with no\n> inconsistency for 0b000 vs 0b001.\n\nYep, we do use a different table for ast2400 vs ast2500. See\nast2400_div_table vs ast2500_div_table.\n\n>\n>> + &aspeed_clk_lock);\n>> + aspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;\n>> +\n>> + /* P-Bus (BCLK) clock divider */\n>> + hw = clk_hw_register_divider_table(NULL, \"bclk\", \"hpll\", 0,\n>> + scu_base + ASPEED_CLK_SELECTION, 0, 2, 0,\n>\n> Bit 0 in SCU08 is a 1-bit field \"CPU/AHB clock dynamic slow down enable\". BCLK\n> is actually in SCU*D*8, but (perhaps confusingly) documented immediately below\n> SCU*0*8.\n\nGood catch. Fixed in v3.\n\nCheers,\n\nJoel","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"bWePY9dI\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"m5/fK6+f\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y271p5r4zz9sBW\n\tfor ;\n\tWed, 27 Sep 2017 16:18:54 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dx5gC-0007nj-NC; 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Tue,\n\t26 Sep 2017 23:13:50 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1506343255.30138.29.camel@aj.id.au>","References":"<20170921042641.7326-1-joel@jms.id.au>\n\t<20170921042641.7326-4-joel@jms.id.au>\n\t<1506343255.30138.29.camel@aj.id.au>","From":"Joel Stanley ","Date":"Wed, 27 Sep 2017 16:13:30 +1000","X-Google-Sender-Auth":"PmDCdTvOZ1AXNdMnL_hpAC36Ejk","Message-ID":"","Subject":"Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register\n\tPLLs","To":"Andrew Jeffery ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170926_231412_899653_D44E5EDE ","X-CRM114-Status":"GOOD ( 19.29 )","X-Spam-Score":"-2.4 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.4 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow\n\ttrust [2a00:1450:4010:c07:0:0:0:235 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (joel.stan[at]gmail.com)\n\t0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level\n\tmail domains are different\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t0.2 FREEMAIL_FORGED_FROMDOMAIN 2nd level domains in From and\n\tEnvelopeFrom freemail headers are different","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Ryan Chen , Arnd Bergmann ,\n\tBenjamin Herrenschmidt ,\n\tMichael Turquette ,\n\tStephen Boyd ,\n\tLinux Kernel Mailing List ,\n\tRick Altherr , Jeremy Kerr ,\n\tLee Jones , linux-clk@vger.kernel.org,\n\tLinux ARM ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776101,"web_url":"http://patchwork.ozlabs.org/comment/1776101/","msgid":"<1506497645.30138.37.camel@aj.id.au>","list_archive_url":null,"date":"2017-09-27T07:34:05","subject":"Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register\n\tPLLs","submitter":{"id":68332,"url":"http://patchwork.ozlabs.org/api/people/68332/","name":"Andrew Jeffery","email":"andrew@aj.id.au"},"content":"On Wed, 2017-09-27 at 16:13 +1000, Joel Stanley wrote:\n> > > +                     div_table,\n> > \n> > This doesn't seem to be correct. There's the problem of 0b000 and 0b001 mapping\n> > the same value of 2 for the AST2500, whose table then increments in steps of 1.\n> > The AST2400 mapping on the otherhand is multiples of 2 starting at 2, with no\n> > inconsistency for 0b000 vs 0b001.\n> \n> Yep, we do use a different table for ast2400 vs ast2500. See\n> ast2400_div_table vs ast2500_div_table.\n\nYep, but for the AST2500 this is a different table again to what you've\nalready defined (for the AST2500). However, for the AST2400 the table\nlooks the same as the other AST2400 tables.\n\nCheers,\n\nAndrew","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"lInnPfCF\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=aj.id.au header.i=@aj.id.au header.b=\"boYOZ1iy\";\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=messagingengine.com\n\theader.i=@messagingengine.com\n\theader.b=\"XFh9ZBun\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y291x3Yf9z9t4b\n\tfor ;\n\tWed, 27 Sep 2017 17:49:09 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dx75a-00030D-6F; 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There's the problem of 0b000 and 0b001 mapping\n>> > the same value of 2 for the AST2500, whose table then increments in steps of 1.\n>> > The AST2400 mapping on the otherhand is multiples of 2 starting at 2, with no\n>> > inconsistency for 0b000 vs 0b001.\n>>\n>> Yep, we do use a different table for ast2400 vs ast2500. See\n>> ast2400_div_table vs ast2500_div_table.\n>\n> Yep, but for the AST2500 this is a different table again to what you've\n> already defined (for the AST2500). However, for the AST2400 the table\n> looks the same as the other AST2400 tables.\n\nYou're right. I didn't realise you were pointing out something strange\nabout eclk.\n\nI added another table for eclk, and the correct one is selected by the\nplatform data.\n\nI'll send out v4 today if no more reviews come in.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"H/kCrQgN\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"luOyaWO4\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2hYz3fHJz9tXb\n\tfor ;\n\tThu, 28 Sep 2017 14:30:15 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxQSg-0001jL-GR; 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\n\tWed, 27 Sep 2017 21:29:42 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<1506497645.30138.37.camel@aj.id.au>","References":"<20170921042641.7326-1-joel@jms.id.au>\n\t<20170921042641.7326-4-joel@jms.id.au>\n\t<1506343255.30138.29.camel@aj.id.au>\n\t\n\t<1506497645.30138.37.camel@aj.id.au>","From":"Joel Stanley ","Date":"Thu, 28 Sep 2017 14:29:22 +1000","X-Google-Sender-Auth":"5YVZSVpKTvjyb0o4ViDySH06rvc","Message-ID":"","Subject":"Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register\n\tPLLs","To":"Andrew Jeffery ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170927_213006_732611_B15B78CD ","X-CRM114-Status":"GOOD ( 16.15 )","X-Spam-Score":"-1.7 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.7 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2a00:1450:400c:c0c:0:0:0:233 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (joel.stan[at]gmail.com)\n\t0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level\n\tmail domains are different\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t0.2 FREEMAIL_FORGED_FROMDOMAIN 2nd level domains in From and\n\tEnvelopeFrom freemail headers are different","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Ryan Chen , Arnd Bergmann ,\n\tBenjamin Herrenschmidt ,\n\tMichael Turquette ,\n\tStephen Boyd ,\n\tLinux Kernel Mailing List ,\n\tRick Altherr , Jeremy Kerr ,\n\tLee Jones , linux-clk@vger.kernel.org,\n\tLinux ARM ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778620,"web_url":"http://patchwork.ozlabs.org/comment/1778620/","msgid":"<20171002212435.GP457@codeaurora.org>","list_archive_url":null,"date":"2017-10-02T21:24:35","subject":"Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register\n\tPLLs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/21, Joel Stanley wrote:\n> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n> \t\t\tmult, div);\n> }\n> \n> +static int __init aspeed_clk_probe(struct platform_device *pdev)\n\nDrop __init? Should be a section mismatch with __init here.\n\n> +{\n> +\tconst struct aspeed_clk_soc_data *soc_data;\n> +\tconst struct clk_div_table *mac_div_table;\n> +\tconst struct clk_div_table *div_table;\n> +\tstruct device *dev = &pdev->dev;\n> +\tstruct regmap *map;\n> +\tstruct clk_hw *hw;\n> +\tu32 val, rate;\n> +\n> +\tmap = syscon_node_to_regmap(dev->of_node);\n> +\tif (IS_ERR(map)) {\n> +\t\tdev_err(dev, \"no syscon regmap\\n\");\n> +\t\treturn PTR_ERR(map);\n> +\t}\n> +\n> +\t/* SoC generations share common layouts but have different divisors */\n> +\tsoc_data = of_device_get_match_data(&pdev->dev);\n\nCheck for soc_data being NULL.\n\n> +\tdiv_table = soc_data->div_table;\n> +\tmac_div_table = soc_data->mac_div_table;\n> +\n> +\t/* UART clock div13 setting */\n> +\tregmap_read(map, ASPEED_MISC_CTRL, &val);\n> +\tif (val & BIT(12))\n\nWhat does BIT(12) mean? #define or comment please.\n\n> +\t\trate = 24000000 / 13;\n> +\telse\n> +\t\trate = 24000000;\n> +\t/* TODO: Find the parent data for the uart clock */\n> +\thw = clk_hw_register_fixed_rate(NULL, \"uart\", NULL, 0, rate);\n> +\taspeed_clk_data->hws[ASPEED_CLK_UART] = hw;\n> +\n> +\t/*\n> +\t * Memory controller (M-PLL) PLL. This clock is configured by the\n> +\t * bootloader, and is exposed to Linux as a read-only clock rate.\n> +\t */\n> +\tregmap_read(map, ASPEED_MPLL_PARAM, &val);\n> +\taspeed_clk_data->hws[ASPEED_CLK_MPLL] =\taspeed_calc_pll(\"mpll\", val);\n> +\n> +\t/* SD/SDIO clock divider (TODO: There's a gate too) */\n> +\thw = clk_hw_register_divider_table(NULL, \"sdio\", \"hpll\", 0,\n\nPlease pass your dev pointer here from the platform device.\n\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 12, 3, 0,\n> +\t\t\tdiv_table,\n> +\t\t\t&aspeed_clk_lock);\n\nAnd check for errors? Perhaps use devm_clk_hw_regsiter() APIs and\nconstruct the dividers and muxes directly instead of using the\nbasic type registration APIs.\n\n> +\taspeed_clk_data->hws[ASPEED_CLK_SDIO] = hw;\n> +\n> +\t/* MAC AHB bus clock divider */\n> +\thw = clk_hw_register_divider_table(NULL, \"mac\", \"hpll\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 16, 3, 0,\n> +\t\t\tmac_div_table,\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_MAC] = hw;\n> +\n> +\t/* LPC Host (LHCLK) clock divider */\n> +\thw = clk_hw_register_divider_table(NULL, \"lhclk\", \"hpll\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 20, 3, 0,\n> +\t\t\tdiv_table,\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_LHCLK] = hw;\n> +\n> +\t/* Video Engine (ECLK) mux and clock divider */\n> +\thw = clk_hw_register_mux(NULL, \"eclk_mux\",\n> +\t\t\teclk_parents, ARRAY_SIZE(eclk_parents), 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 2, 2,\n> +\t\t\t0, &aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_ECLK_MUX] = hw;\n> +\thw = clk_hw_register_divider_table(NULL, \"eclk\", \"eclk_mux\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 20, 3, 0,\n> +\t\t\tdiv_table,\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_ECLK] = hw;\n> +\n> +\t/* P-Bus (BCLK) clock divider */\n> +\thw = clk_hw_register_divider_table(NULL, \"bclk\", \"hpll\", 0,\n> +\t\t\tscu_base + ASPEED_CLK_SELECTION, 0, 2, 0,\n> +\t\t\tdiv_table,\n> +\t\t\t&aspeed_clk_lock);\n> +\taspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;\n> +\n> +\treturn 0;\n> +};\n> +\n> +static const struct of_device_id aspeed_clk_dt_ids[] = {\n> +\t{ .compatible = \"aspeed,ast2400-scu\", .data = &ast2400_data },\n> +\t{ .compatible = \"aspeed,ast2500-scu\", .data = &ast2500_data },\n> +\t{ },\n\n ^\nNitpick, drop the comma\n\n> +};\n> +\n> +static struct platform_driver aspeed_clk_driver = {\n> +\t.probe = aspeed_clk_probe,\n> +\t.driver = {\n> +\t\t.name = \"aspeed-clk\",\n> +\t\t.of_match_table = aspeed_clk_dt_ids,\n> +\t\t.suppress_bind_attrs = true,\n> +\t},\n> +};\n> +builtin_platform_driver(aspeed_clk_driver);\n> +\n> +\n\nKill a newline, save the internet.\n\n> static void __init aspeed_ast2400_cc(struct regmap *map)\n> {\n> \tstruct clk_hw *hw;","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778624,"web_url":"http://patchwork.ozlabs.org/comment/1778624/","msgid":"<20171002213742.GQ457@codeaurora.org>","list_archive_url":null,"date":"2017-10-02T21:37:42","subject":"Re: [PATCH v2 4/5] clk: aspeed: Register gated clocks","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/21, Joel Stanley wrote:\n> The majority of the clocks in the system are gates paired with a reset\n> controller that holds the IP in reset.\n> \n> This borrows from clk_hw_register_gate, but registers two 'gates', one\n> to control the clock enable register and the other to control the reset\n> IP. This allows us to enforce the ordering:\n> \n> 1. Place IP in reset\n> 2. Enable clock\n> 3. Delay\n> 4. Release reset\n> \n> There are some gates that do not have an associated reset; these are\n> handled by using -1 as the index for the reset.\n\nHalf of these aren't clks, but reset bits? Perhaps you should\nregister power domains for these things and then have the power\ndomain assert the reset, enable the clock, delay, and then\nrelease the reset in the poweron callback. Then device drivers\ndon't have to be aware of the ordering, and you can keep\nenforcing the ordering in one place, but we don't have to make\nfake gates and shoehorn the sequence into the clk framework.\n\n> \n> Signed-off-by: Joel Stanley \n> ---\n> drivers/clk/clk-aspeed.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 128 insertions(+)\n> \n> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c\n> index 19531798e040..dec9db4ec47b 100644\n> --- a/drivers/clk/clk-aspeed.c\n> +++ b/drivers/clk/clk-aspeed.c\n> @@ -191,6 +191,108 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n> \t\t\tmult, div);\n> }\n> \n> +static int aspeed_clk_enable(struct clk_hw *hw)\n> +{\n> +\tstruct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);\n> +\tunsigned long flags;\n> +\tu32 clk = BIT(gate->clock_idx);\n> +\tu32 rst = BIT(gate->reset_idx);\n> +\n> +\tspin_lock_irqsave(gate->lock, flags);\n> +\n> +\tif (gate->reset_idx >= 0) {\n> +\t\t/* Put IP in reset */\n> +\t\tregmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, rst);\n> +\n> +\t\t/* Delay 100us */\n> +\t\tudelay(100);\n> +\t}\n> +\n> +\t/* Enable clock */\n> +\tregmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, 0);\n> +\n> +\tif (gate->reset_idx >= 0) {\n> +\t\t/* Delay 10ms */\n> +\t\t/* TODO: can we sleep here? */\n> +\t\tmsleep(10);\n> +\n> +\t\t/* Take IP out of reset */\n> +\t\tregmap_update_bits(gate->map, ASPEED_RESET_CTRL, rst, 0);\n> +\t}\n> +\n> +\tspin_unlock_irqrestore(gate->lock, flags);\n> +\n> +\treturn 0;\n> +}\n> +\n> +static void aspeed_clk_disable(struct clk_hw *hw)\n> +{\n> +\tstruct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);\n> +\tunsigned long flags;\n> +\tu32 clk = BIT(gate->clock_idx);\n> +\n> +\tspin_lock_irqsave(gate->lock, flags);\n> +\n> +\t/* Disable clock */\n\nDrop useless comment please.\n\n> +\tregmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, clk);\n> +\n> +\tspin_unlock_irqrestore(gate->lock, flags);\n> +}\n> +\n> +static int aspeed_clk_is_enabled(struct clk_hw *hw)\n> +{\n> +\tstruct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);\n> +\tu32 clk = BIT(gate->clock_idx);\n> +\tu32 reg;\n> +\n> +\tregmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);\n> +\n> +\treturn (reg & clk) ? 0 : 1;\n> +}\n> +\n> +static const struct clk_ops aspeed_clk_gate_ops = {\n> +\t.enable = aspeed_clk_enable,\n> +\t.disable = aspeed_clk_disable,\n> +\t.is_enabled = aspeed_clk_is_enabled,\n> +};\n> +\n> +static struct clk_hw *aspeed_clk_hw_register_gate(struct device *dev,\n> +\t\tconst char *name, const char *parent_name, unsigned long flags,\n> +\t\tstruct regmap *map, u8 clock_idx, u8 reset_idx,\n> +\t\tu8 clk_gate_flags, spinlock_t *lock)\n> +{\n> +\tstruct aspeed_clk_gate *gate;\n> +\tstruct clk_init_data init;\n> +\tstruct clk_hw *hw;\n> +\tint ret;\n> +\n> +\tgate = kzalloc(sizeof(*gate), GFP_KERNEL);\n> +\tif (!gate)\n> +\t\treturn ERR_PTR(-ENOMEM);\n> +\n> +\tinit.name = name;\n> +\tinit.ops = &aspeed_clk_gate_ops;\n> +\tinit.flags = flags | CLK_IS_BASIC;\n\nPlease drop CLK_IS_BASIC.\n\n> +\tinit.parent_names = parent_name ? &parent_name : NULL;\n> +\tinit.num_parents = parent_name ? 1 : 0;\n> +\n> +\tgate->map = map;\n> +\tgate->clock_idx = clock_idx;\n> +\tgate->reset_idx = reset_idx;\n> +\tgate->flags = clk_gate_flags;\n> +\tgate->lock = lock;\n> +\tgate->hw.init = &init;\n> +\n> +\thw = &gate->hw;\n> +\tret = clk_hw_register(dev, hw);\n> +\tif (ret) {\n> +\t\tkfree(gate);\n> +\t\thw = ERR_PTR(ret);\n> +\t}\n> +\n> +\treturn hw;\n> +}\n> +\n> static int __init aspeed_clk_probe(struct platform_device *pdev)\n> {\n> \tconst struct aspeed_clk_soc_data *soc_data;\n> @@ -200,6 +302,7 @@ static int __init aspeed_clk_probe(struct platform_device *pdev)\n> \tstruct regmap *map;\n> \tstruct clk_hw *hw;\n> \tu32 val, rate;\n> +\tint i;\n> \n> \tmap = syscon_node_to_regmap(dev->of_node);\n> \tif (IS_ERR(map)) {\n> @@ -269,6 +372,31 @@ static int __init aspeed_clk_probe(struct platform_device *pdev)\n> \t\t\t&aspeed_clk_lock);\n> \taspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;\n> \n> +\t/* There are a number of clocks that not included in this driver as\n\nNeeds a /* before comment text starts. Also, TODO?\n\n> +\t * more information is required:\n> +\t * D2-PLL\n> +\t * D-PLL\n> +\t * YCLK\n> +\t * RGMII\n> +\t * RMII\n> +\t * UART[1..5] clock source mux\n> +\t */\n> +\n> +\tfor (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) {\n> +\t\tconst struct aspeed_gate_data *gd;\n> +\n> +\t\tgd = &aspeed_gates[i];\n> +\t\taspeed_clk_data->hws[ASPEED_CLK_GATES + i] =\n> +\t\t\taspeed_clk_hw_register_gate(NULL, gd->name,\n\nPass device?\n\n> +\t\t\t\t\t gd->parent_name,\n> +\t\t\t\t\t gd->flags,\n> +\t\t\t\t\t map,\n> +\t\t\t\t\t gd->clock_idx,\n> +\t\t\t\t\t gd->reset_idx,\n> +\t\t\t\t\t CLK_GATE_SET_TO_DISABLE,\n> +\t\t\t\t\t &aspeed_clk_lock);","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778625,"web_url":"http://patchwork.ozlabs.org/comment/1778625/","msgid":"<20171002213958.GR457@codeaurora.org>","list_archive_url":null,"date":"2017-10-02T21:39:58","subject":"Re: [PATCH v2 2/5] clk: aspeed: Register core clocks","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/21, Joel Stanley wrote:\n> @@ -112,9 +115,137 @@ static const struct aspeed_gate_data aspeed_gates[] __initconst = {\n> \t/* 31: reserved */\n> };\n> \n> +static const struct clk_div_table ast2400_div_table[] = {\n> +\t{ 0x0, 2 },\n> +\t{ 0x1, 4 },\n> +\t{ 0x2, 6 },\n> +\t{ 0x3, 8 },\n> +\t{ 0x4, 10 },\n> +\t{ 0x5, 12 },\n> +\t{ 0x6, 14 },\n> +\t{ 0x7, 16 },\n> +\t{ 0 }\n> +};\n> +\n> +static const struct clk_div_table ast2500_div_table[] = {\n> +\t{ 0x0, 4 },\n> +\t{ 0x1, 8 },\n> +\t{ 0x2, 12 },\n> +\t{ 0x3, 16 },\n> +\t{ 0x4, 20 },\n> +\t{ 0x5, 24 },\n> +\t{ 0x6, 28 },\n> +\t{ 0x7, 32 },\n> +\t{ 0 }\n> +};\n> +\n> +static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n> +{\n> +\tunsigned int mult, div;\n> +\n> +\tif (val & BIT(20)) {\n\n#define for these BIT() things please. Or a comment, but #define\nis probably better. Just improves readability.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"kV80GcAm\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"iEi3UMZY\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"iEi3UMZY\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y5bF25BJFz9t4X\n\tfor ;\n\tTue, 3 Oct 2017 08:40:38 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dz8Rr-0008I0-Dm; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778734,"web_url":"http://patchwork.ozlabs.org/comment/1778734/","msgid":"","list_archive_url":null,"date":"2017-10-03T05:47:17","subject":"Re: [PATCH v2 4/5] clk: aspeed: Register gated clocks","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"On Tue, Oct 3, 2017 at 7:07 AM, Stephen Boyd wrote:\n> On 09/21, Joel Stanley wrote:\n>> The majority of the clocks in the system are gates paired with a reset\n>> controller that holds the IP in reset.\n>>\n>> This borrows from clk_hw_register_gate, but registers two 'gates', one\n>> to control the clock enable register and the other to control the reset\n>> IP. This allows us to enforce the ordering:\n>>\n>> 1. Place IP in reset\n>> 2. Enable clock\n>> 3. Delay\n>> 4. Release reset\n>>\n>> There are some gates that do not have an associated reset; these are\n>> handled by using -1 as the index for the reset.\n>\n> Half of these aren't clks, but reset bits? Perhaps you should\n> register power domains for these things and then have the power\n> domain assert the reset, enable the clock, delay, and then\n> release the reset in the poweron callback. Then device drivers\n> don't have to be aware of the ordering, and you can keep\n> enforcing the ordering in one place, but we don't have to make\n> fake gates and shoehorn the sequence into the clk framework.\n\nI had a look. We've got 24 gates being registered, and half are just\ngate+reset pairs, while the other half are both. Some of them have\nclocks with divisors upstream of the gate, so in those cases we do\ncare what the rate is. For the others they are simply bringing the IP\nonline.\n\nNote that we don't have drivers for all of the peripherals, so things\nmay change once those drivers are written.\n\nI hadn't looked into the power domain stuff - when I brought this up\non the list recently Philip suggested that this should be contained in\na clk driver, so that's the direction we went:\n\n http://www.spinics.net/lists/linux-clk/msg18733.html\n\nCheers,\n\nJoel","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"LM4vGGJj\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"R8a6ZCfE\"; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1778735,"web_url":"http://patchwork.ozlabs.org/comment/1778735/","msgid":"","list_archive_url":null,"date":"2017-10-03T05:48:00","subject":"Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register\n\tPLLs","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote:\n> On 09/21, Joel Stanley wrote:\n>> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n>> + /*\n>> + * Memory controller (M-PLL) PLL. This clock is configured by the\n>> + * bootloader, and is exposed to Linux as a read-only clock rate.\n>> + */\n>> + regmap_read(map, ASPEED_MPLL_PARAM, &val);\n>> + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = aspeed_calc_pll(\"mpll\", val);\n>> +\n>> + /* SD/SDIO clock divider (TODO: There's a gate too) */\n>> + hw = clk_hw_register_divider_table(NULL, \"sdio\", \"hpll\", 0,\n>\n> Please pass your dev pointer here from the platform device.\n>\n>> + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,\n>> + div_table,\n>> + &aspeed_clk_lock);\n>\n> And check for errors? Perhaps use devm_clk_hw_regsiter() APIs and\n> construct the dividers and muxes directly instead of using the\n> basic type registration APIs.\n\nDo you think that devm_ is overkill, given we will never unload this driver?\n\nCan you explain why you suggest to construct the structures directly\ninstead of using the APIs?\n\nI had a read of the basic type registration functions, and the\nrelevant failure paths are memory allocation failures. If we're out of\nmemory that early in boot then things have gone pretty bad.\n\nI can add checks for null and bail out; I don't think there's value in\nfreeing the allocated memory: if a system can't load it's clock driver\nthen it's super hosed.\n\nThanks for the review. I fixed all of the other things you mentioned.\n\nCheers,\n\nJoel","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"aaAdtIWy\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"qcih9EH1\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y5p4n02Hbz9t48\n\tfor ;\n\tTue, 3 Oct 2017 16:49:13 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dzG4j-0000tg-7l; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1780126,"web_url":"http://patchwork.ozlabs.org/comment/1780126/","msgid":"<20171004211820.GX457@codeaurora.org>","list_archive_url":null,"date":"2017-10-04T21:18:20","subject":"Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register\n\tPLLs","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 10/03, Joel Stanley wrote:\n> On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote:\n> > On 09/21, Joel Stanley wrote:\n> >> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n> >> + /*\n> >> + * Memory controller (M-PLL) PLL. This clock is configured by the\n> >> + * bootloader, and is exposed to Linux as a read-only clock rate.\n> >> + */\n> >> + regmap_read(map, ASPEED_MPLL_PARAM, &val);\n> >> + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = aspeed_calc_pll(\"mpll\", val);\n> >> +\n> >> + /* SD/SDIO clock divider (TODO: There's a gate too) */\n> >> + hw = clk_hw_register_divider_table(NULL, \"sdio\", \"hpll\", 0,\n> >\n> > Please pass your dev pointer here from the platform device.\n> >\n> >> + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,\n> >> + div_table,\n> >> + &aspeed_clk_lock);\n> >\n> > And check for errors? Perhaps use devm_clk_hw_regsiter() APIs and\n> > construct the dividers and muxes directly instead of using the\n> > basic type registration APIs.\n> \n> Do you think that devm_ is overkill, given we will never unload this driver?\n\nIs probe defer going to happen? Even if unload can't happen,\nprobe defer is a concern unless that is also ruled out.\n\n> \n> Can you explain why you suggest to construct the structures directly\n> instead of using the APIs?\n\nThere aren't devm APIs for some of these basic clk type\nregistration functions.\n\n> \n> I had a read of the basic type registration functions, and the\n> relevant failure paths are memory allocation failures. If we're out of\n> memory that early in boot then things have gone pretty bad.\n> \n> I can add checks for null and bail out; I don't think there's value in\n> freeing the allocated memory: if a system can't load it's clock driver\n> then it's super hosed.\n\nIf we can't proceed without this driver because it's super hosed,\nthen perhaps we need to panic the system on errors here. Should\nbe simple enough to add some error checks and goto panic(\"Things\nare super hosed\").","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"bX5+vCDe\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"Z9gPya4/\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"Z9gPya4/\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y6pg06GqBz9sRq\n\tfor ;\n\tThu, 5 Oct 2017 08:18:50 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dzr42-0003F5-2o; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1780301,"web_url":"http://patchwork.ozlabs.org/comment/1780301/","msgid":"","list_archive_url":null,"date":"2017-10-05T06:22:50","subject":"Re: [PATCH v2 3/5] clk: aspeed: Add platform driver and register\n\tPLLs","submitter":{"id":48628,"url":"http://patchwork.ozlabs.org/api/people/48628/","name":"Joel Stanley","email":"joel@jms.id.au"},"content":"On Thu, Oct 5, 2017 at 6:48 AM, Stephen Boyd wrote:\n> On 10/03, Joel Stanley wrote:\n>> On Tue, Oct 3, 2017 at 6:54 AM, Stephen Boyd wrote:\n>> > On 09/21, Joel Stanley wrote:\n>> >> @@ -160,6 +191,104 @@ static struct clk_hw *aspeed_calc_pll(const char *name, u32 val)\n>> >> + /*\n>> >> + * Memory controller (M-PLL) PLL. This clock is configured by the\n>> >> + * bootloader, and is exposed to Linux as a read-only clock rate.\n>> >> + */\n>> >> + regmap_read(map, ASPEED_MPLL_PARAM, &val);\n>> >> + aspeed_clk_data->hws[ASPEED_CLK_MPLL] = aspeed_calc_pll(\"mpll\", val);\n>> >> +\n>> >> + /* SD/SDIO clock divider (TODO: There's a gate too) */\n>> >> + hw = clk_hw_register_divider_table(NULL, \"sdio\", \"hpll\", 0,\n>> >\n>> > Please pass your dev pointer here from the platform device.\n>> >\n>> >> + scu_base + ASPEED_CLK_SELECTION, 12, 3, 0,\n>> >> + div_table,\n>> >> + &aspeed_clk_lock);\n>> >\n>> > And check for errors? Perhaps use devm_clk_hw_regsiter() APIs and\n>> > construct the dividers and muxes directly instead of using the\n>> > basic type registration APIs.\n>>\n>> Do you think that devm_ is overkill, given we will never unload this driver?\n>\n> Is probe defer going to happen? Even if unload can't happen,\n> probe defer is a concern unless that is also ruled out.\n\nAs I understand it, I will only get an EPROBE_DEFER if I'm requesting\nsomething from another driver?\n\nIf that's the case then we can rule that out.\n\n>>\n>> Can you explain why you suggest to construct the structures directly\n>> instead of using the APIs?\n>\n> There aren't devm APIs for some of these basic clk type\n> registration functions.\n>\n>>\n>> I had a read of the basic type registration functions, and the\n>> relevant failure paths are memory allocation failures. If we're out of\n>> memory that early in boot then things have gone pretty bad.\n>>\n>> I can add checks for null and bail out; I don't think there's value in\n>> freeing the allocated memory: if a system can't load it's clock driver\n>> then it's super hosed.\n>\n> If we can't proceed without this driver because it's super hosed,\n> then perhaps we need to panic the system on errors here. Should\n> be simple enough to add some error checks and goto panic(\"Things\n> are super hosed\").\n\nOkay. I added checks in v4. Does that look ok you you?\n\nCheers,\n\nJoel","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"hlIxy1VC\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"cxpRfaor\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y72lg0R8Sz9t4X\n\tfor ;\n\tThu, 5 Oct 2017 17:23:43 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dzzZL-0005va-1M; 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