[{"id":1772434,"web_url":"http://patchwork.ozlabs.org/comment/1772434/","msgid":"","list_archive_url":null,"date":"2017-09-21T06:11:44","subject":"Re: [Qemu-devel] [PATCH v11 0/5] Add support for Smartfusion2 SoC","submitter":{"id":64324,"url":"http://patchwork.ozlabs.org/api/people/64324/","name":"sundeep subbaraya","email":"sundeep.lkml@gmail.com"},"content":"Thanks Philippe :)\n\nSundeep\n\nOn Thu, Sep 21, 2017 at 1:47 AM, Philippe Mathieu-Daudé \nwrote:\n\n> Hi Peter,\n>\n> Now than Igor's patch landed, I respin Sundeep's series updating it to work\n> after the \"arm: drop intermediate cpu_model -> cpu type parsing and use cpu\n> type directly\" patch.\n>\n> v11:\n> - msf2-soc.c: add a check for null m3clk\n> - msf2-soc.c, msf2-som.c: drop cpu_model to directly use cpu type\n>\n> --\n>\n> Sundeep original cover:\n>\n> I am trying to add Smartfusion2 SoC.\n> SoC is from Microsemi and System on Module(SOM)\n> board is from Emcraft systems. Smartfusion2 has hardened\n> Microcontroller(Cortex-M3)based Sub System and FPGA fabric.\n> At the moment only system timer, sysreg and SPI\n> controller are modelled.\n>\n> Testing:\n> ./arm-softmmu/qemu-system-arm -M emcraft-sf2 -serial mon:stdio \\\n> -kernel u-boot.bin -display none -drive file=spi.bin,if=mtd,format=raw\n>\n> Binaries u-boot.bin and spi.bin are at:\n> https://github.com/Subbaraya-Sundeep/qemu-test-binaries.git\n>\n> U-boot is from Emcraft with modified\n> - SPI driver not to use PDMA.\n> - ugly hack to pass dtb to kernel in r1.\n> @\n> https://github.com/Subbaraya-Sundeep/emcraft-uboot-sf2.git\n>\n> Linux is 4.5 linux with Smartfusion2 SoC dts and clocksource\n> driver added by myself @\n> https://github.com/Subbaraya-Sundeep/linux.git\n>\n> v10:\n> Added msf2_sysreg_realize in msf2-sysreg.c\n> modified unimplemented devices names:\n> pdma->dma and hpdma->hs-dma\n> used uint8_t for apb divisors properties\n> simplified msf2_divbits() using ctz32()\n>\n> v9:\n> used trace instead of DB_PRINT in msf2-sysreg.c\n> used LOG_UNIMP for non guest errors in msf2-sysreg.c\n> added unimplemented devices in msf2-soc.c\n> removed .alias suffix in alias memory region name for eNVM\n> removed mc->ignore_memory_transaction_failures in msf2-som.c\n>\n> v8:\n> memory_region_init_ram to memory_region_init_rom in soc\n> %s/emcraft_sf2_init/emcraft_sf2_s2s010_init/g in som\n> Added mc->ignore_memory_transaction_failures = true in som\n> as per latest commit.\n> Code simplifications as suggested by Alistair in sysreg and ssi.\n>\n> v7:\n> Removed vmstate_register_ram_global as per latest commit\n> Moved header files to C which are local to C source files\n> Removed abort() from msf2-sysreg.c\n> Added VMStateDescription in mss-timer.c\n>\n> v6:\n> Moved some defines from header files to source files\n> Added properties m3clk, apb0div, apb0div1 properties\n> to soc.\n> Added properties apb0divisor, apb1divisor to sysreg\n> Update system_clock_source in msf2-soc.c\n> Changed machine name smartfusion2-som->emcraft-sf2\n>\n> v5\n> As per Philippe comments:\n> Added abort in Sysreg if guest tries to remap memory\n> other than default mapping.\n> Use of CONFIG_MSF2 in Makefile for soc.c\n> Fixed incorrect logic in timer model.\n> Renamed msf2-timer.c -> mss-timer.c\n> msf2-spi.c -> mss-spi.c also type names\n> Renamed function msf2_init->emcraft_sf2_init in msf2-som.c\n> Added part-name,eNVM-size,eSRAM-size,pclk0 and pclk1\n> properties to soc.\n> Pass soc part-name,memory size and clock rate properties from som.\n> v4:\n> Fixed build failure by using PRIx macros.\n> v3:\n> Added SoC file and board file as per Alistair comments.\n> v2:\n> Added SPI controller so that u-boot loads kernel from spi flash.\n> v1:\n> Initial patch set with timer and sysreg\n>\n> Thanks,\n> Sundeep\n>\n> Subbaraya Sundeep (5):\n> msf2: Add Smartfusion2 System timer\n> msf2: Microsemi Smartfusion2 System Register block\n> msf2: Add Smartfusion2 SPI controller\n> msf2: Add Smartfusion2 SoC\n> msf2: Add Emcraft's Smartfusion2 SOM kit\n>\n> default-configs/arm-softmmu.mak | 1 +\n> include/hw/arm/msf2-soc.h | 67 +++++++\n> include/hw/misc/msf2-sysreg.h | 77 ++++++++\n> include/hw/ssi/mss-spi.h | 58 ++++++\n> include/hw/timer/mss-timer.h | 64 +++++++\n> hw/arm/msf2-soc.c | 238 +++++++++++++++++++++++\n> hw/arm/msf2-som.c | 105 +++++++++++\n> hw/misc/msf2-sysreg.c | 160 ++++++++++++++++\n> hw/ssi/mss-spi.c | 404 ++++++++++++++++++++++++++++++\n> ++++++++++\n> hw/timer/mss-timer.c | 289 ++++++++++++++++++++++++++++\n> hw/arm/Makefile.objs | 1 +\n> hw/misc/Makefile.objs | 1 +\n> hw/misc/trace-events | 5 +\n> hw/ssi/Makefile.objs | 1 +\n> hw/timer/Makefile.objs | 1 +\n> 15 files changed, 1472 insertions(+)\n> create mode 100644 include/hw/arm/msf2-soc.h\n> create mode 100644 include/hw/misc/msf2-sysreg.h\n> create mode 100644 include/hw/ssi/mss-spi.h\n> create mode 100644 include/hw/timer/mss-timer.h\n> create mode 100644 hw/arm/msf2-soc.c\n> create mode 100644 hw/arm/msf2-som.c\n> create mode 100644 hw/misc/msf2-sysreg.c\n> create mode 100644 hw/ssi/mss-spi.c\n> create mode 100644 hw/timer/mss-timer.c\n>\n> --\n> 2.14.1\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-Content-Filtered-By":"Mailman/MimeDel 2.1.21","Subject":"Re: [Qemu-devel] [PATCH v11 0/5] Add support for Smartfusion2 SoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Maydell ,\n\tPeter Crosthwaite ,\n\tAlistair Francis ,\n\tQEMU Developers , qemu-arm , \n\tIgor Mammedov ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1772979,"web_url":"http://patchwork.ozlabs.org/comment/1772979/","msgid":"","list_archive_url":null,"date":"2017-09-21T16:33:23","subject":"Re: [Qemu-devel] [PATCH v11 0/5] Add support for Smartfusion2 SoC","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"content":"On 20 September 2017 at 21:17, Philippe Mathieu-Daudé wrote:\n> Hi Peter,\n>\n> Now than Igor's patch landed, I respin Sundeep's series updating it to work\n> after the \"arm: drop intermediate cpu_model -> cpu type parsing and use cpu\n> type directly\" patch.\n>\n> v11:\n> - msf2-soc.c: add a check for null m3clk\n> - msf2-soc.c, msf2-som.c: drop cpu_model to directly use cpu type\n>\n> --\n\nApplied to target-arm.next.\n\nThanks to Sundeep for being so patient with our code review process,\nand to Philippe and Alistair for doing the review and shepherding\nthe series through it.\n\nthank\n-- PMM","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2a00:1450:400c:c09::232","Subject":"Re: [Qemu-devel] [PATCH v11 0/5] Add support for Smartfusion2 SoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Crosthwaite ,\n\tAlistair Francis ,\n\tQEMU Developers ,\n\tSubbaraya Sundeep ,\n\tqemu-arm , Igor Mammedov ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}},{"id":1774320,"web_url":"http://patchwork.ozlabs.org/comment/1774320/","msgid":"","list_archive_url":null,"date":"2017-09-24T23:39:28","subject":"Re: [Qemu-devel] [PATCH v11 0/5] Add support for Smartfusion2 SoC","submitter":{"id":64324,"url":"http://patchwork.ozlabs.org/api/people/64324/","name":"sundeep subbaraya","email":"sundeep.lkml@gmail.com"},"content":"Thanks Peter, Philippe and Alistair :)\nSundeep\n\nOn Thu, Sep 21, 2017 at 10:03 PM, Peter Maydell \nwrote:\n\n> On 20 September 2017 at 21:17, Philippe Mathieu-Daudé \n> wrote:\n> > Hi Peter,\n> >\n> > Now than Igor's patch landed, I respin Sundeep's series updating it to\n> work\n> > after the \"arm: drop intermediate cpu_model -> cpu type parsing and use\n> cpu\n> > type directly\" patch.\n> >\n> > v11:\n> > - msf2-soc.c: add a check for null m3clk\n> > - msf2-soc.c, msf2-som.c: drop cpu_model to directly use cpu type\n> >\n> > --\n>\n> Applied to target-arm.next.\n>\n> Thanks to Sundeep for being so patient with our code review process,\n> and to Philippe and Alistair for doing the review and shepherding\n> the series through it.\n>\n> thank\n> -- PMM\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; 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charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","X-Content-Filtered-By":"Mailman/MimeDel 2.1.21","Subject":"Re: [Qemu-devel] [PATCH v11 0/5] Add support for Smartfusion2 SoC","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Peter Crosthwaite , Alistair Francis\n\t, \tQEMU Developers ,\n\t=?utf-8?q?Philippe_Mathieu-D?= =?utf-8?b?YXVkw6k=?= ,\n\tqemu-arm , Igor Mammedov ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"}}]