[{"id":1772632,"web_url":"http://patchwork.ozlabs.org/comment/1772632/","msgid":"<5172c185-c6b5-49c3-cf0a-c3e073459346@synopsys.com>","list_archive_url":null,"date":"2017-09-21T09:39:42","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":68387,"url":"http://patchwork.ozlabs.org/api/people/68387/","name":"Jose Abreu","email":"Jose.Abreu@synopsys.com"},"content":"Hi Jernej,\n\nOn 20-09-2017 21:01, Jernej Skrabec wrote:\n> [added media mailing list due to CEC question]\n>\n> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only\n> video and CEC functionality is supported. Audio needs more tweaks.\n>\n> Series is based on the H3 DE2 patch series available on mailing list:\n> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s&e= \n> (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n>\n> Patch 1 adds support for polling plug detection since custom PHY used here\n> doesn't support HPD interrupt.\n>\n> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits\n> same issues as HDMI controller used in iMX6 SoCs.\n>\n> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n>\n> Patch 4 adds dt bindings documentation.\n>\n> Patch 5 adds actual H3 HDMI glue driver.\n>\n> Patch 6 and 7 add HDMI node to DT and enable it where needed.\n>\n> Allwinner used DW HDMI controller in a non standard way:\n> - register offsets obfuscation layer, which can fortunately be turned off\n> - register read lock, which has to be disabled by magic number\n> - custom PHY, which have to be initialized before DW HDMI controller\n> - non standard clocks\n> - no HPD interrupt\n>\n> Because of that, I have two questions:\n> - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n> mainly concerned about invalidating CEC address here.\n\nYou mean you get no interrupt when HPD status changes? Hans can\nanswer this better but then you will need to invalidate the cec\nphysical address yourself because right now its invalidated in\nthe dw-hdmi irq handler (see dw_hdmi_irq()).\n\n> - PHY has to be initialized before DW HDMI controller to disable offset\n> obfuscation and read lock among other things. This means that all clocks have\n> to be enabled in glue driver. This poses a problem, since when using\n> component model, dw-hdmi bridge uses drvdata for it's own private data and\n> prevents glue layer to pass a pointer to unbind function, where clocks should\n> be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks\n> are also not disabled when unbind callback is called. I noticed that when H3\n> SoC is shutdown, HDMI output is still enabled and lastest image is shown on\n> monitor until it is unplugged from power supply. Is there any simple solution\n> to this?\n\nI don't know if you can use an empty platform device created with\nplatform_device_alloc(). Perhaps it would be better fix this in\nthe dw-hdmi driver. I see two solutions:\n\n - Either you return the dw-hdmi private structure in the bind\ncallback, store it and pass it in the unbind\n - Or, you pass your own private data to the dw-hdmi bind, the\ndw-hdmi stores it and you just create a public function in the\ndw-hdmi driver called like dw_hdmi_get_auxdata(struct device\n*dev) which returns your private data.\n\nI think first option is nice, maybe anyone else can suggest\nsomething better?\n\nBest regards,\nJose Miguel Abreu\n\n>\n> Chen-Yu,\n> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I think\n> it is safe to assume that divider in HDMI clock doesn't have any effect.\n>\n> Branch based on linux-next from 1. September with integrated patches is\n> available here:\n> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_jernejsk_linux-2D1_tree_h3-5Fhdmi-5Frfc&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=lDAnd3egsc2sxqVM-Ya_Me9ozWXKWvxxvsdV3Jn3vpA&e= \n>\n> Some additonal info about H3 HDMI:\n> https://urldefense.proofpoint.com/v2/url?u=https-3A__linux-2Dsunxi.org_DWC-5FHDMI-5FController&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=d9iEgk23RCLJL4oXJ4kkt6NyYK90_vFy0mCD3WauJDk&e= \n>\n> Thanks to Jens Kuske, who figured out that it is actually DW HDMI controller\n> and mapped scrambled register offsets to original ones.\n>\n> Icenowy Zheng (1):\n> ARM: sun8i: h3: Add DesignWare HDMI controller node\n>\n> Jernej Skrabec (6):\n> drm: bridge: Enable polling hpd event in dw_hdmi\n> drm: bridge: Enable workaround in dw_hdmi for v1.32a\n> clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock\n> dt-bindings: Document Allwinner DWC HDMI TX node\n> drm: sun4i: Add a glue for the DesignWare HDMI controller in H3\n> ARM: sun8i: h3: Enable HDMI output on H3 boards\n>\n> .../bindings/display/sunxi/sun4i-drm.txt | 158 ++++++-\n> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3.dtsi | 5 +\n> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 36 ++\n> drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-\n> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +-\n> drivers/gpu/drm/sun4i/Kconfig | 9 +\n> drivers/gpu/drm/sun4i/Makefile | 1 +\n> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 500 +++++++++++++++++++++\n> 15 files changed, 950 insertions(+), 6 deletions(-)\n> create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.4.0","MIME-Version":"1.0","In-Reply-To":"<20170920200124.20457-1-jernej.skrabec@siol.net>","X-Originating-IP":"[10.107.19.118]","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170921_024032_065705_C7099CDC ","X-CRM114-Status":"GOOD ( 22.76 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno trust [198.182.47.9 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, narmstrong@baylibre.com,\n\tlinux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,\n\tlinux-sunxi@googlegroups.com, hans.verkuil@cisco.com,\n\tLaurent.pinchart@ideasonboard.com, linux-media@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\ticenowy@aosc.io","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1772639,"web_url":"http://patchwork.ozlabs.org/comment/1772639/","msgid":"<68fa56f8-9878-12d0-1696-4393abe45db5@cisco.com>","list_archive_url":null,"date":"2017-09-21T09:59:27","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":26081,"url":"http://patchwork.ozlabs.org/api/people/26081/","name":"Hans Verkuil (hansverk)","email":"hansverk@cisco.com"},"content":"On 09/21/17 11:39, Jose Abreu wrote:\n> Hi Jernej,\n> \n> On 20-09-2017 21:01, Jernej Skrabec wrote:\n>> [added media mailing list due to CEC question]\n>>\n>> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only\n>> video and CEC functionality is supported. Audio needs more tweaks.\n>>\n>> Series is based on the H3 DE2 patch series available on mailing list:\n>> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s&e= \n>> (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n>>\n>> Patch 1 adds support for polling plug detection since custom PHY used here\n>> doesn't support HPD interrupt.\n>>\n>> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits\n>> same issues as HDMI controller used in iMX6 SoCs.\n>>\n>> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n>>\n>> Patch 4 adds dt bindings documentation.\n>>\n>> Patch 5 adds actual H3 HDMI glue driver.\n>>\n>> Patch 6 and 7 add HDMI node to DT and enable it where needed.\n>>\n>> Allwinner used DW HDMI controller in a non standard way:\n>> - register offsets obfuscation layer, which can fortunately be turned off\n>> - register read lock, which has to be disabled by magic number\n>> - custom PHY, which have to be initialized before DW HDMI controller\n>> - non standard clocks\n>> - no HPD interrupt\n>>\n>> Because of that, I have two questions:\n>> - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n>> mainly concerned about invalidating CEC address here.\n> \n> You mean you get no interrupt when HPD status changes? Hans can\n> answer this better but then you will need to invalidate the cec\n> physical address yourself because right now its invalidated in\n> the dw-hdmi irq handler (see dw_hdmi_irq()).\n\nThat's correct. When the HPD goes low you need to call cec_notifier_phys_addr_invalidate()\nto invalidate the physical address. This is not terribly time sensitive, i.e.\nchecking this once a second would be quick enough.\n\nRegards,\n\n\tHans","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"Wbwmc/bx\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=cisco.com header.i=@cisco.com\n\theader.b=\"cbfdwJVu\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xyXCh3Ln7z9t49\n\tfor ;\n\tThu, 21 Sep 2017 20:00:00 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duyGy-0007Sw-UL; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776649,"web_url":"http://patchwork.ozlabs.org/comment/1776649/","msgid":"<20170927215638.tjbllqq2twdvuivj@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-27T21:56:38","subject":"Re: [RESEND RFC PATCH 4/7] dt-bindings: Document Allwinner DWC HDMI\n\tTX node","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Wed, Sep 20, 2017 at 10:01:21PM +0200, Jernej Skrabec wrote:\n> Add documentation about Allwinner DWC HDMI TX node, found in H3 SoC.\n> \n> Signed-off-by: Jernej Skrabec \n> ---\n> .../bindings/display/sunxi/sun4i-drm.txt | 158 ++++++++++++++++++++-\n> 1 file changed, 157 insertions(+), 1 deletion(-)\n> \n> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt\n> index 92512953943e..cb6aee5c486f 100644\n> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt\n> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt\n> @@ -60,6 +60,40 @@ Required properties:\n> first port should be the input endpoint. The second should be the\n> output, usually to an HDMI connector.\n> \n> +DWC HDMI TX Encoder\n> +-----------------------------\n> +\n> +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP\n> +with Allwinner's own PHY IP. It supports audio and video outputs and CEC.\n> +\n> +These DT bindings follow the Synopsys DWC HDMI TX bindings defined in\n> +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the\n> +following device-specific properties.\n> +\n> +Required properties:\n> +\n> + - compatible: value must be one of:\n> + * \"allwinner,sun8i-h3-dw-hdmi\"\n> + - reg: two pairs of base address and size of memory-mapped region, first\n> + for controller and second for PHY\n> + registers.\n> + - reg-io-width: See dw_hdmi.txt. Shall be 1.\n> + - interrupts: HDMI interrupt number\n> + - clocks: phandles to the clocks feeding the HDMI encoder\n> + * iahb: the HDMI interface clock\n> + * isfr: the HDMI module clock\n> + * ddc: the HDMI ddc clock\n> + - clock-names: the clock names mentioned above\n> + - resets: phandles to the reset controllers driving the encoder\n> + * hdmi: the reset line for the HDMI\n> + * ddc: the reset line for the DDC\n> + - reset-names: the reset names mentioned above\n> +\n> + - ports: A ports node with endpoint definitions as defined in\n> + Documentation/devicetree/bindings/media/video-interfaces.txt. The\n> + first port should be the input endpoint. The second should be the\n> + output, usually to an HDMI connector.\n> +\n> TV Encoder\n> ----------\n> \n> @@ -255,7 +289,7 @@ Required properties:\n> - allwinner,pipelines: list of phandle to the display engine\n> frontends (DE 1.0) or mixers (DE 2.0) available.\n> \n> -Example:\n> +Example 1:\n> \n> panel: panel {\n> \tcompatible = \"olimex,lcd-olinuxino-43-ts\";\n> @@ -455,3 +489,125 @@ display-engine {\n> \tcompatible = \"allwinner,sun5i-a13-display-engine\";\n> \tallwinner,pipelines = <&fe0>;\n> };\n> +\n> +Example 2:\n> +\n> +connector {\n> +\tcompatible = \"hdmi-connector\";\n> +\ttype = \"a\";\n> +\n> +\tport {\n> +\t\thdmi_con_in: endpoint {\n> +\t\t\tremote-endpoint = <&hdmi_out_con>;\n> +\t\t};\n> +\t};\n> +};\n> +\n> +de: display-engine {\n> +\tcompatible = \"allwinner,sun8i-h3-display-engine\";\n> +\tallwinner,pipelines = <&mixer0>;\n> +};\n> +\n> +hdmi: hdmi@1ee0000 {\n> +\tcompatible = \"allwinner,h3-dw-hdmi\";\n> +\treg = <0x01ee0000 0x10000>,\n> +\t <0x01ef0000 0x10000>;\n> +\treg-io-width = <1>;\n> +\tinterrupts = ;\n> +\tclocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI>,\n> +\t\t <&ccu CLK_HDMI_DDC>;\n> +\tclock-names = \"iahb\", \"isfr\", \"ddc\";\n> +\tresets = <&ccu RST_BUS_HDMI0>, <&ccu RST_BUS_HDMI1>;\n> +\treset-names = \"hdmi\", \"ddc\";\n> +\n> +\tports {\n> +\t\t#address-cells = <1>;\n> +\t\t#size-cells = <0>;\n> +\n> +\t\thdmi_in: port@0 {\n> +\t\t\t#address-cells = <1>;\n> +\t\t\t#size-cells = <0>;\n> +\t\t\treg = <0>;\n> +\n> +\t\t\thdmi_in_tcon0: endpoint@0 {\n> +\t\t\t\treg = <0>;\n\nYou don't need reg when there's only one.\n\nOtherwise,\n\nAcked-by: Rob Herring ","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777906,"web_url":"http://patchwork.ozlabs.org/comment/1777906/","msgid":"<51c50157-6794-852b-f89d-647b9cf06ef2@ozlabs.ru>","list_archive_url":null,"date":"2017-09-30T11:58:03","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":7621,"url":"http://patchwork.ozlabs.org/api/people/7621/","name":"Alexey Kardashevskiy","email":"aik@ozlabs.ru"},"content":"On 21/09/17 06:01, Jernej Skrabec wrote:\n> [added media mailing list due to CEC question]\n> \n> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only\n> video and CEC functionality is supported. Audio needs more tweaks.\n> \n> Series is based on the H3 DE2 patch series available on mailing list:\n> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.html\n> (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n> \n> Patch 1 adds support for polling plug detection since custom PHY used here\n> doesn't support HPD interrupt.\n> \n> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits\n> same issues as HDMI controller used in iMX6 SoCs.\n> \n> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n> \n> Patch 4 adds dt bindings documentation.\n> \n> Patch 5 adds actual H3 HDMI glue driver.\n> \n> Patch 6 and 7 add HDMI node to DT and enable it where needed.\n> \n> Allwinner used DW HDMI controller in a non standard way:\n> - register offsets obfuscation layer, which can fortunately be turned off\n> - register read lock, which has to be disabled by magic number\n> - custom PHY, which have to be initialized before DW HDMI controller\n> - non standard clocks\n> - no HPD interrupt\n> \n> Because of that, I have two questions:\n> - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n> mainly concerned about invalidating CEC address here.\n> - PHY has to be initialized before DW HDMI controller to disable offset\n> obfuscation and read lock among other things. This means that all clocks have\n> to be enabled in glue driver. This poses a problem, since when using\n> component model, dw-hdmi bridge uses drvdata for it's own private data and\n> prevents glue layer to pass a pointer to unbind function, where clocks should\n> be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks\n> are also not disabled when unbind callback is called. I noticed that when H3\n> SoC is shutdown, HDMI output is still enabled and lastest image is shown on\n> monitor until it is unplugged from power supply. Is there any simple solution\n> to this?\n> \n> Chen-Yu,\n> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I think\n> it is safe to assume that divider in HDMI clock doesn't have any effect.\n> \n> Branch based on linux-next from 1. September with integrated patches is\n> available here:\n> https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc\n\n\nOut of curiosity I tried this one and got:\n\n\n\n[ 0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO\n[ 0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver\n[ 0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi PIO driver\n[ 0.148009] ------------[ cut here ]------------\n[ 0.148035] WARNING: CPU: 0 PID: 1 at\ndrivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274\n[ 0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted\n4.13.0-rc6-next-20170825-aik-aik #24\n[ 0.148051] Hardware name: Allwinner sun8i Family\n[ 0.148082] [] (unwind_backtrace) from []\n(show_stack+0x10/0x14)\n[ 0.148101] [] (show_stack) from []\n(dump_stack+0x84/0x98)\n[ 0.148117] [] (dump_stack) from [] (__warn+0xe0/0xfc)\n[ 0.148132] [] (__warn) from []\n(warn_slowpath_null+0x20/0x28)\n[ 0.148145] [] (warn_slowpath_null) from []\n(ccu_nm_set_rate+0x1d0/0x274)\n[ 0.148161] [] (ccu_nm_set_rate) from []\n(clk_change_rate+0x19c/0x250)\n[ 0.148175] [] (clk_change_rate) from []\n(clk_core_set_rate_nolock+0x68/0xb0)\n[ 0.148187] [] (clk_core_set_rate_nolock) from []\n(clk_set_rate+0x20/0x30)\n[ 0.148202] [] (clk_set_rate) from []\n(of_clk_set_defaults+0x200/0x364)\n[ 0.148219] [] (of_clk_set_defaults) from []\n(platform_drv_probe+0x18/0xb0)\n[ 0.148233] [] (platform_drv_probe) from []\n(driver_probe_device+0x234/0x2e8)\n[ 0.148246] [] (driver_probe_device) from []\n(__driver_attach+0xb8/0xbc)\n[ 0.148258] [] (__driver_attach) from [","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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\n\tSat, 30 Sep 2017 04:58:12 -0700 (PDT)","Subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","To":"Jernej Skrabec ,\n\tmaxime.ripard@free-electrons.com, wens@csie.org","References":"<20170920200124.20457-1-jernej.skrabec@siol.net>","From":"Alexey Kardashevskiy ","Message-ID":"<51c50157-6794-852b-f89d-647b9cf06ef2@ozlabs.ru>","Date":"Sat, 30 Sep 2017 21:58:03 +1000","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170920200124.20457-1-jernej.skrabec@siol.net>","Content-Language":"en-AU","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170930_045833_998729_0D2F4222 ","X-CRM114-Status":"GOOD ( 20.68 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2607:f8b0:400e:c00:0:0:0:241 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, narmstrong@baylibre.com,\n\tlinux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,\n\tlinux-sunxi@googlegroups.com, hans.verkuil@cisco.com,\n\tLaurent.pinchart@ideasonboard.com, linux-media@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\ticenowy@aosc.io","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777934,"web_url":"http://patchwork.ozlabs.org/comment/1777934/","msgid":"<34246001.lKHNgTVc0h@jernej-laptop>","list_archive_url":null,"date":"2017-09-30T17:56:19","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":70601,"url":"http://patchwork.ozlabs.org/api/people/70601/","name":"Jernej Škrabec","email":"jernej.skrabec@siol.net"},"content":"Hi,\n\nDne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy \nnapisal(a):\n> On 21/09/17 06:01, Jernej Skrabec wrote:\n> > [added media mailing list due to CEC question]\n> > \n> > This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,\n> > only video and CEC functionality is supported. Audio needs more tweaks.\n> > \n> > Series is based on the H3 DE2 patch series available on mailing list:\n> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.h\n> > tml (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n> > \n> > Patch 1 adds support for polling plug detection since custom PHY used here\n> > doesn't support HPD interrupt.\n> > \n> > Patch 2 enables overflow workaround for v1.32a. This HDMI controller\n> > exhibits same issues as HDMI controller used in iMX6 SoCs.\n> > \n> > Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n> > \n> > Patch 4 adds dt bindings documentation.\n> > \n> > Patch 5 adds actual H3 HDMI glue driver.\n> > \n> > Patch 6 and 7 add HDMI node to DT and enable it where needed.\n> > \n> > Allwinner used DW HDMI controller in a non standard way:\n> > - register offsets obfuscation layer, which can fortunately be turned off\n> > - register read lock, which has to be disabled by magic number\n> > - custom PHY, which have to be initialized before DW HDMI controller\n> > - non standard clocks\n> > - no HPD interrupt\n> > \n> > Because of that, I have two questions:\n> > - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n> > \n> > mainly concerned about invalidating CEC address here.\n> > \n> > - PHY has to be initialized before DW HDMI controller to disable offset\n> > \n> > obfuscation and read lock among other things. This means that all clocks\n> > have to be enabled in glue driver. This poses a problem, since when\n> > using component model, dw-hdmi bridge uses drvdata for it's own private\n> > data and prevents glue layer to pass a pointer to unbind function,\n> > where clocks should be disabled. I noticed same issue in meson DW HDMI\n> > glue driver, where clocks are also not disabled when unbind callback is\n> > called. I noticed that when H3 SoC is shutdown, HDMI output is still\n> > enabled and lastest image is shown on monitor until it is unplugged\n> > from power supply. Is there any simple solution to this?\n> > \n> > Chen-Yu,\n> > TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I\n> > think it is safe to assume that divider in HDMI clock doesn't have any\n> > effect.\n> > \n> > Branch based on linux-next from 1. September with integrated patches is\n> > available here:\n> > https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc\n> \n> Out of curiosity I tried this one and got:\n> \n> \n> \n> [ 0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO\n> [ 0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO\n> driver [ 0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi\n> PIO driver [ 0.148009] ------------[ cut here ]------------\n> [ 0.148035] WARNING: CPU: 0 PID: 1 at\n> drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274\n> [ 0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted\n> 4.13.0-rc6-next-20170825-aik-aik #24\n> [ 0.148051] Hardware name: Allwinner sun8i Family\n> [ 0.148082] [] (unwind_backtrace) from []\n> (show_stack+0x10/0x14)\n> [ 0.148101] [] (show_stack) from []\n> (dump_stack+0x84/0x98)\n> [ 0.148117] [] (dump_stack) from []\n> (__warn+0xe0/0xfc) [ 0.148132] [] (__warn) from []\n> (warn_slowpath_null+0x20/0x28)\n> [ 0.148145] [] (warn_slowpath_null) from []\n> (ccu_nm_set_rate+0x1d0/0x274)\n> [ 0.148161] [] (ccu_nm_set_rate) from []\n> (clk_change_rate+0x19c/0x250)\n> [ 0.148175] [] (clk_change_rate) from []\n> (clk_core_set_rate_nolock+0x68/0xb0)\n> [ 0.148187] [] (clk_core_set_rate_nolock) from []\n> (clk_set_rate+0x20/0x30)\n> [ 0.148202] [] (clk_set_rate) from []\n> (of_clk_set_defaults+0x200/0x364)\n> [ 0.148219] [] (of_clk_set_defaults) from []\n> (platform_drv_probe+0x18/0xb0)\n> [ 0.148233] [] (platform_drv_probe) from []\n> (driver_probe_device+0x234/0x2e8)\n> [ 0.148246] [] (driver_probe_device) from []\n> (__driver_attach+0xb8/0xbc)\n> [ 0.148258] [] (__driver_attach) from [ Unable to handle kernel NULL pointer dereference at virtual address 00000008\n> \n\nPatch for that is already merged upstream and can be found here:\nhttps://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/\ndrivers/clk/sunxi-ng?id=62d212bdb022deeb875f92f6e376c799e3f35eca\n\n> and a bit later:\n> \n> [ 1.995572] Rebooting in 10 seconds..\n\nI'm not sure about that one. Kernel config issue?\n\nRegards,\nJernej\n\n> \n> Orange PI PC, script.bin.OPI-PC_1080p60_hdmi.\n> \n> What do I miss? Thanks.\n> \n> \n> \n> --\n> Alexey","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"FYZtJM2I\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y4GN125c8z9sDB\n\tfor ;\n\tSun, 1 Oct 2017 04:57:05 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dyM0Z-0002YJ-9g; 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q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=6+JOOaSNalikkYQiki5APUSms4Kp0lbZb2YYFeML5E4=;\n\tb=FYZtJM2ImcOsTO\n\tlJRC0ACKBNwmrMOc4XrRM65EhD/bFT6RjOTd+JVyuDmI1FjYwwnPStQtv2wR5HuJ6d/pYnmRIV0A5\n\t30DWGda2KasnGg289UbmMwdfUrH/HW/zsTYAptuV+ihwk0EpVpqkoHLPnQ1LL0RsLeXfiQVHWzwdM\n\tA1FwjVrilH982sGH1V8fL/zkgTDPk/h2cALQL8VBcDVTJWHohYlUL1P1OtjyP1Z2v5DPRCIgEuUqg\n\tA7Ro9xF550n+JFY7a21VUjJT0SV+Z2EwIsOB/aw2Z9aE4ycye4fjqIslHDCElrlcj8bYUh7Cj2OFK\n\to1sQPyZLkYaeVOUscZew==;","X-Virus-Scanned":"amavisd-new at psrvmta12.zcs-production.pri","From":"Jernej =?utf-8?q?=C5=A0krabec?= ","To":"Alexey Kardashevskiy ","Subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","Date":"Sat, 30 Sep 2017 19:56:19 +0200","Message-ID":"<34246001.lKHNgTVc0h@jernej-laptop>","In-Reply-To":"<51c50157-6794-852b-f89d-647b9cf06ef2@ozlabs.ru>","References":"<20170920200124.20457-1-jernej.skrabec@siol.net>\n\t<51c50157-6794-852b-f89d-647b9cf06ef2@ozlabs.ru>","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170930_105654_247661_A381D1B5 ","X-CRM114-Status":"GOOD ( 22.34 )","X-Spam-Score":"-2.6 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.6 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [213.250.19.135 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"devicetree@vger.kernel.org, narmstrong@baylibre.com,\n\tlinux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org,\n\tdri-devel@lists.freedesktop.org, wens@csie.org, hans.verkuil@cisco.com,\n\tLaurent.pinchart@ideasonboard.com, maxime.ripard@free-electrons.com, \n\tlinux-media@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, icenowy@aosc.io","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1777970,"web_url":"http://patchwork.ozlabs.org/comment/1777970/","msgid":"","list_archive_url":null,"date":"2017-10-01T01:46:38","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":7621,"url":"http://patchwork.ozlabs.org/api/people/7621/","name":"Alexey Kardashevskiy","email":"aik@ozlabs.ru"},"content":"On 01/10/17 04:56, Jernej Škrabec wrote:\n> Hi,\n> \n> Dne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy \n> napisal(a):\n>> On 21/09/17 06:01, Jernej Skrabec wrote:\n>>> [added media mailing list due to CEC question]\n>>>\n>>> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,\n>>> only video and CEC functionality is supported. Audio needs more tweaks.\n>>>\n>>> Series is based on the H3 DE2 patch series available on mailing list:\n>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.h\n>>> tml (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n>>>\n>>> Patch 1 adds support for polling plug detection since custom PHY used here\n>>> doesn't support HPD interrupt.\n>>>\n>>> Patch 2 enables overflow workaround for v1.32a. This HDMI controller\n>>> exhibits same issues as HDMI controller used in iMX6 SoCs.\n>>>\n>>> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n>>>\n>>> Patch 4 adds dt bindings documentation.\n>>>\n>>> Patch 5 adds actual H3 HDMI glue driver.\n>>>\n>>> Patch 6 and 7 add HDMI node to DT and enable it where needed.\n>>>\n>>> Allwinner used DW HDMI controller in a non standard way:\n>>> - register offsets obfuscation layer, which can fortunately be turned off\n>>> - register read lock, which has to be disabled by magic number\n>>> - custom PHY, which have to be initialized before DW HDMI controller\n>>> - non standard clocks\n>>> - no HPD interrupt\n>>>\n>>> Because of that, I have two questions:\n>>> - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n>>>\n>>> mainly concerned about invalidating CEC address here.\n>>>\n>>> - PHY has to be initialized before DW HDMI controller to disable offset\n>>>\n>>> obfuscation and read lock among other things. This means that all clocks\n>>> have to be enabled in glue driver. This poses a problem, since when\n>>> using component model, dw-hdmi bridge uses drvdata for it's own private\n>>> data and prevents glue layer to pass a pointer to unbind function,\n>>> where clocks should be disabled. I noticed same issue in meson DW HDMI\n>>> glue driver, where clocks are also not disabled when unbind callback is\n>>> called. I noticed that when H3 SoC is shutdown, HDMI output is still\n>>> enabled and lastest image is shown on monitor until it is unplugged\n>>> from power supply. Is there any simple solution to this?\n>>>\n>>> Chen-Yu,\n>>> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I\n>>> think it is safe to assume that divider in HDMI clock doesn't have any\n>>> effect.\n>>>\n>>> Branch based on linux-next from 1. September with integrated patches is\n>>> available here:\n>>> https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc\n>>\n>> Out of curiosity I tried this one and got:\n>>\n>>\n>>\n>> [ 0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO\n>> [ 0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO\n>> driver [ 0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi\n>> PIO driver [ 0.148009] ------------[ cut here ]------------\n>> [ 0.148035] WARNING: CPU: 0 PID: 1 at\n>> drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274\n>> [ 0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted\n>> 4.13.0-rc6-next-20170825-aik-aik #24\n>> [ 0.148051] Hardware name: Allwinner sun8i Family\n>> [ 0.148082] [] (unwind_backtrace) from []\n>> (show_stack+0x10/0x14)\n>> [ 0.148101] [] (show_stack) from []\n>> (dump_stack+0x84/0x98)\n>> [ 0.148117] [] (dump_stack) from []\n>> (__warn+0xe0/0xfc) [ 0.148132] [] (__warn) from []\n>> (warn_slowpath_null+0x20/0x28)\n>> [ 0.148145] [] (warn_slowpath_null) from []\n>> (ccu_nm_set_rate+0x1d0/0x274)\n>> [ 0.148161] [] (ccu_nm_set_rate) from []\n>> (clk_change_rate+0x19c/0x250)\n>> [ 0.148175] [] (clk_change_rate) from []\n>> (clk_core_set_rate_nolock+0x68/0xb0)\n>> [ 0.148187] [] (clk_core_set_rate_nolock) from []\n>> (clk_set_rate+0x20/0x30)\n>> [ 0.148202] [] (clk_set_rate) from []\n>> (of_clk_set_defaults+0x200/0x364)\n>> [ 0.148219] [] (of_clk_set_defaults) from []\n>> (platform_drv_probe+0x18/0xb0)\n>> [ 0.148233] [] (platform_drv_probe) from []\n>> (driver_probe_device+0x234/0x2e8)\n>> [ 0.148246] [] (driver_probe_device) from []\n>> (__driver_attach+0xb8/0xbc)\n>> [ 0.148258] [] (__driver_attach) from [> Unable to handle kernel NULL pointer dereference at virtual address 00000008\n>>\n> \n> Patch for that is already merged upstream and can be found here:\n> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/\n> drivers/clk/sunxi-ng?id=62d212bdb022deeb875f92f6e376c799e3f35eca\n\nLovely, it works, thanks!\n\n\n>> and a bit later:\n>>\n>> [ 1.995572] Rebooting in 10 seconds..\n> \n> I'm not sure about that one. Kernel config issue?\n\n\n\nYup, I did not have CMA enabled.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"t508JXv9\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=ozlabs-ru.20150623.gappssmtp.com\n\theader.i=@ozlabs-ru.20150623.gappssmtp.com header.b=\"VYLAxFnS\"; \n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y4Sq22tWPz9sPk\n\tfor ;\n\tSun, 1 Oct 2017 12:47:38 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dyTLx-0001ab-DD; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1797675,"web_url":"http://patchwork.ozlabs.org/comment/1797675/","msgid":"<20171102071942.GN30645@codeaurora.org>","list_archive_url":null,"date":"2017-11-02T07:19:42","subject":"Re: [RESEND RFC PATCH 3/7] clk: sunxi: Add CLK_SET_RATE_PARENT flag\n\tfor H3 HDMI clock","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/20, Jernej Skrabec wrote:\n> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.\n> \n> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.\n> \n> Signed-off-by: Jernej Skrabec \n> Signed-off-by: Icenowy Zheng \n> ---\n\nAcked-by: Stephen Boyd ","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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