[{"id":1772618,"web_url":"http://patchwork.ozlabs.org/comment/1772618/","msgid":"<5172c185-c6b5-49c3-cf0a-c3e073459346@synopsys.com>","list_archive_url":null,"date":"2017-09-21T09:39:42","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":68387,"url":"http://patchwork.ozlabs.org/api/people/68387/","name":"Jose Abreu","email":"Jose.Abreu@synopsys.com"},"content":"Hi Jernej,\n\nOn 20-09-2017 21:01, Jernej Skrabec wrote:\n> [added media mailing list due to CEC question]\n>\n> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only\n> video and CEC functionality is supported. Audio needs more tweaks.\n>\n> Series is based on the H3 DE2 patch series available on mailing list:\n> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s&e= \n> (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n>\n> Patch 1 adds support for polling plug detection since custom PHY used here\n> doesn't support HPD interrupt.\n>\n> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits\n> same issues as HDMI controller used in iMX6 SoCs.\n>\n> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n>\n> Patch 4 adds dt bindings documentation.\n>\n> Patch 5 adds actual H3 HDMI glue driver.\n>\n> Patch 6 and 7 add HDMI node to DT and enable it where needed.\n>\n> Allwinner used DW HDMI controller in a non standard way:\n> - register offsets obfuscation layer, which can fortunately be turned off\n> - register read lock, which has to be disabled by magic number\n> - custom PHY, which have to be initialized before DW HDMI controller\n> - non standard clocks\n> - no HPD interrupt\n>\n> Because of that, I have two questions:\n> - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n> mainly concerned about invalidating CEC address here.\n\nYou mean you get no interrupt when HPD status changes? Hans can\nanswer this better but then you will need to invalidate the cec\nphysical address yourself because right now its invalidated in\nthe dw-hdmi irq handler (see dw_hdmi_irq()).\n\n> - PHY has to be initialized before DW HDMI controller to disable offset\n> obfuscation and read lock among other things. This means that all clocks have\n> to be enabled in glue driver. This poses a problem, since when using\n> component model, dw-hdmi bridge uses drvdata for it's own private data and\n> prevents glue layer to pass a pointer to unbind function, where clocks should\n> be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks\n> are also not disabled when unbind callback is called. I noticed that when H3\n> SoC is shutdown, HDMI output is still enabled and lastest image is shown on\n> monitor until it is unplugged from power supply. Is there any simple solution\n> to this?\n\nI don't know if you can use an empty platform device created with\nplatform_device_alloc(). Perhaps it would be better fix this in\nthe dw-hdmi driver. I see two solutions:\n\n - Either you return the dw-hdmi private structure in the bind\ncallback, store it and pass it in the unbind\n - Or, you pass your own private data to the dw-hdmi bind, the\ndw-hdmi stores it and you just create a public function in the\ndw-hdmi driver called like dw_hdmi_get_auxdata(struct device\n*dev) which returns your private data.\n\nI think first option is nice, maybe anyone else can suggest\nsomething better?\n\nBest regards,\nJose Miguel Abreu\n\n>\n> Chen-Yu,\n> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I think\n> it is safe to assume that divider in HDMI clock doesn't have any effect.\n>\n> Branch based on linux-next from 1. September with integrated patches is\n> available here:\n> https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_jernejsk_linux-2D1_tree_h3-5Fhdmi-5Frfc&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=lDAnd3egsc2sxqVM-Ya_Me9ozWXKWvxxvsdV3Jn3vpA&e= \n>\n> Some additonal info about H3 HDMI:\n> https://urldefense.proofpoint.com/v2/url?u=https-3A__linux-2Dsunxi.org_DWC-5FHDMI-5FController&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=d9iEgk23RCLJL4oXJ4kkt6NyYK90_vFy0mCD3WauJDk&e= \n>\n> Thanks to Jens Kuske, who figured out that it is actually DW HDMI controller\n> and mapped scrambled register offsets to original ones.\n>\n> Icenowy Zheng (1):\n> ARM: sun8i: h3: Add DesignWare HDMI controller node\n>\n> Jernej Skrabec (6):\n> drm: bridge: Enable polling hpd event in dw_hdmi\n> drm: bridge: Enable workaround in dw_hdmi for v1.32a\n> clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock\n> dt-bindings: Document Allwinner DWC HDMI TX node\n> drm: sun4i: Add a glue for the DesignWare HDMI controller in H3\n> ARM: sun8i: h3: Enable HDMI output on H3 boards\n>\n> .../bindings/display/sunxi/sun4i-drm.txt | 158 ++++++-\n> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-beelink-x2.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 33 ++\n> arch/arm/boot/dts/sun8i-h3.dtsi | 5 +\n> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 36 ++\n> drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-\n> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 14 +-\n> drivers/gpu/drm/sun4i/Kconfig | 9 +\n> drivers/gpu/drm/sun4i/Makefile | 1 +\n> drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 500 +++++++++++++++++++++\n> 15 files changed, 950 insertions(+), 6 deletions(-)\n> create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c\n>\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyWn61Tw3z9t43\n\tfor ;\n\tThu, 21 Sep 2017 19:40:26 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751596AbdIUJkK (ORCPT\n\t);\n\tThu, 21 Sep 2017 05:40:10 -0400","from us01smtprelay-2.synopsys.com ([198.182.47.9]:54181 \"EHLO\n\tsmtprelay.synopsys.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751450AbdIUJkJ (ORCPT\n\t); Thu, 21 Sep 2017 05:40:09 -0400","from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238])\n\tby smtprelay.synopsys.com (Postfix) with ESMTP id E65E324E12C0;\n\tThu, 21 Sep 2017 02:40:06 -0700 (PDT)","from mailhost.synopsys.com (localhost [127.0.0.1])\n\tby mailhost.synopsys.com (Postfix) with ESMTP id 72FF6E00;\n\tThu, 21 Sep 2017 02:40:06 -0700 (PDT)","from US01WEHTC2.internal.synopsys.com\n\t(us01wehtc2-vip.internal.synopsys.com [10.12.239.238])\n\tby mailhost.synopsys.com (Postfix) with ESMTP id 0A14FDBE;\n\tThu, 21 Sep 2017 02:40:05 -0700 (PDT)","from DE02WEHTCB.internal.synopsys.com (10.225.19.94) by\n\tUS01WEHTC2.internal.synopsys.com (10.12.239.237) with Microsoft SMTP\n\tServer (TLS) id 14.3.266.1; Thu, 21 Sep 2017 02:40:03 -0700","from DE02WEHTCA.internal.synopsys.com (10.225.19.92) by\n\tDE02WEHTCB.internal.synopsys.com (10.225.19.94) with Microsoft SMTP\n\tServer (TLS) id 14.3.266.1; Thu, 21 Sep 2017 11:40:01 +0200","from [10.0.2.15] (10.107.19.118) by\n\tDE02WEHTCA.internal.synopsys.com\n\t(10.225.19.80) with Microsoft SMTP Server (TLS) id 14.3.266.1;\n\tThu, 21 Sep 2017 11:40:00 +0200"],"Subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","To":"Jernej Skrabec ,\n\t, ","References":"<20170920200124.20457-1-jernej.skrabec@siol.net>","CC":", ,\n\t, ,\n\t, , \n\t, ,\n\t, ,\n\t","From":"Jose Abreu ","Message-ID":"<5172c185-c6b5-49c3-cf0a-c3e073459346@synopsys.com>","Date":"Thu, 21 Sep 2017 10:39:42 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.4.0","MIME-Version":"1.0","In-Reply-To":"<20170920200124.20457-1-jernej.skrabec@siol.net>","Content-Type":"text/plain; charset=\"windows-1252\"","Content-Transfer-Encoding":"7bit","X-Originating-IP":"[10.107.19.118]","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772637,"web_url":"http://patchwork.ozlabs.org/comment/1772637/","msgid":"<68fa56f8-9878-12d0-1696-4393abe45db5@cisco.com>","list_archive_url":null,"date":"2017-09-21T09:59:27","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":26081,"url":"http://patchwork.ozlabs.org/api/people/26081/","name":"Hans Verkuil (hansverk)","email":"hansverk@cisco.com"},"content":"On 09/21/17 11:39, Jose Abreu wrote:\n> Hi Jernej,\n> \n> On 20-09-2017 21:01, Jernej Skrabec wrote:\n>> [added media mailing list due to CEC question]\n>>\n>> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only\n>> video and CEC functionality is supported. Audio needs more tweaks.\n>>\n>> Series is based on the H3 DE2 patch series available on mailing list:\n>> https://urldefense.proofpoint.com/v2/url?u=http-3A__lists.infradead.org_pipermail_linux-2Darm-2Dkernel_2017-2DAugust_522697.html&d=DwIBAg&c=DPL6_X_6JkXFx7AXWqB0tg&r=WHDsc6kcWAl4i96Vm5hJ_19IJiuxx_p_Rzo2g-uHDKw&m=coyfcQKSr2asrHcaCeWFmAP_9nkFkRK8s7Uw5bmVei4&s=JCFaMXK1MmZ3jE745_YcqZhZkaqtc6UapGfSSapcz_s&e= \n>> (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n>>\n>> Patch 1 adds support for polling plug detection since custom PHY used here\n>> doesn't support HPD interrupt.\n>>\n>> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits\n>> same issues as HDMI controller used in iMX6 SoCs.\n>>\n>> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n>>\n>> Patch 4 adds dt bindings documentation.\n>>\n>> Patch 5 adds actual H3 HDMI glue driver.\n>>\n>> Patch 6 and 7 add HDMI node to DT and enable it where needed.\n>>\n>> Allwinner used DW HDMI controller in a non standard way:\n>> - register offsets obfuscation layer, which can fortunately be turned off\n>> - register read lock, which has to be disabled by magic number\n>> - custom PHY, which have to be initialized before DW HDMI controller\n>> - non standard clocks\n>> - no HPD interrupt\n>>\n>> Because of that, I have two questions:\n>> - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n>> mainly concerned about invalidating CEC address here.\n> \n> You mean you get no interrupt when HPD status changes? Hans can\n> answer this better but then you will need to invalidate the cec\n> physical address yourself because right now its invalidated in\n> the dw-hdmi irq handler (see dw_hdmi_irq()).\n\nThat's correct. When the HPD goes low you need to call cec_notifier_phys_addr_invalidate()\nto invalidate the physical address. This is not terribly time sensitive, i.e.\nchecking this once a second would be quick enough.\n\nRegards,\n\n\tHans\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=cisco.com header.i=@cisco.com\n\theader.b=\"KJJDd3ik\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyXC875j7z9t49\n\tfor ;\n\tThu, 21 Sep 2017 19:59:32 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751722AbdIUJ7b (ORCPT\n\t);\n\tThu, 21 Sep 2017 05:59:31 -0400","from aer-iport-2.cisco.com ([173.38.203.52]:23132 \"EHLO\n\taer-iport-2.cisco.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751634AbdIUJ7a (ORCPT\n\t); Thu, 21 Sep 2017 05:59:30 -0400","from aer-iport-nat.cisco.com (HELO aer-core-1.cisco.com)\n\t([173.38.203.22])\n\tby aer-iport-2.cisco.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t21 Sep 2017 09:59:28 +0000","from [10.47.79.81] ([10.47.79.81]) (authenticated bits=0)\n\tby aer-core-1.cisco.com (8.14.5/8.14.5) with ESMTP id v8L9xRiV001663\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES128-SHA bits=128 verify=NO);\n\tThu, 21 Sep 2017 09:59:28 GMT"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple;\n\td=cisco.com; i=@cisco.com; l=2251; q=dns/txt; s=iport;\n\tt=1505987970; x=1507197570;\n\th=subject:to:cc:references:from:message-id:date:\n\tmime-version:in-reply-to:content-transfer-encoding;\n\tbh=vkbQUAr2NmKJhQfmZYQiPjoyQlSQO1VTowsrqauktwc=;\n\tb=KJJDd3ikRIMRgbBIgn5WzhlAhZHllIy0uo3s+O1di7lyVh/mmqhM2dih\n\tDugfc/bUzR/bksGQDkdmHXY/BAXwLr0OorjneZrro6ACUoQW2bbQWIjVs\n\t/7GWmOHnGYlbUJgmn827NyC/kS1aZuukrVm5uwWAiW8kt0tuXCbg6DFIa U=;","X-IronPort-AV":"E=Sophos;i=\"5.42,424,1500940800\"; d=\"scan'208\";a=\"654785411\"","Subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","To":"Jose Abreu ,\n\tJernej Skrabec ,\n\tmaxime.ripard@free-electrons.com, wens@csie.org","Cc":"Laurent.pinchart@ideasonboard.com, hans.verkuil@cisco.com,\n\tnarmstrong@baylibre.com, dri-devel@lists.freedesktop.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,\n\ticenowy@aosc.io, linux-sunxi@googlegroups.com,\n\tlinux-media@vger.kernel.org","References":"<20170920200124.20457-1-jernej.skrabec@siol.net>\n\t<5172c185-c6b5-49c3-cf0a-c3e073459346@synopsys.com>","From":"Hans Verkuil ","Message-ID":"<68fa56f8-9878-12d0-1696-4393abe45db5@cisco.com>","Date":"Thu, 21 Sep 2017 11:59:27 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<5172c185-c6b5-49c3-cf0a-c3e073459346@synopsys.com>","Content-Type":"text/plain; charset=windows-1252","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","X-Authenticated-User":"hansverk","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1777905,"web_url":"http://patchwork.ozlabs.org/comment/1777905/","msgid":"<51c50157-6794-852b-f89d-647b9cf06ef2@ozlabs.ru>","list_archive_url":null,"date":"2017-09-30T11:58:03","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":7621,"url":"http://patchwork.ozlabs.org/api/people/7621/","name":"Alexey Kardashevskiy","email":"aik@ozlabs.ru"},"content":"On 21/09/17 06:01, Jernej Skrabec wrote:\n> [added media mailing list due to CEC question]\n> \n> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now, only\n> video and CEC functionality is supported. Audio needs more tweaks.\n> \n> Series is based on the H3 DE2 patch series available on mailing list:\n> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.html\n> (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n> \n> Patch 1 adds support for polling plug detection since custom PHY used here\n> doesn't support HPD interrupt.\n> \n> Patch 2 enables overflow workaround for v1.32a. This HDMI controller exhibits\n> same issues as HDMI controller used in iMX6 SoCs.\n> \n> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n> \n> Patch 4 adds dt bindings documentation.\n> \n> Patch 5 adds actual H3 HDMI glue driver.\n> \n> Patch 6 and 7 add HDMI node to DT and enable it where needed.\n> \n> Allwinner used DW HDMI controller in a non standard way:\n> - register offsets obfuscation layer, which can fortunately be turned off\n> - register read lock, which has to be disabled by magic number\n> - custom PHY, which have to be initialized before DW HDMI controller\n> - non standard clocks\n> - no HPD interrupt\n> \n> Because of that, I have two questions:\n> - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n> mainly concerned about invalidating CEC address here.\n> - PHY has to be initialized before DW HDMI controller to disable offset\n> obfuscation and read lock among other things. This means that all clocks have\n> to be enabled in glue driver. This poses a problem, since when using\n> component model, dw-hdmi bridge uses drvdata for it's own private data and\n> prevents glue layer to pass a pointer to unbind function, where clocks should\n> be disabled. I noticed same issue in meson DW HDMI glue driver, where clocks\n> are also not disabled when unbind callback is called. I noticed that when H3\n> SoC is shutdown, HDMI output is still enabled and lastest image is shown on\n> monitor until it is unplugged from power supply. Is there any simple solution\n> to this?\n> \n> Chen-Yu,\n> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I think\n> it is safe to assume that divider in HDMI clock doesn't have any effect.\n> \n> Branch based on linux-next from 1. September with integrated patches is\n> available here:\n> https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc\n\n\nOut of curiosity I tried this one and got:\n\n\n\n[ 0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO\n[ 0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO driver\n[ 0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi PIO driver\n[ 0.148009] ------------[ cut here ]------------\n[ 0.148035] WARNING: CPU: 0 PID: 1 at\ndrivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274\n[ 0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted\n4.13.0-rc6-next-20170825-aik-aik #24\n[ 0.148051] Hardware name: Allwinner sun8i Family\n[ 0.148082] [] (unwind_backtrace) from []\n(show_stack+0x10/0x14)\n[ 0.148101] [] (show_stack) from []\n(dump_stack+0x84/0x98)\n[ 0.148117] [] (dump_stack) from [] (__warn+0xe0/0xfc)\n[ 0.148132] [] (__warn) from []\n(warn_slowpath_null+0x20/0x28)\n[ 0.148145] [] (warn_slowpath_null) from []\n(ccu_nm_set_rate+0x1d0/0x274)\n[ 0.148161] [] (ccu_nm_set_rate) from []\n(clk_change_rate+0x19c/0x250)\n[ 0.148175] [] (clk_change_rate) from []\n(clk_core_set_rate_nolock+0x68/0xb0)\n[ 0.148187] [] (clk_core_set_rate_nolock) from []\n(clk_set_rate+0x20/0x30)\n[ 0.148202] [] (clk_set_rate) from []\n(of_clk_set_defaults+0x200/0x364)\n[ 0.148219] [] (of_clk_set_defaults) from []\n(platform_drv_probe+0x18/0xb0)\n[ 0.148233] [] (platform_drv_probe) from []\n(driver_probe_device+0x234/0x2e8)\n[ 0.148246] [] (driver_probe_device) from []\n(__driver_attach+0xb8/0xbc)\n[ 0.148258] [] (__driver_attach) from [","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=ozlabs-ru.20150623.gappssmtp.com\n\theader.i=@ozlabs-ru.20150623.gappssmtp.com header.b=\"r9V6fAjb\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y46Q03nCrz9sRq\n\tfor ;\n\tSat, 30 Sep 2017 21:58:16 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752793AbdI3L6O (ORCPT\n\t);\n\tSat, 30 Sep 2017 07:58:14 -0400","from mail-pf0-f193.google.com ([209.85.192.193]:33514 \"EHLO\n\tmail-pf0-f193.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751677AbdI3L6M (ORCPT\n\t); Sat, 30 Sep 2017 07:58:12 -0400","by mail-pf0-f193.google.com with SMTP id m28so1290241pfi.0\n\tfor ;\n\tSat, 30 Sep 2017 04:58:12 -0700 (PDT)","from [192.168.10.22] (124-171-134-202.dyn.iinet.net.au.\n\t[124.171.134.202]) by smtp.googlemail.com with ESMTPSA id\n\tc7sm12973689pfg.85.2017.09.30.04.58.06\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSat, 30 Sep 2017 04:58:11 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=ozlabs-ru.20150623.gappssmtp.com; s=20150623;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=MBqt/irApZzTV33VOp3NwcuagSLXqO3JDRTGgcybyHM=;\n\tb=r9V6fAjbRda1YyEtweBXlJR6BoRVTGHyC0kXsgR4SvW33VNLV6dTJga89cVsjUQM2O\n\tV0H4pVHuKMrssmuzePmKX6yD9IjA1oikbKo8NBSY2sXDmPOEEiXZo+1kIAOwLEZkmO9Y\n\tya8kRYz/PGZjH9YAq6D3nZCtp5n9St+8uMxkLqj25GiV4OcisBkWxad0wej6rrsBjqvg\n\tmvxr18MDnKVDCETDatzOyrwiyc4CeKywTiWlqdP7p/G4V4awUQamMUxf71cMzygjMAU0\n\tzr9kDcGgaN95uhvDmaoM3A5AJa26QbXemvyc0IaeZSu9icnHbjQCQtV7FW2YwOciEkwU\n\tZhFQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=MBqt/irApZzTV33VOp3NwcuagSLXqO3JDRTGgcybyHM=;\n\tb=gUiWiQT6hebhepwbyT4AVp1kOd3LGiubo92SYbtHtTeJo/w7Kxd+Dezp5nennvpEPw\n\tPpt/RIwxaG8j8CuYRLSuQvzM+J/o0IeG+eh2LbplbTz07D5tAceHE9JGFOMmYgdb9Z54\n\tC+XvvO1JlxzwU1yy4Kz4M5iHUyTnN5hvN25QWHwYPkooP/RImGs0coho4VD9b9wmHZ+Q\n\tcQ7CQlzCIezJXdPXMdDI/c2s0SeRPZR5crQLjOYf2rbhpQtOjSse6V8QT7qNms7/H1OS\n\tZHDxyrDZpoNy4lmIaUgqp7GzTF5iqWLoh8t6HsodIwMSQk9h2tBVi4I+2OJ3qG3hImHE\n\tSmdA==","X-Gm-Message-State":"AMCzsaVmt58cOG0UyqcEvxW5XdzWftoAfLk+despSkP0dYBAHnxSYXQP\n\tbnPPVubWgiht62RkH9qBnM1UGQ==","X-Google-Smtp-Source":"AOwi7QCyAVsawnbxUbPN/oK62WWAu6y/dHhN38+lPAqTq+4JjZigcBNlZ2KKYFo2HAV/q6ZmAbNLmw==","X-Received":"by 10.99.95.207 with SMTP id t198mr1201462pgb.145.1506772692034; \n\tSat, 30 Sep 2017 04:58:12 -0700 (PDT)","Subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","To":"Jernej Skrabec ,\n\tmaxime.ripard@free-electrons.com, wens@csie.org","Cc":"Laurent.pinchart@ideasonboard.com, hans.verkuil@cisco.com,\n\tnarmstrong@baylibre.com, dri-devel@lists.freedesktop.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,\n\ticenowy@aosc.io, linux-sunxi@googlegroups.com,\n\tlinux-media@vger.kernel.org","References":"<20170920200124.20457-1-jernej.skrabec@siol.net>","From":"Alexey Kardashevskiy ","Message-ID":"<51c50157-6794-852b-f89d-647b9cf06ef2@ozlabs.ru>","Date":"Sat, 30 Sep 2017 21:58:03 +1000","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<20170920200124.20457-1-jernej.skrabec@siol.net>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-AU","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1777933,"web_url":"http://patchwork.ozlabs.org/comment/1777933/","msgid":"<34246001.lKHNgTVc0h@jernej-laptop>","list_archive_url":null,"date":"2017-09-30T17:56:19","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":70601,"url":"http://patchwork.ozlabs.org/api/people/70601/","name":"Jernej Škrabec","email":"jernej.skrabec@siol.net"},"content":"Hi,\n\nDne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy \nnapisal(a):\n> On 21/09/17 06:01, Jernej Skrabec wrote:\n> > [added media mailing list due to CEC question]\n> > \n> > This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,\n> > only video and CEC functionality is supported. Audio needs more tweaks.\n> > \n> > Series is based on the H3 DE2 patch series available on mailing list:\n> > http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.h\n> > tml (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n> > \n> > Patch 1 adds support for polling plug detection since custom PHY used here\n> > doesn't support HPD interrupt.\n> > \n> > Patch 2 enables overflow workaround for v1.32a. This HDMI controller\n> > exhibits same issues as HDMI controller used in iMX6 SoCs.\n> > \n> > Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n> > \n> > Patch 4 adds dt bindings documentation.\n> > \n> > Patch 5 adds actual H3 HDMI glue driver.\n> > \n> > Patch 6 and 7 add HDMI node to DT and enable it where needed.\n> > \n> > Allwinner used DW HDMI controller in a non standard way:\n> > - register offsets obfuscation layer, which can fortunately be turned off\n> > - register read lock, which has to be disabled by magic number\n> > - custom PHY, which have to be initialized before DW HDMI controller\n> > - non standard clocks\n> > - no HPD interrupt\n> > \n> > Because of that, I have two questions:\n> > - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n> > \n> > mainly concerned about invalidating CEC address here.\n> > \n> > - PHY has to be initialized before DW HDMI controller to disable offset\n> > \n> > obfuscation and read lock among other things. This means that all clocks\n> > have to be enabled in glue driver. This poses a problem, since when\n> > using component model, dw-hdmi bridge uses drvdata for it's own private\n> > data and prevents glue layer to pass a pointer to unbind function,\n> > where clocks should be disabled. I noticed same issue in meson DW HDMI\n> > glue driver, where clocks are also not disabled when unbind callback is\n> > called. I noticed that when H3 SoC is shutdown, HDMI output is still\n> > enabled and lastest image is shown on monitor until it is unplugged\n> > from power supply. Is there any simple solution to this?\n> > \n> > Chen-Yu,\n> > TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I\n> > think it is safe to assume that divider in HDMI clock doesn't have any\n> > effect.\n> > \n> > Branch based on linux-next from 1. September with integrated patches is\n> > available here:\n> > https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc\n> \n> Out of curiosity I tried this one and got:\n> \n> \n> \n> [ 0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO\n> [ 0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO\n> driver [ 0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi\n> PIO driver [ 0.148009] ------------[ cut here ]------------\n> [ 0.148035] WARNING: CPU: 0 PID: 1 at\n> drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274\n> [ 0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted\n> 4.13.0-rc6-next-20170825-aik-aik #24\n> [ 0.148051] Hardware name: Allwinner sun8i Family\n> [ 0.148082] [] (unwind_backtrace) from []\n> (show_stack+0x10/0x14)\n> [ 0.148101] [] (show_stack) from []\n> (dump_stack+0x84/0x98)\n> [ 0.148117] [] (dump_stack) from []\n> (__warn+0xe0/0xfc) [ 0.148132] [] (__warn) from []\n> (warn_slowpath_null+0x20/0x28)\n> [ 0.148145] [] (warn_slowpath_null) from []\n> (ccu_nm_set_rate+0x1d0/0x274)\n> [ 0.148161] [] (ccu_nm_set_rate) from []\n> (clk_change_rate+0x19c/0x250)\n> [ 0.148175] [] (clk_change_rate) from []\n> (clk_core_set_rate_nolock+0x68/0xb0)\n> [ 0.148187] [] (clk_core_set_rate_nolock) from []\n> (clk_set_rate+0x20/0x30)\n> [ 0.148202] [] (clk_set_rate) from []\n> (of_clk_set_defaults+0x200/0x364)\n> [ 0.148219] [] (of_clk_set_defaults) from []\n> (platform_drv_probe+0x18/0xb0)\n> [ 0.148233] [] (platform_drv_probe) from []\n> (driver_probe_device+0x234/0x2e8)\n> [ 0.148246] [] (driver_probe_device) from []\n> (__driver_attach+0xb8/0xbc)\n> [ 0.148258] [] (__driver_attach) from [ Unable to handle kernel NULL pointer dereference at virtual address 00000008\n> \n\nPatch for that is already merged upstream and can be found here:\nhttps://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/\ndrivers/clk/sunxi-ng?id=62d212bdb022deeb875f92f6e376c799e3f35eca\n\n> and a bit later:\n> \n> [ 1.995572] Rebooting in 10 seconds..\n\nI'm not sure about that one. Kernel config issue?\n\nRegards,\nJernej\n\n> \n> Orange PI PC, script.bin.OPI-PC_1080p60_hdmi.\n> \n> What do I miss? Thanks.\n> \n> \n> \n> --\n> Alexey\n\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y4GMd4C13z9t48\n\tfor ;\n\tSun, 1 Oct 2017 04:56:45 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751601AbdI3R42 (ORCPT\n\t);\n\tSat, 30 Sep 2017 13:56:28 -0400","from mailoutvs2.siol.net ([213.250.19.135]:41949 \"EHLO\n\tmail.siol.net\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1751069AbdI3R40 (ORCPT );\n\tSat, 30 Sep 2017 13:56:26 -0400","from localhost (localhost [127.0.0.1])\n\tby mail.siol.net (Zimbra) with ESMTP id 388E852301E;\n\tSat, 30 Sep 2017 19:56:23 +0200 (CEST)","from mail.siol.net ([127.0.0.1])\n\tby localhost (psrvmta12.zcs-production.pri [127.0.0.1]) (amavisd-new, \n\tport 10032)\n\twith ESMTP id CHDuQ8TCwvew; Sat, 30 Sep 2017 19:56:22 +0200 (CEST)","from mail.siol.net (localhost [127.0.0.1])\n\tby mail.siol.net (Zimbra) with ESMTPS id 5C3FE5251C2;\n\tSat, 30 Sep 2017 19:56:22 +0200 (CEST)","from jernej-laptop.localnet (cpe-86-58-68-135.ftth.triera.net\n\t[86.58.68.135]) (Authenticated sender: 031275009)\n\tby mail.siol.net (Zimbra) with ESMTPA id 62B4452301E;\n\tSat, 30 Sep 2017 19:56:20 +0200 (CEST)"],"X-Virus-Scanned":"amavisd-new at psrvmta12.zcs-production.pri","From":"Jernej =?utf-8?q?=C5=A0krabec?= ","To":"Alexey Kardashevskiy ","Cc":"maxime.ripard@free-electrons.com, wens@csie.org,\n\tLaurent.pinchart@ideasonboard.com, hans.verkuil@cisco.com,\n\tnarmstrong@baylibre.com, dri-devel@lists.freedesktop.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,\n\ticenowy@aosc.io, linux-sunxi@googlegroups.com,\n\tlinux-media@vger.kernel.org","Subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","Date":"Sat, 30 Sep 2017 19:56:19 +0200","Message-ID":"<34246001.lKHNgTVc0h@jernej-laptop>","In-Reply-To":"<51c50157-6794-852b-f89d-647b9cf06ef2@ozlabs.ru>","References":"<20170920200124.20457-1-jernej.skrabec@siol.net>\n\t<51c50157-6794-852b-f89d-647b9cf06ef2@ozlabs.ru>","MIME-Version":"1.0","Content-Transfer-Encoding":"7Bit","Content-Type":"text/plain; charset=\"us-ascii\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1777969,"web_url":"http://patchwork.ozlabs.org/comment/1777969/","msgid":"","list_archive_url":null,"date":"2017-10-01T01:46:38","subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","submitter":{"id":7621,"url":"http://patchwork.ozlabs.org/api/people/7621/","name":"Alexey Kardashevskiy","email":"aik@ozlabs.ru"},"content":"On 01/10/17 04:56, Jernej Škrabec wrote:\n> Hi,\n> \n> Dne sobota, 30. september 2017 ob 13:58:03 CEST je Alexey Kardashevskiy \n> napisal(a):\n>> On 21/09/17 06:01, Jernej Skrabec wrote:\n>>> [added media mailing list due to CEC question]\n>>>\n>>> This patch series adds a HDMI glue driver for Allwinner H3 SoC. For now,\n>>> only video and CEC functionality is supported. Audio needs more tweaks.\n>>>\n>>> Series is based on the H3 DE2 patch series available on mailing list:\n>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-August/522697.h\n>>> tml (ignore patches marked with [NOT FOR REVIEW NOW] tag)\n>>>\n>>> Patch 1 adds support for polling plug detection since custom PHY used here\n>>> doesn't support HPD interrupt.\n>>>\n>>> Patch 2 enables overflow workaround for v1.32a. This HDMI controller\n>>> exhibits same issues as HDMI controller used in iMX6 SoCs.\n>>>\n>>> Patch 3 adds CLK_SET_RATE_PARENT to hdmi clock.\n>>>\n>>> Patch 4 adds dt bindings documentation.\n>>>\n>>> Patch 5 adds actual H3 HDMI glue driver.\n>>>\n>>> Patch 6 and 7 add HDMI node to DT and enable it where needed.\n>>>\n>>> Allwinner used DW HDMI controller in a non standard way:\n>>> - register offsets obfuscation layer, which can fortunately be turned off\n>>> - register read lock, which has to be disabled by magic number\n>>> - custom PHY, which have to be initialized before DW HDMI controller\n>>> - non standard clocks\n>>> - no HPD interrupt\n>>>\n>>> Because of that, I have two questions:\n>>> - Since HPD have to be polled, is it enough just to enable poll mode? I'm\n>>>\n>>> mainly concerned about invalidating CEC address here.\n>>>\n>>> - PHY has to be initialized before DW HDMI controller to disable offset\n>>>\n>>> obfuscation and read lock among other things. This means that all clocks\n>>> have to be enabled in glue driver. This poses a problem, since when\n>>> using component model, dw-hdmi bridge uses drvdata for it's own private\n>>> data and prevents glue layer to pass a pointer to unbind function,\n>>> where clocks should be disabled. I noticed same issue in meson DW HDMI\n>>> glue driver, where clocks are also not disabled when unbind callback is\n>>> called. I noticed that when H3 SoC is shutdown, HDMI output is still\n>>> enabled and lastest image is shown on monitor until it is unplugged\n>>> from power supply. Is there any simple solution to this?\n>>>\n>>> Chen-Yu,\n>>> TL Lim was unable to obtain any answer from Allwinner about HDMI clocks. I\n>>> think it is safe to assume that divider in HDMI clock doesn't have any\n>>> effect.\n>>>\n>>> Branch based on linux-next from 1. September with integrated patches is\n>>> available here:\n>>> https://github.com/jernejsk/linux-1/tree/h3_hdmi_rfc\n>>\n>> Out of curiosity I tried this one and got:\n>>\n>>\n>>\n>> [ 0.071711] sun4i-usb-phy 1c19400.phy: Couldn't request ID GPIO\n>> [ 0.074809] sun8i-h3-pinctrl 1c20800.pinctrl: initialized sunXi PIO\n>> driver [ 0.076167] sun8i-h3-r-pinctrl 1f02c00.pinctrl: initialized sunXi\n>> PIO driver [ 0.148009] ------------[ cut here ]------------\n>> [ 0.148035] WARNING: CPU: 0 PID: 1 at\n>> drivers/clk/sunxi-ng/ccu_common.c:41 ccu_nm_set_rate+0x1d0/0x274\n>> [ 0.148046] CPU: 0 PID: 1 Comm: swapper/0 Not tainted\n>> 4.13.0-rc6-next-20170825-aik-aik #24\n>> [ 0.148051] Hardware name: Allwinner sun8i Family\n>> [ 0.148082] [] (unwind_backtrace) from []\n>> (show_stack+0x10/0x14)\n>> [ 0.148101] [] (show_stack) from []\n>> (dump_stack+0x84/0x98)\n>> [ 0.148117] [] (dump_stack) from []\n>> (__warn+0xe0/0xfc) [ 0.148132] [] (__warn) from []\n>> (warn_slowpath_null+0x20/0x28)\n>> [ 0.148145] [] (warn_slowpath_null) from []\n>> (ccu_nm_set_rate+0x1d0/0x274)\n>> [ 0.148161] [] (ccu_nm_set_rate) from []\n>> (clk_change_rate+0x19c/0x250)\n>> [ 0.148175] [] (clk_change_rate) from []\n>> (clk_core_set_rate_nolock+0x68/0xb0)\n>> [ 0.148187] [] (clk_core_set_rate_nolock) from []\n>> (clk_set_rate+0x20/0x30)\n>> [ 0.148202] [] (clk_set_rate) from []\n>> (of_clk_set_defaults+0x200/0x364)\n>> [ 0.148219] [] (of_clk_set_defaults) from []\n>> (platform_drv_probe+0x18/0xb0)\n>> [ 0.148233] [] (platform_drv_probe) from []\n>> (driver_probe_device+0x234/0x2e8)\n>> [ 0.148246] [] (driver_probe_device) from []\n>> (__driver_attach+0xb8/0xbc)\n>> [ 0.148258] [] (__driver_attach) from [> Unable to handle kernel NULL pointer dereference at virtual address 00000008\n>>\n> \n> Patch for that is already merged upstream and can be found here:\n> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/\n> drivers/clk/sunxi-ng?id=62d212bdb022deeb875f92f6e376c799e3f35eca\n\nLovely, it works, thanks!\n\n\n>> and a bit later:\n>>\n>> [ 1.995572] Rebooting in 10 seconds..\n> \n> I'm not sure about that one. Kernel config issue?\n\n\n\nYup, I did not have CMA enabled.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=ozlabs-ru.20150623.gappssmtp.com\n\theader.i=@ozlabs-ru.20150623.gappssmtp.com header.b=\"VYLAxFnS\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y4SpJ4T1yz9sPk\n\tfor ;\n\tSun, 1 Oct 2017 12:47:04 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752176AbdJABqs (ORCPT\n\t);\n\tSat, 30 Sep 2017 21:46:48 -0400","from mail-pg0-f68.google.com ([74.125.83.68]:35674 \"EHLO\n\tmail-pg0-f68.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751604AbdJABqq (ORCPT\n\t); Sat, 30 Sep 2017 21:46:46 -0400","by mail-pg0-f68.google.com with SMTP id j16so2282915pga.2\n\tfor ;\n\tSat, 30 Sep 2017 18:46:46 -0700 (PDT)","from [192.168.10.22] (124-171-134-202.dyn.iinet.net.au.\n\t[124.171.134.202]) by smtp.googlemail.com with ESMTPSA id\n\tz69sm12330947pfl.86.2017.09.30.18.46.40\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSat, 30 Sep 2017 18:46:45 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=ozlabs-ru.20150623.gappssmtp.com; s=20150623;\n\th=subject:to:cc:references:from:message-id:date:user-agent\n\t:mime-version:in-reply-to:content-language:content-transfer-encoding; \n\tbh=9c2P1QxN0vNreRzBpW7sJLSu3/oJLkgE9SC7MQcJImU=;\n\tb=VYLAxFnSndUhRj0iedZ+6yKSnJIPKPOIJNpmDKwrN56yfY26C5lkLaQec1Q2n4SYAa\n\tMT5sQYH9G0dtS4u3Ul50IIdflBBR9JAzTZVweILroJ2xS6eCVYFq8/V/KXtrO+/i2EBs\n\tZsMQdj5WYqMbBnRnVsOB87bKr00iaBA7agbGo+z92bMo8SC/grepDfRyiMBSfNy1ItBG\n\tHo+hPi/npYNtg6P8ect9eXG9x9E1zIZ+u+cqvrzQPQ4pL5G5ynvR3DPEGLTklXEr8uzM\n\t+EEW5nja5qVsyrd4ekxVdSifkV4KMaS3DIChPAVICsu3QZiTwDYf29CwGilz2AIN+7Ab\n\t/ohw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:subject:to:cc:references:from:message-id:date\n\t:user-agent:mime-version:in-reply-to:content-language\n\t:content-transfer-encoding;\n\tbh=9c2P1QxN0vNreRzBpW7sJLSu3/oJLkgE9SC7MQcJImU=;\n\tb=Je6DF7onSgeoIlIpJaZ+5GVl5YBKSltZ6m+EoWSs//BIn3IZ6i2liH8IysDYXLKXdb\n\tEn0pEM7giJlyuLUiwh4b57+e0p+moiZUMUkWFrdcNzqApGoOLgpoWAmM/wKupZ3rDoQR\n\tBZWoOItFv2HWVxwyrqxOSx8gAvnoiJjWAtF2hCTukXMQuSnG8wL5QKUz3iWyrVfF7nq6\n\tGNpjVrgpRSd/pMaUl6LrXSsje9U3WNpayzhUDnh4awjaThsHShFzZUIMwWosA722JjVr\n\tQuULJ6ngrgadxwex/scI1wIaqRaWfXFYBdMQBHC78mPW4bLmW5hT/bn42utT32qiUv9Z\n\tmlMQ==","X-Gm-Message-State":"AHPjjUjiziZKEXWttkd9idXm+vdlfHudkkqmTnrZXXtUAUl4zR6oR4FG\n\tTYiYspss+dYYURsdumjlmm0AHA==","X-Google-Smtp-Source":"AOwi7QDQgzWq105VvGL+wl++hEissYSLVO54hVtinM2jAq8GIZK21c11mdwETMBhj7Vka2+3opwv+Q==","X-Received":"by 10.159.252.66 with SMTP id t2mr10736317plz.31.1506822406054; \n\tSat, 30 Sep 2017 18:46:46 -0700 (PDT)","Subject":"Re: [RESEND RFC PATCH 0/7] sun8i H3 HDMI glue driver for DW HDMI","To":"=?utf-8?q?Jernej_=C5=A0krabec?= ","Cc":"maxime.ripard@free-electrons.com, wens@csie.org,\n\tLaurent.pinchart@ideasonboard.com, hans.verkuil@cisco.com,\n\tnarmstrong@baylibre.com, dri-devel@lists.freedesktop.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,\n\ticenowy@aosc.io, linux-sunxi@googlegroups.com,\n\tlinux-media@vger.kernel.org","References":"<20170920200124.20457-1-jernej.skrabec@siol.net>\n\t<51c50157-6794-852b-f89d-647b9cf06ef2@ozlabs.ru>\n\t<34246001.lKHNgTVc0h@jernej-laptop>","From":"Alexey Kardashevskiy ","Message-ID":"","Date":"Sun, 1 Oct 2017 12:46:38 +1100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<34246001.lKHNgTVc0h@jernej-laptop>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-AU","Content-Transfer-Encoding":"8bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1797674,"web_url":"http://patchwork.ozlabs.org/comment/1797674/","msgid":"<20171102071942.GN30645@codeaurora.org>","list_archive_url":null,"date":"2017-11-02T07:19:42","subject":"Re: [RESEND RFC PATCH 3/7] clk: sunxi: Add CLK_SET_RATE_PARENT flag\n\tfor H3 HDMI clock","submitter":{"id":6071,"url":"http://patchwork.ozlabs.org/api/people/6071/","name":"Stephen Boyd","email":"sboyd@codeaurora.org"},"content":"On 09/20, Jernej Skrabec wrote:\n> When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.\n> \n> Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.\n> \n> Signed-off-by: Jernej Skrabec \n> Signed-off-by: Icenowy Zheng \n> ---\n\nAcked-by: Stephen Boyd ","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"kTzyv9UF\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"GM1//mqw\"; \n\tdkim-atps=neutral","pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org","pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=sboyd@codeaurora.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3ySGgq2yq9z9t30\n\tfor ;\n\tThu, 2 Nov 2017 18:20:07 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1755098AbdKBHTw (ORCPT\n\t);\n\tThu, 2 Nov 2017 03:19:52 -0400","from smtp.codeaurora.org ([198.145.29.96]:54800 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750907AbdKBHTv (ORCPT\n\t); Thu, 2 Nov 2017 03:19:51 -0400","by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid CD92F607CA; Thu, 2 Nov 2017 07:19:50 +0000 (UTC)","from localhost (i-global254.qualcomm.com [199.106.103.254])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: sboyd@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id BBBEA6085C;\n\tThu, 2 Nov 2017 07:19:43 +0000 (UTC)"],"DKIM-Signature":["v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1509607190;\n\tbh=OEnFs+E46nwCMp/pRNP9OygHW6bGIieUhL4x4PpdOcc=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=kTzyv9UFUKcquJps9Y0/u7ZkOkisqYIQAEUhVbZ3Yw482KMpSItUfE51BQOFYyXkd\n\tRsVczei2QtCyqymIBnKZf1ujKeOGUHaGfyFc1AVnkW5CpDeZtx/QL6AY9chlCH2K3D\n\tOMWJRTuIJFQO04OIvn+ztB1ThvbhFBW/xqeExezM=","v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1509607183;\n\tbh=OEnFs+E46nwCMp/pRNP9OygHW6bGIieUhL4x4PpdOcc=;\n\th=Date:From:To:Cc:Subject:References:In-Reply-To:From;\n\tb=GM1//mqwomvbJoNoma0Igcq7K8gwyRcYKCNV2NuiS7RchHz5cCAnZ0WsKpwa47f5R\n\tNyvdh/31Zf7B/sZsc9DpBM+xkyRzfgj2azDMdCkVXIIvPq/7SZRbu1nUiyvBcKiwXH\n\t6VjY6Ts9cCNlr43yTRE2nUikdD/TKkgJVb+s/eSQ="],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org","X-Spam-Level":"","X-Spam-Status":"No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0","DMARC-Filter":"OpenDMARC Filter v1.3.2 smtp.codeaurora.org BBBEA6085C","Date":"Thu, 2 Nov 2017 00:19:42 -0700","From":"Stephen Boyd ","To":"Jernej Skrabec ","Cc":"maxime.ripard@free-electrons.com, wens@csie.org,\n\tLaurent.pinchart@ideasonboard.com, hans.verkuil@cisco.com,\n\tnarmstrong@baylibre.com, dri-devel@lists.freedesktop.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,\n\ticenowy@aosc.io, linux-sunxi@googlegroups.com,\n\tlinux-media@vger.kernel.org","Subject":"Re: [RESEND RFC PATCH 3/7] clk: sunxi: Add CLK_SET_RATE_PARENT flag\n\tfor H3 HDMI clock","Message-ID":"<20171102071942.GN30645@codeaurora.org>","References":"<20170920200124.20457-1-jernej.skrabec@siol.net>\n\t<20170920200124.20457-4-jernej.skrabec@siol.net>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170920200124.20457-4-jernej.skrabec@siol.net>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]