[{"id":1771715,"web_url":"http://patchwork.ozlabs.org/comment/1771715/","msgid":"<15262fbd-7750-bb70-9336-42ff9d1b26d8@kapsi.fi>","list_archive_url":null,"date":"2017-09-20T09:52:50","subject":"Re: [PATCH 0/4] Add Tegra186 PCIe support","submitter":{"id":64745,"url":"http://patchwork.ozlabs.org/api/people/64745/","name":"Mikko Perttunen","email":"cyndis@kapsi.fi"},"content":"The series,\n\nReviewed-by: Mikko Perttunen \nTested-by: Mikko Perttunen \n\nverified with an Intel 82574L ethernet card.\n\nMikko\n\nOn 20.09.2017 09:42, Manikanta Maddireddy wrote:\n> Tegra186 has three PCIe controllers which can be operated\n> in 401, 211 or 111 lane configurations. Tegra TX2 platform\n> has x4 and M.2 Key E PCIe slots, these patches enables\n> x4 slot. BPMP programs UPHY lane0 ownership to USB,\n> so M.2 Key E PCIe will not work.\n>\n> Testing: x4 slot is verified with PCIe based USB3.1 card.\n> PCIe link up, usb flash drive mounting and file copy are\n> verified. Pasting PCIe link up logs below.\n>\n> [ 1.452512] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n> [ 1.452723] tegra-pcie 10003000.pcie: Failed to get supply 'dvdd-pex': -517\n> [ 1.561824] ehci-pci: EHCI PCI platform driver\n> [ 1.591587] ohci-pci: OHCI PCI platform driver\n> [ 3.072464] tegra-pcie 10003000.pcie: 4x1, 1x1 configuration\n> [ 3.078989] tegra-pcie 10003000.pcie: probing port 0, using 4 lanes\n> [ 3.087272] tegra-pcie 10003000.pcie: Slot present pin change, signature: 00000018\n> [ 3.128818] tegra-pcie 10003000.pcie: PCI host bridge to bus 0000:00\n> [ 3.135174] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\n> [ 3.141352] pci_bus 0000:00: root bus resource [mem 0x50100000-0x57ffffff]\n> [ 3.148221] pci_bus 0000:00: root bus resource [mem 0x58000000-0x7fffffff pref]\n> [ 3.155542] pci_bus 0000:00: root bus resource [bus 00-ff]\n> [ 3.161173] pci 0000:00:01.0: [10de:10e5] type 01 class 0x060400\n> [ 3.161188] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n> [ 3.170838] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4 may corrupt adjacent RW1C bits\n> [ 3.180532] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x52 may corrupt adjacent RW1C bits\n> [ 3.190305] pci 0000:00:01.0: PME# supported from D0 D1 D2 D3hot D3cold\n> [ 3.190312] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x4c may corrupt adjacent RW1C bits\n> [ 3.200158] pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring\n> [ 3.208158] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n> [ 3.217918] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n> [ 3.227649] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x3e may corrupt adjacent RW1C bits\n> [ 3.237382] pci_bus 0000:00: 2-byte config write to 0000:00:01.0 offset 0x6 may corrupt adjacent RW1C bits\n> [ 3.247135] pci 0000:01:00.0: [1b21:1242] type 00 class 0x0c0330\n> [ 3.247157] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n> [ 3.256807] pci_bus 0000:01: 2-byte config write to 0000:01:00.0 offset 0x4 may corrupt adjacent RW1C bits\n> [ 3.266477] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]\n> [ 3.266544] pci 0000:01:00.0: enabling Extended Tags\n> [ 3.271622] pci 0000:01:00.0: PME# supported from D3hot D3cold\n> [ 3.271775] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01\n> [ 3.271798] pci 0000:00:01.0: BAR 14: assigned [mem 0x50100000-0x501fffff]\n> [ 3.278671] pci 0000:01:00.0: BAR 0: assigned [mem 0x50100000-0x50107fff 64bit]\n> [ 3.285993] pci 0000:00:01.0: PCI bridge to [bus 01]\n> [ 3.290959] pci 0000:00:01.0: bridge window [mem 0x50100000-0x501fffff]\n> [ 3.297763] pci 0000:00:01.0: nv_msi_ht_cap_quirk didn't locate host bridge\n> [ 3.304784] pcieport 0000:00:01.0: enabling device (0000 -> 0002)\n> [ 3.311014] pcieport 0000:00:01.0: Signaling PME with IRQ 57\n> [ 3.316768] pci 0000:01:00.0: enabling device (0000 -> 0002)\n>\n> Manikanta Maddireddy (4):\n> dt-bindings: pci: tegra: Document Tegra186 PCIe DT\n> PCI: tegra: Add Tegra186 PCIe support\n> arm64: tegra: Add PCIe node for Tegra186\n> arm64: tegra: Enable PCIe on Jetson TX2\n>\n> .../bindings/pci/nvidia,tegra20-pcie.txt | 134 ++++++++++++++++++++-\n> arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 24 ++++\n> arch/arm64/boot/dts/nvidia/tegra186.dtsi | 82 +++++++++++++\n> drivers/pci/host/pci-tegra.c | 123 +++++++++++++++----\n> 4 files changed, 338 insertions(+), 25 deletions(-)\n>\n--\nTo unsubscribe from this list: send the line \"unsubscribe linux-tegra\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kapsi.fi;\n\ts=20161220; \n\th=Content-Transfer-Encoding:Content-Type:In-Reply-To:MIME-Version:Date:Message-ID:From:Cc:References:To:Subject;\n\tbh=mhmAL4+ZB2CWvuaBHr8Ykm9FDBPu5i3gsGyS1WVD58c=; \n\tb=yYN/avJcaI983EvruTXHGWG6RqtrsdmFnKrRRJm5pIfTkY8zrt3zNkl/mau3dWMUdrvKVCSdCtsTa/pbqIdceGPlzmGnP5IxVV397kkzS23QLxVF32hlh4+U3EqVZ6ho6zKs4+dbfQl8n4m5URQS8AnQq7XP4U0jXu+4lFS5i3aqc7MBFMW5eQgEkzslMwEmXIu4+FyAeFNKfAarBaTH0j1FHy66X2oiBfEuLH2macN332PHZvDePcjAexchIiJ8h4IWftuKTxsM6TPWdukzUJ5kVNSYh8EQ0wySLRw0gHQjQh2PA9hkT6Q5nu/PWinxyoP4TyLrnUll3RUDLW+U8w==;","Subject":"Re: [PATCH 0/4] Add Tegra186 PCIe support","To":"Manikanta Maddireddy , bhelgaas@google.com,\n\tthierry.reding@gmail.com, jonathanh@nvidia.com","References":"<1505889764-19397-1-git-send-email-mmaddireddy@nvidia.com>","Cc":"linux-tegra@vger.kernel.org, linux-pci@vger.kernel.org","From":"Mikko Perttunen ","Message-ID":"<15262fbd-7750-bb70-9336-42ff9d1b26d8@kapsi.fi>","Date":"Wed, 20 Sep 2017 12:52:50 +0300","User-Agent":"Mozilla/5.0 (X11; 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