[{"id":1771154,"web_url":"http://patchwork.ozlabs.org/comment/1771154/","msgid":"<1505834813.16414.5.camel@mtksdaap41>","list_archive_url":null,"date":"2017-09-19T15:26:53","subject":"Re: [PATCH v1 3/4] arm: dts: mt7623: add display related nodes","submitter":{"id":65928,"url":"http://patchwork.ozlabs.org/api/people/65928/","name":"CK Hu (胡俊光)","email":"ck.hu@mediatek.com"},"content":"Hi, Ryder:\n\nSome comment inline.\n\nOn Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote:\n> This patch adds the device nodes for the display function block.\n> Also, we add some missing pin macros in mt7623-pinfunc.h.\n> \n> Signed-off-by: Ryder Lee \n> CC: Linus Walleij \n> Acked-by: Linus Walleij \n> ---\n> arch/arm/boot/dts/mt7623.dtsi | 210 ++++++++++++++++++++++++++\n> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 41 ++++-\n> include/dt-bindings/pinctrl/mt7623-pinfunc.h | 12 ++\n> 3 files changed, 261 insertions(+), 2 deletions(-)\n> \n> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi\n> index 9ec3767..e11e5e7 100644\n> --- a/arch/arm/boot/dts/mt7623.dtsi\n> +++ b/arch/arm/boot/dts/mt7623.dtsi\n> @@ -20,6 +20,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \"skeleton64.dtsi\"\n> @@ -28,6 +29,11 @@\n> \tcompatible = \"mediatek,mt7623\";\n> \tinterrupt-parent = <&sysirq>;\n> \n> +\taliases {\n> +\t\trdma0 = &rdma0;\n> +\t\trdma1 = &rdma1;\n\nFor display, are these two aliases enough?\n\n> +\t};\n> +\n> \tcpu_opp_table: opp_table {\n> \t\tcompatible = \"operating-points-v2\";\n> \t\topp-shared;\n> @@ -273,6 +279,17 @@\n> \t\t\t ;\n> \t};\n> \n> +\tsmi_common: smi@1000c000 {\n> +\t\tcompatible = \"mediatek,mt7623-smi-common\",\n> +\t\t\t \"mediatek,mt2701-smi-common\";\n> +\t\treg = <0 0x1000c000 0 0x1000>;\n> +\t\tclocks = <&infracfg CLK_INFRA_SMI>,\n> +\t\t\t <&mmsys CLK_MM_SMI_COMMON>,\n> +\t\t\t <&infracfg CLK_INFRA_SMI>;\n> +\t\tclock-names = \"apb\", \"smi\", \"async\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n> +\t};\n> +\n> \tpwrap: pwrap@1000d000 {\n> \t\tcompatible = \"mediatek,mt7623-pwrap\",\n> \t\t\t \"mediatek,mt2701-pwrap\";\n> @@ -286,6 +303,17 @@\n> \t\tclock-names = \"spi\", \"wrap\";\n> \t};\n> \n> +\tmipi_tx0: mipi-dphy@10010000 {\n> +\t\tcompatible = \"mediatek,mt7623-mipi-tx\",\n> +\t\t\t \"mediatek,mt2701-mipi-tx\";\n> +\t\treg = <0 0x10010000 0 0x90>;\n> +\t\tclocks = <&clk26m>;\n> +\t\tclock-output-names = \"mipi_tx0_pll\";\n> +\t\t#clock-cells = <0>;\n> +\t\t#phy-cells = <0>;\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n> \tcir: cir@10013000 {\n> \t\tcompatible = \"mediatek,mt7623-cir\";\n> \t\treg = <0 0x10013000 0 0x1000>;\n> @@ -304,6 +332,17 @@\n> \t\treg = <0 0x10200100 0 0x1c>;\n> \t};\n> \n> +\tiommu: mmsys_iommu@10205000 {\n> +\t\tcompatible = \"mediatek,mt7623-m4u\",\n> +\t\t\t \"mediatek,mt2701-m4u\";\n> +\t\treg = <0 0x10205000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&infracfg CLK_INFRA_M4U>;\n> +\t\tclock-names = \"bclk\";\n> +\t\tmediatek,larbs = <&larb0 &larb1 &larb2>;\n> +\t\t#iommu-cells = <1>;\n> +\t};\n> +\n> \tefuse: efuse@10206000 {\n> \t\tcompatible = \"mediatek,mt7623-efuse\",\n> \t\t\t \"mediatek,mt8173-efuse\";\n> @@ -661,6 +700,169 @@\n> \t\tstatus = \"disabled\";\n> \t};\n> \n> +\tmmsys: syscon@14000000 {\n> +\t\tcompatible = \"mediatek,mt7623-mmsys\",\n> +\t\t\t \"mediatek,mt2701-mmsys\",\n> +\t\t\t \"syscon\";\n> +\t\treg = <0 0x14000000 0 0x1000>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tdisplay_components: dispsys@14000000 {\n> +\t\tcompatible = \"mediatek,mt7623-mmsys\",\n> +\t\t\t \"mediatek,mt2701-mmsys\";\n> +\t\treg = <0 0x14000000 0 0x1000>;\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n> +\t};\n> +\n> +\tovl@14007000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-ovl\",\n> +\t\t\t \"mediatek,mt2701-disp-ovl\";\n> +\t\treg = <0 0x14007000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_OVL>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;\n> +\t\tmediatek,larb = <&larb0>;\n> +\t};\n> +\n> +\trdma0: rdma@14008000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-rdma\",\n> +\t\t\t \"mediatek,mt2701-disp-rdma\";\n> +\t\treg = <0 0x14008000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_RDMA>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;\n> +\t\tmediatek,larb = <&larb0>;\n> +\t};\n> +\n> +\twdma@14009000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-wdma\",\n> +\t\t\t \"mediatek,mt2701-disp-wdma\";\n\nThere is neither \"mediatek,mt7623-disp-wdma\" nor\n\"mediatek,mt2701-disp-wdma\" in driver, do you really need this device\nnode?\n\n> +\t\treg = <0 0x14009000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_WDMA>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;\n> +\t\tmediatek,larb = <&larb0>;\n> +\t};\n> +\n> +\tbls: bls@1400a000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-pwm\",\n> +\t\t\t \"mediatek,mt2701-disp-pwm\";\n> +\t\treg = <0 0x1400a000 0 0x1000>;\n> +\t\t#pwm-cells = <2>;\n> +\t\tclocks = <&mmsys CLK_MM_MDP_BLS_26M>,\n> +\t\t\t <&mmsys CLK_MM_DISP_BLS>;\n> +\t\tclock-names = \"main\", \"mm\";\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n> +\tcolor@1400b000 {\n\ncolor: color@1400b000 {\n\n> +\t\tcompatible = \"mediatek,mt7623-disp-color\",\n> +\t\t\t \"mediatek,mt2701-disp-color\";\n> +\t\treg = <0 0x1400b000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_COLOR>;\n> +\t};\n> +\n> +\tdsi: dsi@1400c000 {\n> +\t\tcompatible = \"mediatek,mt7623-dsi\",\n> +\t\t\t \"mediatek,mt2701-dsi\";\n> +\t\treg = <0 0x1400c000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DSI_ENGINE>,\n> +\t\t\t <&mmsys CLK_MM_DSI_DIG>,\n> +\t\t\t <&mipi_tx0>;\n> +\t\tclock-names = \"engine\", \"digital\", \"hs\";\n> +\t\tphys = <&mipi_tx0>;\n> +\t\tphy-names = \"dphy\";\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n> +\tmutex: mutex@1400e000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-mutex\",\n> +\t\t\t \"mediatek,mt2701-disp-mutex\";\n> +\t\treg = <0 0x1400e000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_MUTEX_32K>;\n> +\t};\n> +\n> +\tlarb0: larb@14010000 {\n> +\t\tcompatible = \"mediatek,mt7623-smi-larb\",\n> +\t\t\t \"mediatek,mt2701-smi-larb\";\n> +\t\treg = <0 0x14010000 0 0x1000>;\n> +\t\tmediatek,smi = <&smi_common>;\n> +\t\tmediatek,larb-id = <0>;\n> +\t\tclocks = <&mmsys CLK_MM_SMI_LARB0>,\n> +\t\t\t <&mmsys CLK_MM_SMI_LARB0>;\n> +\t\tclock-names = \"apb\", \"smi\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n> +\t};\n> +\n> +\trdma1: rdma@14012000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-rdma\",\n> +\t\t\t \"mediatek,mt2701-disp-rdma\";\n> +\t\treg = <0 0x14012000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_RDMA1>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;\n> +\t\tmediatek,larb = <&larb0>;\n> +\t};\n> +\n> +\timgsys: syscon@15000000 {\n> +\t\tcompatible = \"mediatek,mt7623-imgsys\",\n> +\t\t\t \"mediatek,mt2701-imgsys\",\n> +\t\t\t \"syscon\";\n> +\t\treg = <0 0x15000000 0 0x1000>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tlarb2: larb@15001000 {\n> +\t\tcompatible = \"mediatek,mt7623-smi-larb\",\n> +\t\t\t \"mediatek,mt2701-smi-larb\";\n> +\t\treg = <0 0x15001000 0 0x1000>;\n> +\t\tmediatek,smi = <&smi_common>;\n> +\t\tmediatek,larb-id = <2>;\n> +\t\tclocks = <&imgsys CLK_IMG_SMI_COMM>,\n> +\t\t\t <&imgsys CLK_IMG_SMI_COMM>;\n> +\t\tclock-names = \"apb\", \"smi\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;\n> +\t};\n> +\n> +\tjpegdec: jpegdec@15004000 {\n> +\t\tcompatible = \"mediatek,mt7623-jpgdec\",\n> +\t\t\t \"mediatek,mt2701-jpgdec\";\n> +\t\treg = <0 0x15004000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&imgsys CLK_IMG_JPGDEC_SMI>,\n> +\t\t\t <&imgsys CLK_IMG_JPGDEC>;\n> +\t\tclock-names = \"jpgdec-smi\",\n> +\t\t\t \"jpgdec\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;\n> +\t\tmediatek,larb = <&larb2>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,\n> +\t\t\t <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;\n> +\t};\n> +\n> +\tvdecsys: syscon@16000000 {\n> +\t\tcompatible = \"mediatek,mt7623-vdecsys\",\n> +\t\t\t \"mediatek,mt2701-vdecsys\",\n> +\t\t\t \"syscon\";\n> +\t\treg = <0 0x16000000 0 0x1000>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tlarb1: larb@16010000 {\n> +\t\tcompatible = \"mediatek,mt7623-smi-larb\",\n> +\t\t\t \"mediatek,mt2701-smi-larb\";\n> +\t\treg = <0 0x16010000 0 0x1000>;\n> +\t\tmediatek,smi = <&smi_common>;\n> +\t\tmediatek,larb-id = <1>;\n> +\t\tclocks = <&vdecsys CLK_VDEC_CKGEN>,\n> +\t\t\t <&vdecsys CLK_VDEC_LARB>;\n> +\t\tclock-names = \"apb\", \"smi\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;\n> +\t};\n> +\n> \thifsys: syscon@1a000000 {\n> \t\tcompatible = \"mediatek,mt7623-hifsys\",\n> \t\t\t \"mediatek,mt2701-hifsys\",\n> @@ -799,4 +1001,12 @@\n> \t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;\n> \t\tstatus = \"disabled\";\n> \t};\n> +\n> +\tbdpsys: syscon@1c000000 {\n> +\t\tcompatible = \"mediatek,mt7623-bdpsys\",\n> +\t\t\t \"mediatek,mt2701-bdpsys\",\n> +\t\t\t \"syscon\";\n> +\t\treg = <0 0x1c000000 0 0x1000>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> };\n> diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n> index 688a863..267a05a 100644\n> --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n> +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n> @@ -17,6 +17,17 @@\n> \t\tserial2 = &uart2;\n> \t};\n> \n> +\tbacklight_lcd: backlight_lcd {\n> +\t\tcompatible = \"pwm-backlight\";\n> +\t\tpwms = <&bls 0 100000>;\n> +\t\tbrightness-levels = <\n> +\t\t\t 0 16 32 48 64 80 96 112\n> +\t\t\t128 144 160 176 192 208 224 240\n> +\t\t\t255\n> +\t\t>;\n> +\t\tdefault-brightness-level = <9>;\n> +\t};\n> +\n> \tchosen {\n> \t\tstdout-path = \"serial2:115200n8\";\n> \t};\n> @@ -86,6 +97,12 @@\n> \t};\n> };\n> \n> +&bls {\n> +\tstatus = \"okay\";\n> +\tpinctrl-names = \"default\";\n> +\tpinctrl-0 = <&bls_pins_a>;\n> +};\n> +\n> &cir {\n> \tpinctrl-names = \"default\";\n> \tpinctrl-0 = <&cir_pins_a>;\n> @@ -210,6 +227,12 @@\n> };\n> \n> &pio {\n> +\tbls_pins_a: bls@0 {\n> +\t\tpins_cmd_dat {\n> +\t\t\tpinmux = ;\n> +\t\t};\n> +\t};\n> +\n> \tcir_pins_a:cir@0 {\n> \t\tpins_cir {\n> \t\t\tpinmux = ;\n> @@ -273,6 +296,21 @@\n> \t\t};\n> \t};\n> \n> +\tmipi_dsi_pin: mipi_dsi_pin {\n> +\t\tpins_cmd_dat {\n> +\t\t\tpinmux = ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ;\n> +\t\t};\n> +\t};\n> +\n> \tmmc0_pins_default: mmc0default {\n> \t\tpins_cmd_dat {\n> \t\t\tpinmux = ,\n> @@ -378,8 +416,7 @@\n> \n> \tpwm_pins_a: pwm@0 {\n> \t\tpins_pwm {\n> -\t\t\tpinmux = ,\n> -\t\t\t\t ,\n> +\t\t\tpinmux = ,\n> \t\t\t\t ,\n> \t\t\t\t ,\n> \t\t\t\t ;\n> diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h\n> index 436a87b..72bed67 100644\n> --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h\n> +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h\n> @@ -272,6 +272,18 @@\n> #define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0)\n> #define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1)\n> \n> +#define MT7623_PIN_91_MIPI_TDN3_FUNC_GPIO91 (MTK_PIN_NO(91) | 0)\n> +#define MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3 (MTK_PIN_NO(91) | 1)\n> +\n> +#define MT7623_PIN_92_MIPI_TDP3_FUNC_GPIO92 (MTK_PIN_NO(92) | 0)\n> +#define MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3 (MTK_PIN_NO(92) | 1)\n> +\n> +#define MT7623_PIN_93_MIPI_TDN2_FUNC_GPIO93 (MTK_PIN_NO(93) | 0)\n> +#define MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2 (MTK_PIN_NO(93) | 1)\n> +\n> +#define MT7623_PIN_94_MIPI_TDP2_FUNC_GPIO94 (MTK_PIN_NO(94) | 0)\n> +#define MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2 (MTK_PIN_NO(94) | 1)\n> +\n> #define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0)\n> #define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1)\n> \n\nRegards,\nCK\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxRZ34f0Cz9s7g\n\tfor ;\n\tWed, 20 Sep 2017 01:27:07 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751394AbdISP1G (ORCPT\n\t);\n\tTue, 19 Sep 2017 11:27:06 -0400","from mailgw02.mediatek.com ([210.61.82.184]:47127 \"EHLO\n\tmailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751227AbdISP1F (ORCPT\n\t); Tue, 19 Sep 2017 11:27:05 -0400","from mtkcas06.mediatek.inc [(172.21.101.30)] by\n\tmailgw02.mediatek.com (envelope-from )\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 1561352790; Tue, 19 Sep 2017 23:27:00 +0800","from mtkcas08.mediatek.inc (172.21.101.126) by\n\tmtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Tue, 19 Sep 2017 23:26:38 +0800","from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Tue, 19 Sep 2017 23:26:24 +0800"],"X-UUID":"1718e193ec304fbfa69ef4fa4587abab-20170919","Message-ID":"<1505834813.16414.5.camel@mtksdaap41>","Subject":"Re: [PATCH v1 3/4] arm: dts: mt7623: add display related nodes","From":"CK Hu ","To":"Ryder Lee ","CC":"Matthias Brugger , , \n\tLinus Walleij , ,\n\t,\n\t","Date":"Tue, 19 Sep 2017 23:26:53 +0800","In-Reply-To":"<0eb19ae1a4717d316cdaec44f6c20bfa8aa24ddc.1505801355.git.ryder.lee@mediatek.com>","References":"\n\t<0eb19ae1a4717d316cdaec44f6c20bfa8aa24ddc.1505801355.git.ryder.lee@mediatek.com>","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailer":"Evolution 3.2.3-0ubuntu6 ","Content-Transfer-Encoding":"7bit","MIME-Version":"1.0","X-MTK":"N","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1771485,"web_url":"http://patchwork.ozlabs.org/comment/1771485/","msgid":"<1505869897.27600.6.camel@mtksdaap41>","list_archive_url":null,"date":"2017-09-20T01:11:37","subject":"Re: [PATCH v1 3/4] arm: dts: mt7623: add display related nodes","submitter":{"id":65928,"url":"http://patchwork.ozlabs.org/api/people/65928/","name":"CK Hu (胡俊光)","email":"ck.hu@mediatek.com"},"content":"Hi, Ryder:\n\nMode comment inline.\n\nOn Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote:\n> This patch adds the device nodes for the display function block.\n> Also, we add some missing pin macros in mt7623-pinfunc.h.\n> \n> Signed-off-by: Ryder Lee \n> CC: Linus Walleij \n> Acked-by: Linus Walleij \n> ---\n> arch/arm/boot/dts/mt7623.dtsi | 210 ++++++++++++++++++++++++++\n> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 41 ++++-\n> include/dt-bindings/pinctrl/mt7623-pinfunc.h | 12 ++\n> 3 files changed, 261 insertions(+), 2 deletions(-)\n> \n> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi\n> index 9ec3767..e11e5e7 100644\n> --- a/arch/arm/boot/dts/mt7623.dtsi\n> +++ b/arch/arm/boot/dts/mt7623.dtsi\n> @@ -20,6 +20,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \"skeleton64.dtsi\"\n> @@ -28,6 +29,11 @@\n> \tcompatible = \"mediatek,mt7623\";\n> \tinterrupt-parent = <&sysirq>;\n> \n> +\taliases {\n> +\t\trdma0 = &rdma0;\n> +\t\trdma1 = &rdma1;\n> +\t};\n> +\n> \tcpu_opp_table: opp_table {\n> \t\tcompatible = \"operating-points-v2\";\n> \t\topp-shared;\n> @@ -273,6 +279,17 @@\n> \t\t\t ;\n> \t};\n> \n> +\tsmi_common: smi@1000c000 {\n> +\t\tcompatible = \"mediatek,mt7623-smi-common\",\n> +\t\t\t \"mediatek,mt2701-smi-common\";\n> +\t\treg = <0 0x1000c000 0 0x1000>;\n> +\t\tclocks = <&infracfg CLK_INFRA_SMI>,\n> +\t\t\t <&mmsys CLK_MM_SMI_COMMON>,\n> +\t\t\t <&infracfg CLK_INFRA_SMI>;\n> +\t\tclock-names = \"apb\", \"smi\", \"async\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n> +\t};\n> +\n> \tpwrap: pwrap@1000d000 {\n> \t\tcompatible = \"mediatek,mt7623-pwrap\",\n> \t\t\t \"mediatek,mt2701-pwrap\";\n> @@ -286,6 +303,17 @@\n> \t\tclock-names = \"spi\", \"wrap\";\n> \t};\n> \n> +\tmipi_tx0: mipi-dphy@10010000 {\n> +\t\tcompatible = \"mediatek,mt7623-mipi-tx\",\n> +\t\t\t \"mediatek,mt2701-mipi-tx\";\n> +\t\treg = <0 0x10010000 0 0x90>;\n> +\t\tclocks = <&clk26m>;\n> +\t\tclock-output-names = \"mipi_tx0_pll\";\n> +\t\t#clock-cells = <0>;\n> +\t\t#phy-cells = <0>;\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n> \tcir: cir@10013000 {\n> \t\tcompatible = \"mediatek,mt7623-cir\";\n> \t\treg = <0 0x10013000 0 0x1000>;\n> @@ -304,6 +332,17 @@\n> \t\treg = <0 0x10200100 0 0x1c>;\n> \t};\n> \n> +\tiommu: mmsys_iommu@10205000 {\n> +\t\tcompatible = \"mediatek,mt7623-m4u\",\n> +\t\t\t \"mediatek,mt2701-m4u\";\n> +\t\treg = <0 0x10205000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&infracfg CLK_INFRA_M4U>;\n> +\t\tclock-names = \"bclk\";\n> +\t\tmediatek,larbs = <&larb0 &larb1 &larb2>;\n> +\t\t#iommu-cells = <1>;\n> +\t};\n> +\n> \tefuse: efuse@10206000 {\n> \t\tcompatible = \"mediatek,mt7623-efuse\",\n> \t\t\t \"mediatek,mt8173-efuse\";\n> @@ -661,6 +700,169 @@\n> \t\tstatus = \"disabled\";\n> \t};\n> \n> +\tmmsys: syscon@14000000 {\n> +\t\tcompatible = \"mediatek,mt7623-mmsys\",\n> +\t\t\t \"mediatek,mt2701-mmsys\",\n> +\t\t\t \"syscon\";\n> +\t\treg = <0 0x14000000 0 0x1000>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tdisplay_components: dispsys@14000000 {\n> +\t\tcompatible = \"mediatek,mt7623-mmsys\",\n> +\t\t\t \"mediatek,mt2701-mmsys\";\n> +\t\treg = <0 0x14000000 0 0x1000>;\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n> +\t};\n> +\n> +\tovl@14007000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-ovl\",\n> +\t\t\t \"mediatek,mt2701-disp-ovl\";\n> +\t\treg = <0 0x14007000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_OVL>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;\n> +\t\tmediatek,larb = <&larb0>;\n> +\t};\n> +\n> +\trdma0: rdma@14008000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-rdma\",\n> +\t\t\t \"mediatek,mt2701-disp-rdma\";\n> +\t\treg = <0 0x14008000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_RDMA>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;\n> +\t\tmediatek,larb = <&larb0>;\n> +\t};\n> +\n> +\twdma@14009000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-wdma\",\n> +\t\t\t \"mediatek,mt2701-disp-wdma\";\n> +\t\treg = <0 0x14009000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_WDMA>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;\n> +\t\tmediatek,larb = <&larb0>;\n> +\t};\n> +\n> +\tbls: bls@1400a000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-pwm\",\n> +\t\t\t \"mediatek,mt2701-disp-pwm\";\n> +\t\treg = <0 0x1400a000 0 0x1000>;\n> +\t\t#pwm-cells = <2>;\n> +\t\tclocks = <&mmsys CLK_MM_MDP_BLS_26M>,\n> +\t\t\t <&mmsys CLK_MM_DISP_BLS>;\n> +\t\tclock-names = \"main\", \"mm\";\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n> +\tcolor@1400b000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-color\",\n> +\t\t\t \"mediatek,mt2701-disp-color\";\n> +\t\treg = <0 0x1400b000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_COLOR>;\n> +\t};\n> +\n> +\tdsi: dsi@1400c000 {\n> +\t\tcompatible = \"mediatek,mt7623-dsi\",\n> +\t\t\t \"mediatek,mt2701-dsi\";\n> +\t\treg = <0 0x1400c000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DSI_ENGINE>,\n> +\t\t\t <&mmsys CLK_MM_DSI_DIG>,\n> +\t\t\t <&mipi_tx0>;\n> +\t\tclock-names = \"engine\", \"digital\", \"hs\";\n> +\t\tphys = <&mipi_tx0>;\n> +\t\tphy-names = \"dphy\";\n> +\t\tstatus = \"disabled\";\n> +\t};\n> +\n> +\tmutex: mutex@1400e000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-mutex\",\n> +\t\t\t \"mediatek,mt2701-disp-mutex\";\n> +\t\treg = <0 0x1400e000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_MUTEX_32K>;\n> +\t};\n> +\n> +\tlarb0: larb@14010000 {\n> +\t\tcompatible = \"mediatek,mt7623-smi-larb\",\n> +\t\t\t \"mediatek,mt2701-smi-larb\";\n> +\t\treg = <0 0x14010000 0 0x1000>;\n> +\t\tmediatek,smi = <&smi_common>;\n> +\t\tmediatek,larb-id = <0>;\n> +\t\tclocks = <&mmsys CLK_MM_SMI_LARB0>,\n> +\t\t\t <&mmsys CLK_MM_SMI_LARB0>;\n> +\t\tclock-names = \"apb\", \"smi\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n> +\t};\n> +\n> +\trdma1: rdma@14012000 {\n> +\t\tcompatible = \"mediatek,mt7623-disp-rdma\",\n> +\t\t\t \"mediatek,mt2701-disp-rdma\";\n> +\t\treg = <0 0x14012000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&mmsys CLK_MM_DISP_RDMA1>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;\n> +\t\tmediatek,larb = <&larb0>;\n> +\t};\n> +\n> +\timgsys: syscon@15000000 {\n> +\t\tcompatible = \"mediatek,mt7623-imgsys\",\n> +\t\t\t \"mediatek,mt2701-imgsys\",\n> +\t\t\t \"syscon\";\n> +\t\treg = <0 0x15000000 0 0x1000>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tlarb2: larb@15001000 {\n> +\t\tcompatible = \"mediatek,mt7623-smi-larb\",\n> +\t\t\t \"mediatek,mt2701-smi-larb\";\n> +\t\treg = <0 0x15001000 0 0x1000>;\n> +\t\tmediatek,smi = <&smi_common>;\n> +\t\tmediatek,larb-id = <2>;\n> +\t\tclocks = <&imgsys CLK_IMG_SMI_COMM>,\n> +\t\t\t <&imgsys CLK_IMG_SMI_COMM>;\n> +\t\tclock-names = \"apb\", \"smi\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;\n> +\t};\n> +\n> +\tjpegdec: jpegdec@15004000 {\n> +\t\tcompatible = \"mediatek,mt7623-jpgdec\",\n> +\t\t\t \"mediatek,mt2701-jpgdec\";\n> +\t\treg = <0 0x15004000 0 0x1000>;\n> +\t\tinterrupts = ;\n> +\t\tclocks = <&imgsys CLK_IMG_JPGDEC_SMI>,\n> +\t\t\t <&imgsys CLK_IMG_JPGDEC>;\n> +\t\tclock-names = \"jpgdec-smi\",\n> +\t\t\t \"jpgdec\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;\n> +\t\tmediatek,larb = <&larb2>;\n> +\t\tiommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,\n> +\t\t\t <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;\n> +\t};\n\njpegdec and some other device node is not related to display. I think\nyou should move them to another patch.\n\n> +\n> +\tvdecsys: syscon@16000000 {\n> +\t\tcompatible = \"mediatek,mt7623-vdecsys\",\n> +\t\t\t \"mediatek,mt2701-vdecsys\",\n> +\t\t\t \"syscon\";\n> +\t\treg = <0 0x16000000 0 0x1000>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> +\n> +\tlarb1: larb@16010000 {\n> +\t\tcompatible = \"mediatek,mt7623-smi-larb\",\n> +\t\t\t \"mediatek,mt2701-smi-larb\";\n> +\t\treg = <0 0x16010000 0 0x1000>;\n> +\t\tmediatek,smi = <&smi_common>;\n> +\t\tmediatek,larb-id = <1>;\n> +\t\tclocks = <&vdecsys CLK_VDEC_CKGEN>,\n> +\t\t\t <&vdecsys CLK_VDEC_LARB>;\n> +\t\tclock-names = \"apb\", \"smi\";\n> +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;\n> +\t};\n> +\n> \thifsys: syscon@1a000000 {\n> \t\tcompatible = \"mediatek,mt7623-hifsys\",\n> \t\t\t \"mediatek,mt2701-hifsys\",\n> @@ -799,4 +1001,12 @@\n> \t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;\n> \t\tstatus = \"disabled\";\n> \t};\n> +\n> +\tbdpsys: syscon@1c000000 {\n> +\t\tcompatible = \"mediatek,mt7623-bdpsys\",\n> +\t\t\t \"mediatek,mt2701-bdpsys\",\n> +\t\t\t \"syscon\";\n> +\t\treg = <0 0x1c000000 0 0x1000>;\n> +\t\t#clock-cells = <1>;\n> +\t};\n> };\n> diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n> index 688a863..267a05a 100644\n> --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n> +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n> @@ -17,6 +17,17 @@\n> \t\tserial2 = &uart2;\n> \t};\n> \n> +\tbacklight_lcd: backlight_lcd {\n> +\t\tcompatible = \"pwm-backlight\";\n> +\t\tpwms = <&bls 0 100000>;\n> +\t\tbrightness-levels = <\n> +\t\t\t 0 16 32 48 64 80 96 112\n> +\t\t\t128 144 160 176 192 208 224 240\n> +\t\t\t255\n> +\t\t>;\n> +\t\tdefault-brightness-level = <9>;\n> +\t};\n> +\n\nI think this patch only for mt7623 common dtsi modification. This part\nis just for bananapi-bpi-r2, so move non-common part to another patch.\n\n> \tchosen {\n> \t\tstdout-path = \"serial2:115200n8\";\n> \t};\n> @@ -86,6 +97,12 @@\n> \t};\n> };\n> \n> +&bls {\n> +\tstatus = \"okay\";\n> +\tpinctrl-names = \"default\";\n> +\tpinctrl-0 = <&bls_pins_a>;\n> +};\n> +\n> &cir {\n> \tpinctrl-names = \"default\";\n> \tpinctrl-0 = <&cir_pins_a>;\n> @@ -210,6 +227,12 @@\n> };\n> \n> &pio {\n> +\tbls_pins_a: bls@0 {\n> +\t\tpins_cmd_dat {\n> +\t\t\tpinmux = ;\n> +\t\t};\n> +\t};\n> +\n> \tcir_pins_a:cir@0 {\n> \t\tpins_cir {\n> \t\t\tpinmux = ;\n> @@ -273,6 +296,21 @@\n> \t\t};\n> \t};\n> \n> +\tmipi_dsi_pin: mipi_dsi_pin {\n> +\t\tpins_cmd_dat {\n> +\t\t\tpinmux = ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ,\n> +\t\t\t\t ;\n> +\t\t};\n> +\t};\n> +\n> \tmmc0_pins_default: mmc0default {\n> \t\tpins_cmd_dat {\n> \t\t\tpinmux = ,\n> @@ -378,8 +416,7 @@\n> \n> \tpwm_pins_a: pwm@0 {\n> \t\tpins_pwm {\n> -\t\t\tpinmux = ,\n> -\t\t\t\t ,\n> +\t\t\tpinmux = ,\n> \t\t\t\t ,\n> \t\t\t\t ,\n> \t\t\t\t ;\n> diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h\n> index 436a87b..72bed67 100644\n> --- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h\n> +++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h\n> @@ -272,6 +272,18 @@\n> #define MT7623_PIN_84_DSI_TE_FUNC_GPIO84 (MTK_PIN_NO(84) | 0)\n> #define MT7623_PIN_84_DSI_TE_FUNC_DSI_TE (MTK_PIN_NO(84) | 1)\n> \n> +#define MT7623_PIN_91_MIPI_TDN3_FUNC_GPIO91 (MTK_PIN_NO(91) | 0)\n> +#define MT7623_PIN_91_MIPI_TDN3_FUNC_TDN3 (MTK_PIN_NO(91) | 1)\n> +\n> +#define MT7623_PIN_92_MIPI_TDP3_FUNC_GPIO92 (MTK_PIN_NO(92) | 0)\n> +#define MT7623_PIN_92_MIPI_TDP3_FUNC_TDP3 (MTK_PIN_NO(92) | 1)\n> +\n> +#define MT7623_PIN_93_MIPI_TDN2_FUNC_GPIO93 (MTK_PIN_NO(93) | 0)\n> +#define MT7623_PIN_93_MIPI_TDN2_FUNC_TDN2 (MTK_PIN_NO(93) | 1)\n> +\n> +#define MT7623_PIN_94_MIPI_TDP2_FUNC_GPIO94 (MTK_PIN_NO(94) | 0)\n> +#define MT7623_PIN_94_MIPI_TDP2_FUNC_TDP2 (MTK_PIN_NO(94) | 1)\n> +\n> #define MT7623_PIN_95_MIPI_TCN_FUNC_GPIO95 (MTK_PIN_NO(95) | 0)\n> #define MT7623_PIN_95_MIPI_TCN_FUNC_TCN (MTK_PIN_NO(95) | 1)\n> \n\nRegards,\nCK\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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Wed, 20 Sep 2017 09:11:53 +0800"],"X-UUID":"3ed18ea5b8994da59edca09b88069032-20170920","Message-ID":"<1505869897.27600.6.camel@mtksdaap41>","Subject":"Re: [PATCH v1 3/4] arm: dts: mt7623: add display related nodes","From":"CK Hu ","To":"Ryder Lee ","CC":"Matthias Brugger , , \n\tLinus Walleij , ,\n\t,\n\t","Date":"Wed, 20 Sep 2017 09:11:37 +0800","In-Reply-To":"<0eb19ae1a4717d316cdaec44f6c20bfa8aa24ddc.1505801355.git.ryder.lee@mediatek.com>","References":"\n\t<0eb19ae1a4717d316cdaec44f6c20bfa8aa24ddc.1505801355.git.ryder.lee@mediatek.com>","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailer":"Evolution 3.2.3-0ubuntu6 ","Content-Transfer-Encoding":"7bit","MIME-Version":"1.0","X-MTK":"N","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772627,"web_url":"http://patchwork.ozlabs.org/comment/1772627/","msgid":"<1505987424.3084.8.camel@mtkswgap22>","list_archive_url":null,"date":"2017-09-21T09:50:24","subject":"Re: [PATCH v1 3/4] arm: dts: mt7623: add display related nodes","submitter":{"id":70514,"url":"http://patchwork.ozlabs.org/api/people/70514/","name":"Ryder Lee","email":"ryder.lee@mediatek.com"},"content":"On Tue, 2017-09-19 at 23:26 +0800, CK Hu wrote:\n> Hi, Ryder:\n> \n> Some comment inline.\n> \n> On Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote:\n> > This patch adds the device nodes for the display function block.\n> > Also, we add some missing pin macros in mt7623-pinfunc.h.\n> > \n> > Signed-off-by: Ryder Lee \n> > CC: Linus Walleij \n> > Acked-by: Linus Walleij \n> > ---\n> > arch/arm/boot/dts/mt7623.dtsi | 210 ++++++++++++++++++++++++++\n> > arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 41 ++++-\n> > include/dt-bindings/pinctrl/mt7623-pinfunc.h | 12 ++\n> > 3 files changed, 261 insertions(+), 2 deletions(-)\n> > \n> > diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi\n> > index 9ec3767..e11e5e7 100644\n> > --- a/arch/arm/boot/dts/mt7623.dtsi\n> > +++ b/arch/arm/boot/dts/mt7623.dtsi\n> > @@ -20,6 +20,7 @@\n> > #include \n> > #include \n> > #include \n> > +#include \n> > #include \n> > #include \n> > #include \"skeleton64.dtsi\"\n> > @@ -28,6 +29,11 @@\n> > \tcompatible = \"mediatek,mt7623\";\n> > \tinterrupt-parent = <&sysirq>;\n> > \n> > +\taliases {\n> > +\t\trdma0 = &rdma0;\n> > +\t\trdma1 = &rdma1;\n> \n> For display, are these two aliases enough?\n\nYes, this part is the same as mt2701.\n\nhttps://patchwork.kernel.org/patch/9803813/\n\n> > +\t};\n> > +\n\n...\n> > +\twdma@14009000 {\n> > +\t\tcompatible = \"mediatek,mt7623-disp-wdma\",\n> > +\t\t\t \"mediatek,mt2701-disp-wdma\";\n> \n> There is neither \"mediatek,mt7623-disp-wdma\" nor\n> \"mediatek,mt2701-disp-wdma\" in driver, do you really need this device\n> node?\n\nOkay, I will remove it.\n\n> > +\t\treg = <0 0x14009000 0 0x1000>;\n> > +\t\tinterrupts = ;\n> > +\t\tclocks = <&mmsys CLK_MM_DISP_WDMA>;\n> > +\t\tiommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;\n> > +\t\tmediatek,larb = <&larb0>;\n> > +\t};\n> > +\n> > +\tbls: bls@1400a000 {\n> > +\t\tcompatible = \"mediatek,mt7623-disp-pwm\",\n> > +\t\t\t \"mediatek,mt2701-disp-pwm\";\n> > +\t\treg = <0 0x1400a000 0 0x1000>;\n> > +\t\t#pwm-cells = <2>;\n> > +\t\tclocks = <&mmsys CLK_MM_MDP_BLS_26M>,\n> > +\t\t\t <&mmsys CLK_MM_DISP_BLS>;\n> > +\t\tclock-names = \"main\", \"mm\";\n> > +\t\tstatus = \"disabled\";\n> > +\t};\n> > +\n> > +\tcolor@1400b000 {\n> \n> color: color@1400b000 {\n\nOkay.\n> > +\t\tcompatible = \"mediatek,mt7623-disp-color\",\n> > +\t\t\t \"mediatek,mt2701-disp-color\";\n> > +\t\treg = <0 0x1400b000 0 0x1000>;\n> > +\t\tinterrupts = ;\n> > +\t\tclocks = <&mmsys CLK_MM_DISP_COLOR>;\n> > +\t};\n> > +\n\n\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyX0p4ypLz9t49\n\tfor ;\n\tThu, 21 Sep 2017 19:50:34 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751550AbdIUJud (ORCPT\n\t);\n\tThu, 21 Sep 2017 05:50:33 -0400","from mailgw02.mediatek.com ([210.61.82.184]:7831 \"EHLO\n\tmailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751521AbdIUJuc (ORCPT\n\t); Thu, 21 Sep 2017 05:50:32 -0400","from mtkcas09.mediatek.inc [(172.21.101.178)] by\n\tmailgw02.mediatek.com (envelope-from )\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 988510608; Thu, 21 Sep 2017 17:50:26 +0800","from mtkcas07.mediatek.inc (172.21.101.84) by\n\tmtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Thu, 21 Sep 2017 17:50:12 +0800","from [172.21.77.33] (172.21.77.33) by mtkcas07.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Thu, 21 Sep 2017 17:49:46 +0800"],"X-UUID":"130ece11292f4b1a9c72a96f557de6bb-20170921","Message-ID":"<1505987424.3084.8.camel@mtkswgap22>","Subject":"Re: [PATCH v1 3/4] arm: dts: mt7623: add display related nodes","From":"Ryder Lee ","To":"CK Hu ","CC":"Matthias Brugger , , \n\tLinus Walleij , ,\n\t,\n\t","Date":"Thu, 21 Sep 2017 17:50:24 +0800","In-Reply-To":"<1505834813.16414.5.camel@mtksdaap41>","References":"\n\t<0eb19ae1a4717d316cdaec44f6c20bfa8aa24ddc.1505801355.git.ryder.lee@mediatek.com>\n\t<1505834813.16414.5.camel@mtksdaap41>","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailer":"Evolution 3.2.3-0ubuntu6 ","Content-Transfer-Encoding":"7bit","MIME-Version":"1.0","X-MTK":"N","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772630,"web_url":"http://patchwork.ozlabs.org/comment/1772630/","msgid":"<1505987616.3084.12.camel@mtkswgap22>","list_archive_url":null,"date":"2017-09-21T09:53:36","subject":"Re: [PATCH v1 3/4] arm: dts: mt7623: add display related nodes","submitter":{"id":70514,"url":"http://patchwork.ozlabs.org/api/people/70514/","name":"Ryder Lee","email":"ryder.lee@mediatek.com"},"content":"On Wed, 2017-09-20 at 09:11 +0800, CK Hu wrote:\n> Hi, Ryder:\n> \n> Mode comment inline.\n> \n> On Tue, 2017-09-19 at 14:27 +0800, Ryder Lee wrote:\n> \n> > +\tsmi_common: smi@1000c000 {\n> > +\t\tcompatible = \"mediatek,mt7623-smi-common\",\n> > +\t\t\t \"mediatek,mt2701-smi-common\";\n> > +\t\treg = <0 0x1000c000 0 0x1000>;\n> > +\t\tclocks = <&infracfg CLK_INFRA_SMI>,\n> > +\t\t\t <&mmsys CLK_MM_SMI_COMMON>,\n> > +\t\t\t <&infracfg CLK_INFRA_SMI>;\n> > +\t\tclock-names = \"apb\", \"smi\", \"async\";\n> > +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n> > +\t};\n> > +\n\n> > +\tiommu: mmsys_iommu@10205000 {\n> > +\t\tcompatible = \"mediatek,mt7623-m4u\",\n> > +\t\t\t \"mediatek,mt2701-m4u\";\n> > +\t\treg = <0 0x10205000 0 0x1000>;\n> > +\t\tinterrupts = ;\n> > +\t\tclocks = <&infracfg CLK_INFRA_M4U>;\n> > +\t\tclock-names = \"bclk\";\n> > +\t\tmediatek,larbs = <&larb0 &larb1 &larb2>;\n> > +\t\t#iommu-cells = <1>;\n> > +\t};\n> > +\n> > +\tmmsys: syscon@14000000 {\n> > +\t\tcompatible = \"mediatek,mt7623-mmsys\",\n> > +\t\t\t \"mediatek,mt2701-mmsys\",\n> > +\t\t\t \"syscon\";\n> > +\t\treg = <0 0x14000000 0 0x1000>;\n> > +\t\t#clock-cells = <1>;\n> > +\t};\n> > +\n\n> > +\tlarb0: larb@14010000 {\n> > +\t\tcompatible = \"mediatek,mt7623-smi-larb\",\n> > +\t\t\t \"mediatek,mt2701-smi-larb\";\n> > +\t\treg = <0 0x14010000 0 0x1000>;\n> > +\t\tmediatek,smi = <&smi_common>;\n> > +\t\tmediatek,larb-id = <0>;\n> > +\t\tclocks = <&mmsys CLK_MM_SMI_LARB0>,\n> > +\t\t\t <&mmsys CLK_MM_SMI_LARB0>;\n> > +\t\tclock-names = \"apb\", \"smi\";\n> > +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;\n> > +\t};\n\n> > +\timgsys: syscon@15000000 {\n> > +\t\tcompatible = \"mediatek,mt7623-imgsys\",\n> > +\t\t\t \"mediatek,mt2701-imgsys\",\n> > +\t\t\t \"syscon\";\n> > +\t\treg = <0 0x15000000 0 0x1000>;\n> > +\t\t#clock-cells = <1>;\n> > +\t};\n> > +\n> > +\tlarb2: larb@15001000 {\n> > +\t\tcompatible = \"mediatek,mt7623-smi-larb\",\n> > +\t\t\t \"mediatek,mt2701-smi-larb\";\n> > +\t\treg = <0 0x15001000 0 0x1000>;\n> > +\t\tmediatek,smi = <&smi_common>;\n> > +\t\tmediatek,larb-id = <2>;\n> > +\t\tclocks = <&imgsys CLK_IMG_SMI_COMM>,\n> > +\t\t\t <&imgsys CLK_IMG_SMI_COMM>;\n> > +\t\tclock-names = \"apb\", \"smi\";\n> > +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;\n> > +\t};\n> > +\n> > +\tjpegdec: jpegdec@15004000 {\n> > +\t\tcompatible = \"mediatek,mt7623-jpgdec\",\n> > +\t\t\t \"mediatek,mt2701-jpgdec\";\n> > +\t\treg = <0 0x15004000 0 0x1000>;\n> > +\t\tinterrupts = ;\n> > +\t\tclocks = <&imgsys CLK_IMG_JPGDEC_SMI>,\n> > +\t\t\t <&imgsys CLK_IMG_JPGDEC>;\n> > +\t\tclock-names = \"jpgdec-smi\",\n> > +\t\t\t \"jpgdec\";\n> > +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;\n> > +\t\tmediatek,larb = <&larb2>;\n> > +\t\tiommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,\n> > +\t\t\t <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;\n> > +\t};\n> \n> jpegdec and some other device node is not related to display. I think\n> you should move them to another patch.\n\nYes, you're right.\n> > +\n> > +\tvdecsys: syscon@16000000 {\n> > +\t\tcompatible = \"mediatek,mt7623-vdecsys\",\n> > +\t\t\t \"mediatek,mt2701-vdecsys\",\n> > +\t\t\t \"syscon\";\n> > +\t\treg = <0 0x16000000 0 0x1000>;\n> > +\t\t#clock-cells = <1>;\n> > +\t};\n> > +\n> > +\tlarb1: larb@16010000 {\n> > +\t\tcompatible = \"mediatek,mt7623-smi-larb\",\n> > +\t\t\t \"mediatek,mt2701-smi-larb\";\n> > +\t\treg = <0 0x16010000 0 0x1000>;\n> > +\t\tmediatek,smi = <&smi_common>;\n> > +\t\tmediatek,larb-id = <1>;\n> > +\t\tclocks = <&vdecsys CLK_VDEC_CKGEN>,\n> > +\t\t\t <&vdecsys CLK_VDEC_LARB>;\n> > +\t\tclock-names = \"apb\", \"smi\";\n> > +\t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;\n> > +\t};\n> > +\n> > \thifsys: syscon@1a000000 {\n> > \t\tcompatible = \"mediatek,mt7623-hifsys\",\n> > \t\t\t \"mediatek,mt2701-hifsys\",\n> > @@ -799,4 +1001,12 @@\n> > \t\tpower-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;\n> > \t\tstatus = \"disabled\";\n> > \t};\n> > +\n> > +\tbdpsys: syscon@1c000000 {\n> > +\t\tcompatible = \"mediatek,mt7623-bdpsys\",\n> > +\t\t\t \"mediatek,mt2701-bdpsys\",\n> > +\t\t\t \"syscon\";\n> > +\t\treg = <0 0x1c000000 0 0x1000>;\n> > +\t\t#clock-cells = <1>;\n> > +\t};\n> > };\n\nI will move these nodes to different patches.\n\n> > diff --git a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n> > index 688a863..267a05a 100644\n> > --- a/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n> > +++ b/arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts\n> > @@ -17,6 +17,17 @@\n> > \t\tserial2 = &uart2;\n> > \t};\n> > \n> > +\tbacklight_lcd: backlight_lcd {\n> > +\t\tcompatible = \"pwm-backlight\";\n> > +\t\tpwms = <&bls 0 100000>;\n> > +\t\tbrightness-levels = <\n> > +\t\t\t 0 16 32 48 64 80 96 112\n> > +\t\t\t128 144 160 176 192 208 224 240\n> > +\t\t\t255\n> > +\t\t>;\n> > +\t\tdefault-brightness-level = <9>;\n> > +\t};\n> > +\n> \n> I think this patch only for mt7623 common dtsi modification. This part\n> is just for bananapi-bpi-r2, so move non-common part to another patch.\n> \nOkay.\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyX4S1Trdz9t4B\n\tfor ;\n\tThu, 21 Sep 2017 19:53:44 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751606AbdIUJxm (ORCPT\n\t);\n\tThu, 21 Sep 2017 05:53:42 -0400","from mailgw02.mediatek.com ([210.61.82.184]:10114 \"EHLO\n\tmailgw02.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1751528AbdIUJxl (ORCPT\n\t); Thu, 21 Sep 2017 05:53:41 -0400","from mtkcas08.mediatek.inc [(172.21.101.126)] by\n\tmailgw02.mediatek.com (envelope-from )\n\t(mhqrelay.mediatek.com ESMTP with TLS)\n\twith ESMTP id 902349530; Thu, 21 Sep 2017 17:53:37 +0800","from mtkcas08.mediatek.inc (172.21.101.126) by\n\tmtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server\n\t(TLS) id 15.0.1210.3; Thu, 21 Sep 2017 17:53:31 +0800","from [172.21.77.33] (172.21.77.33) by mtkcas08.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1210.3 via\n\tFrontend Transport; Thu, 21 Sep 2017 17:53:00 +0800"],"X-UUID":"6aaef63fb749440cac961445928bdfdd-20170921","Message-ID":"<1505987616.3084.12.camel@mtkswgap22>","Subject":"Re: [PATCH v1 3/4] arm: dts: mt7623: add display related nodes","From":"Ryder Lee ","To":"CK Hu ","CC":"Matthias Brugger , , \n\tLinus Walleij , ,\n\t,\n\t","Date":"Thu, 21 Sep 2017 17:53:36 +0800","In-Reply-To":"<1505869897.27600.6.camel@mtksdaap41>","References":"\n\t<0eb19ae1a4717d316cdaec44f6c20bfa8aa24ddc.1505801355.git.ryder.lee@mediatek.com>\n\t<1505869897.27600.6.camel@mtksdaap41>","Content-Type":"text/plain; charset=\"UTF-8\"","X-Mailer":"Evolution 3.2.3-0ubuntu6 ","Content-Transfer-Encoding":"7bit","MIME-Version":"1.0","X-MTK":"N","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]