[{"id":1770170,"web_url":"http://patchwork.ozlabs.org/comment/1770170/","msgid":"<20170918134610.17743-2-jbrunet@baylibre.com>","list_archive_url":null,"date":"2017-09-18T13:46:08","subject":"[PATCH v4 0/2] irqchip: meson: add support for the gpio interrupt\n\tcontroller","submitter":{"id":69839,"url":"http://patchwork.ozlabs.org/api/people/69839/","name":"Jerome Brunet","email":"jbrunet@baylibre.com"},"content":"This patch series adds support for the GPIO interrupt controller found on\nAmlogic's meson SoC families.\n\nUnlike what the name suggests, this controller is not part of the SoC\nGPIO subsystem. It is a separate controller which can watch almost all\ngpio pads of the SoC and generate and interrupt from it. \"Almost\" because\nthere are always exceptions and some specific gpios (TEST_N) lack this\ncapability.\n\nHardware wise, the controller is a 256 to 8 router with a filtering block\nto select edge or level input and the polarity of the signal. We can't\nsetup the filtring to generate a signal on both the high and low polarity\nso, ATM, IRQ_TYPE_EDGE_BOTH is not supported.\n\nThe number of interrupt line routed to the controller depends on the SoC,\nand essentially the total number of GPIO available on the different gpio\ncontrollers of the SoC.\n\nThis series has been tested on Amlogic S905-P200 board with the front\npanel power button. Also tested on the Nanopi-k2 with the ethernet PHY\ninterrupt pin.\n\nThis work is derived from the previous work of Carlo Caione [1].\n\nChanges since RFC : [2]\n* Remove interrupt property in device tree: the controller cannot\n generate interrupts on its own and is merely routing the interrupt to\n the GIC, therefore it should not use the interrupt property. This data\n is now stored directly in the driver, same as the pinctrl data.\n* Improve compatibility checking of meson pinctrl on its interrupt\n parent to activate gpio_to_irq callback\n* Drop IRQ_BOTH hack. Need more work to have an acceptable solution for\n this\n\nChanges since v1 : [3]\n* Correct mistake in patch 4 when no compatible\n controller is found. Sorry for the inconvenience.\n\nChanges since v2: [4]\n* Address Marc's comment on the irqchip driver from v2\n* Drop all gpio subsystem related patches. This will be dealt with\n separately.\n\nChanges since v3: [5]\n* Replace \"upstream\" irq with \"channel\" irq\n* Improve documentation a bit.\n* Drop DT patches: these will be sent later on to the DT maintainer\n if/when the driver is accepted.\n\n[1] : https://lkml.kernel.org/r/1448987062-31225-1-git-send-email-carlo@caione.org\n[2] : https://lkml.kernel.org/r/1475593708-10526-1-git-send-email-jbrunet@baylibre.com\n[3] : https://lkml.kernel.org/r/1476871709-8359-1-git-send-email-jbrunet@baylibre.com\n[4] : https://lkml.kernel.org/r/1476890480-8884-1-git-send-email-jbrunet@baylibre.com\n[5] : https://lkml.kernel.org/r/20170615161804.32658-1-jbrunet@baylibre.com\n\nJerome Brunet (2):\n dt-bindings: interrupt-controller: add DT binding for meson GPIO\n interrupt controller\n irqchip: meson: add support for gpio interrupt controller\n\n .../amlogic,meson-gpio-intc.txt | 35 ++\n drivers/irqchip/Kconfig | 8 +\n drivers/irqchip/Makefile | 1 +\n drivers/irqchip/irq-meson-gpio.c | 414 +++++++++++++++++++++\n 4 files changed, 458 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt\n create mode 100644 drivers/irqchip/irq-meson-gpio.c","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tMon, 18 Sep 2017 06:46:15 -0700 (PDT)","From":"Jerome Brunet ","To":"Marc Zyngier , Thomas Gleixner ,\n\tJason Cooper ,\n\tHeiner Kallweit ","Cc":"Jerome Brunet , Kevin Hilman ,\n\tCarlo Caione , linux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"[PATCH v4 0/2] irqchip: meson: add support for the gpio interrupt\n\tcontroller","Date":"Mon, 18 Sep 2017 15:46:08 +0200","Message-Id":"<20170918134610.17743-2-jbrunet@baylibre.com>","X-Mailer":"git-send-email 2.13.5","In-Reply-To":"<20170918134610.17743-1-jbrunet@baylibre.com>","References":"<20170918134610.17743-1-jbrunet@baylibre.com>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1789785,"web_url":"http://patchwork.ozlabs.org/comment/1789785/","msgid":"<87shegieqv.fsf@on-the-bus.cambridge.arm.com>","list_archive_url":null,"date":"2017-10-18T16:48:24","subject":"Re: [PATCH v4 0/2] irqchip: meson: add support for the gpio\n\tinterrupt controller","submitter":{"id":7353,"url":"http://patchwork.ozlabs.org/api/people/7353/","name":"Marc Zyngier","email":"marc.zyngier@arm.com"},"content":"On Mon, Sep 18 2017 at 3:46:07 pm BST, Jerome Brunet wrote:\n> This patch series adds support for the GPIO interrupt controller found on\n> Amlogic's meson SoC families.\n>\n> Unlike what the name suggests, this controller is not part of the SoC\n> GPIO subsystem. It is a separate controller which can watch almost all\n> gpio pads of the SoC and generate and interrupt from it. \"Almost\" because\n> there are always exceptions and some specific gpios (TEST_N) lack this\n> capability.\n>\n> Hardware wise, the controller is a 256 to 8 router with a filtering block\n> to select edge or level input and the polarity of the signal. We can't\n> setup the filtring to generate a signal on both the high and low polarity\n> so, ATM, IRQ_TYPE_EDGE_BOTH is not supported.\n>\n> The number of interrupt line routed to the controller depends on the SoC,\n> and essentially the total number of GPIO available on the different gpio\n> controllers of the SoC.\n>\n> This series has been tested on Amlogic S905-P200 board with the front\n> panel power button. Also tested on the Nanopi-k2 with the ethernet PHY\n> interrupt pin.\n>\n> This work is derived from the previous work of Carlo Caione [1].\n\nQueued for 4.15.\n\n\tM.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yHJ0Z09TPz9t3h\n\tfor ;\n\tThu, 19 Oct 2017 03:48:30 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751351AbdJRQs3 (ORCPT\n\t);\n\tWed, 18 Oct 2017 12:48:29 -0400","from foss.arm.com ([217.140.101.70]:43814 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750968AbdJRQs2 (ORCPT );\n\tWed, 18 Oct 2017 12:48:28 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 36688F;\n\tWed, 18 Oct 2017 09:48:28 -0700 (PDT)","from on-the-bus (unknown [10.3.33.38])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t691D33F25D; Wed, 18 Oct 2017 09:48:26 -0700 (PDT)"],"From":"Marc Zyngier ","To":"Jerome Brunet ","Cc":"Thomas Gleixner , Jason Cooper ,\n\tHeiner Kallweit ,\n\tKevin Hilman , Carlo Caione , \n\tlinux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org","Subject":"Re: [PATCH v4 0/2] irqchip: meson: add support for the gpio\n\tinterrupt controller","In-Reply-To":"<20170918134610.17743-1-jbrunet@baylibre.com> (Jerome Brunet's\n\tmessage of \"Mon, 18 Sep 2017 15:46:07 +0200\")","Organization":"ARM Ltd","References":"<20170918134610.17743-1-jbrunet@baylibre.com>","User-Agent":"Gnus/5.13 (Gnus v5.13) Emacs/25.1 (gnu/linux)","Date":"Wed, 18 Oct 2017 17:48:24 +0100","Message-ID":"<87shegieqv.fsf@on-the-bus.cambridge.arm.com>","MIME-Version":"1.0","Content-Type":"text/plain","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]