[{"id":1774148,"web_url":"http://patchwork.ozlabs.org/comment/1774148/","msgid":"<20170924130905.64e1bc39@archlinux>","list_archive_url":null,"date":"2017-09-24T12:09:05","subject":"Re: [PATCH 1/3] iio: trigger: stm32-timer: preset shouldn't be\n\tbuffered","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Mon, 18 Sep 2017 12:05:30 +0200\nFabrice Gasnier wrote:\n\n> Currently, setting preset value (ARR) will update directly 'Auto reload\n> value' only on 1st write access. But then, ARPE is set. This makes\n> ARR a shadow register. Preset value should be updated upon each\n> write request: ensure ARPE is 0. This fixes successive writes to\n> preset attribute.\n> \n> Fixes: 4adec7da0536 (\"iio: stm32 trigger: Add quadrature encoder device\")\n> \n> Signed-off-by: Fabrice Gasnier \n\nApplied to the fixes-togreg-post-rc1 branch of iio.git and marked\nfor stable.\n\nThanks,\n\nJonathan\n\n> ---\n> drivers/iio/trigger/stm32-timer-trigger.c | 3 ++-\n> 1 file changed, 2 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c\n> index 9b90534..34cc25b 100644\n> --- a/drivers/iio/trigger/stm32-timer-trigger.c\n> +++ b/drivers/iio/trigger/stm32-timer-trigger.c\n> @@ -715,8 +715,9 @@ static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,\n> \tif (ret)\n> \t\treturn ret;\n> \n> +\t/* TIMx_ARR register shouldn't be buffered (ARPE=0) */\n> +\tregmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);\n> \tregmap_write(priv->regmap, TIM_ARR, preset);\n> -\tregmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);\n> \n> \treturn len;\n> }","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"bl2h0gNC\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=jic23@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y0Qy26p3pz9sRW\n\tfor ;\n\tSun, 24 Sep 2017 22:09:44 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dw5j6-0001u2-4z; Sun, 24 Sep 2017 12:09:36 +0000","from mail.kernel.org ([198.145.29.99])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dw5j2-0001nt-5d for linux-arm-kernel@lists.infradead.org;\n\tSun, 24 Sep 2017 12:09:34 +0000","from archlinux (cpc91196-cmbg18-2-0-cust659.5-4.cable.virginm.net\n\t[81.96.234.148])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 76AC2218B3;\n\tSun, 24 Sep 2017 12:09:08 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=RCmugDEPEYb8+MSy6VUsiQ3MILYTpz9yi5QFXCxoZ9U=;\n\tb=bl2h0gNCLnMq6m\n\tGZBzVyD9wI4Cs8Fx5/jCWedgM6sfztR1wgfuFm2nRphk+9EqPlz343ImQwqregkMXssnJAk6j7qTe\n\trxPI3nPbd4BM+AT+n8Y4wvTdCUboFYo0XnYYJDud9Q8/jwqqic51liwcDH5EQlvurGvqn/eP1gIbL\n\tthS+fk5ttiBYKVadB5quGSs/csytyPWRyr6PvpIgRAElLzp6qiaL7unj0UHgYDBY+0ahdusP50bnK\n\tliAQo2B/d+pTa4+IaMqvqgpH1A9/wB75EHOcZL7BFPzj/fF+4o/jQCNXJVpOp1k/riaVjAPf0DW29\n\tM0iSWNV+lytNUxWcUCew==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 76AC2218B3","Date":"Sun, 24 Sep 2017 13:09:05 +0100","From":"Jonathan Cameron ","To":"Fabrice Gasnier ","Subject":"Re: [PATCH 1/3] iio: trigger: stm32-timer: preset shouldn't be\n\tbuffered","Message-ID":"<20170924130905.64e1bc39@archlinux>","In-Reply-To":"<1505729132-1369-2-git-send-email-fabrice.gasnier@st.com>","References":"<1505729132-1369-1-git-send-email-fabrice.gasnier@st.com>\n\t<1505729132-1369-2-git-send-email-fabrice.gasnier@st.com>","X-Mailer":"Claws Mail 3.15.1-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170924_050932_301971_BDD27AEE ","X-CRM114-Status":"GOOD ( 11.82 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [198.145.29.99 listed in list.dnswl.org]\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"benjamin.gaignard@linaro.org, lars@metafoo.de, benjamin.gaignard@st.com, \n\tlinux-iio@vger.kernel.org, pmeerw@pmeerw.net,\n\tlinux-kernel@vger.kernel.org, \n\tmcoquelin.stm32@gmail.com, knaack.h@gmx.de,\n\tlinux-arm-kernel@lists.infradead.org, alexandre.torgue@st.com","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1774149,"web_url":"http://patchwork.ozlabs.org/comment/1774149/","msgid":"<20170924131027.2d6c5d90@archlinux>","list_archive_url":null,"date":"2017-09-24T12:10:27","subject":"Re: [PATCH 2/3] iio: trigger: stm32-timer: fix a corner case to\n\twrite preset","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Mon, 18 Sep 2017 12:05:31 +0200\nFabrice Gasnier wrote:\n\n> Balance timer start routine that sets ARPE: clear it in stop routine.\n> This fixes a corner case, when timer is used successively as trigger\n> (with sampling_frequency start/stop routines), then as a counter\n> (with preset).\n> \n> Fixes: 93fbe91b5521 (\"iio: Add STM32 timer trigger driver\")\n> \n> Signed-off-by: Fabrice Gasnier \n\nApplied to the fixes-togreg-post-rc1 branch of iio.git and\nmarked for stable.\n\nThanks,\n\nJonathan\n> ---\n> drivers/iio/trigger/stm32-timer-trigger.c | 1 +\n> 1 file changed, 1 insertion(+)\n> \n> diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c\n> index 34cc25b..eb212f8c 100644\n> --- a/drivers/iio/trigger/stm32-timer-trigger.c\n> +++ b/drivers/iio/trigger/stm32-timer-trigger.c\n> @@ -174,6 +174,7 @@ static void stm32_timer_stop(struct stm32_timer_trigger *priv)\n> \t\tclk_disable(priv->clk);\n> \n> \t/* Stop timer */\n> +\tregmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);\n> \tregmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);\n> \tregmap_write(priv->regmap, TIM_PSC, 0);\n> \tregmap_write(priv->regmap, TIM_ARR, 0);","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"RxpnlTyl\"; dkim-atps=neutral","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=jic23@kernel.org"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y0QzS0XQZz9sRW\n\tfor ;\n\tSun, 24 Sep 2017 22:11:00 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dw5kO-0003f9-Fl; Sun, 24 Sep 2017 12:10:56 +0000","from mail.kernel.org ([198.145.29.99])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dw5kJ-0003Zw-QX for linux-arm-kernel@lists.infradead.org;\n\tSun, 24 Sep 2017 12:10:53 +0000","from archlinux (cpc91196-cmbg18-2-0-cust659.5-4.cable.virginm.net\n\t[81.96.234.148])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 94E57218B3;\n\tSun, 24 Sep 2017 12:10:29 +0000 (UTC)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=RTGFL9N/niflKnMQG5zjSga7BMM7JqVzgqrBOacG7aM=;\n\tb=RxpnlTylbfHU2A\n\tLjRc2JvUNGS3y3kyBT7N+vff5HxkthjEU256CJQx0K/f5eQvZzwKmJ501HHnzuFwtlu8FYbE99+FD\n\tT06dqV647OioJUDKuqcLjKoIknE6++bJ1F78zsXH4E2lTrP95MzRzB0zKyhg+gYT7UYHLrQyiik+Y\n\tUSisFYEbBqfJT/xVzUWWv7W3hm2F7D3lJkrwgKFykhdkNao7lCUh3NdEZNqfWiielBgWPylWHCFk4\n\t5KV8dSE9/k8YvpDb90Ne33nl5qboM9IuLwA2fjYeZjkKbF1wcKxrA73XJoKDUVMYz6qSDqPy2nZpT\n\tjyQX7jJPstdO90u5TrnA==;","DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 94E57218B3","Date":"Sun, 24 Sep 2017 13:10:27 +0100","From":"Jonathan Cameron ","To":"Fabrice Gasnier ","Subject":"Re: [PATCH 2/3] iio: trigger: stm32-timer: fix a corner case to\n\twrite preset","Message-ID":"<20170924131027.2d6c5d90@archlinux>","In-Reply-To":"<1505729132-1369-3-git-send-email-fabrice.gasnier@st.com>","References":"<1505729132-1369-1-git-send-email-fabrice.gasnier@st.com>\n\t<1505729132-1369-3-git-send-email-fabrice.gasnier@st.com>","X-Mailer":"Claws Mail 3.15.1-dirty (GTK+ 2.24.31; x86_64-pc-linux-gnu)","MIME-Version":"1.0","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170924_051052_040398_FFE846CD ","X-CRM114-Status":"GOOD ( 11.13 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [198.145.29.99 listed in list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"benjamin.gaignard@linaro.org, lars@metafoo.de, benjamin.gaignard@st.com, \n\tlinux-iio@vger.kernel.org, pmeerw@pmeerw.net,\n\tlinux-kernel@vger.kernel.org, \n\tmcoquelin.stm32@gmail.com, knaack.h@gmx.de,\n\tlinux-arm-kernel@lists.infradead.org, alexandre.torgue@st.com","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1774156,"web_url":"http://patchwork.ozlabs.org/comment/1774156/","msgid":"<20170924132252.211d67d0@archlinux>","list_archive_url":null,"date":"2017-09-24T12:22:52","subject":"Re: [PATCH 3/3] iio: trigger: stm32-timer: enable clock when in\n\tmaster mode","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Mon, 18 Sep 2017 12:05:32 +0200\nFabrice Gasnier wrote:\n\n> Clock should be enabled as soon as using master mode, even before\n> enabling timer. Or, this may provoke bad behavior on the other end\n> (slave timer). Then, introduce 'clk_enabled' flag, instead of relying\n> on CR1 EN bit, to keep track of clock being enabled.\n> Propagate this anywhere else in the driver.\n> \n> Also add 'remove' routine to stop timer and disable clock in case it\n> has been left enabled.\n\nThis last bit leaves us open to some nasty race conditions I think.\nI'm not sure of a clean way to avoid them, but turning this off\nbefore we remove the userspace interfaces doesn't strike me as a good\nidea!\n\nMore detail inline.\n\nJonathan\n\n> \n> Signed-off-by: Fabrice Gasnier \n> ---\n> drivers/iio/trigger/stm32-timer-trigger.c | 60 +++++++++++++++++++++----------\n> 1 file changed, 42 insertions(+), 18 deletions(-)\n> \n> diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c\n> index eb212f8c..5a6509c 100644\n> --- a/drivers/iio/trigger/stm32-timer-trigger.c\n> +++ b/drivers/iio/trigger/stm32-timer-trigger.c\n> @@ -79,6 +79,7 @@ struct stm32_timer_trigger {\n> \tstruct device *dev;\n> \tstruct regmap *regmap;\n> \tstruct clk *clk;\n> +\tbool clk_enabled;\n> \tu32 max_arr;\n> \tconst void *triggers;\n> \tconst void *valids;\n> @@ -106,7 +107,7 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv,\n> {\n> \tunsigned long long prd, div;\n> \tint prescaler = 0;\n> -\tu32 ccer, cr1;\n> +\tu32 ccer;\n> \n> \t/* Period and prescaler values depends of clock rate */\n> \tdiv = (unsigned long long)clk_get_rate(priv->clk);\n> @@ -136,9 +137,10 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv,\n> \tif (ccer & TIM_CCER_CCXE)\n> \t\treturn -EBUSY;\n> \n> -\tregmap_read(priv->regmap, TIM_CR1, &cr1);\n> -\tif (!(cr1 & TIM_CR1_CEN))\n> +\tif (!priv->clk_enabled) {\n> +\t\tpriv->clk_enabled = true;\n> \t\tclk_enable(priv->clk);\n> +\t}\n> \n> \tregmap_write(priv->regmap, TIM_PSC, prescaler);\n> \tregmap_write(priv->regmap, TIM_ARR, prd - 1);\n> @@ -163,16 +165,12 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv,\n> \n> static void stm32_timer_stop(struct stm32_timer_trigger *priv)\n> {\n> -\tu32 ccer, cr1;\n> +\tu32 ccer;\n> \n> \tregmap_read(priv->regmap, TIM_CCER, &ccer);\n> \tif (ccer & TIM_CCER_CCXE)\n> \t\treturn;\n> \n> -\tregmap_read(priv->regmap, TIM_CR1, &cr1);\n> -\tif (cr1 & TIM_CR1_CEN)\n> -\t\tclk_disable(priv->clk);\n> -\n> \t/* Stop timer */\n> \tregmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);\n> \tregmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);\n> @@ -181,6 +179,11 @@ static void stm32_timer_stop(struct stm32_timer_trigger *priv)\n> \n> \t/* Make sure that registers are updated */\n> \tregmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);\n> +\n> +\tif (priv->clk_enabled) {\n> +\t\tpriv->clk_enabled = false;\n> +\t\tclk_disable(priv->clk);\n> +\t}\n> }\n> \n> static ssize_t stm32_tt_store_frequency(struct device *dev,\n> @@ -295,6 +298,11 @@ static ssize_t stm32_tt_store_master_mode(struct device *dev,\n> \tfor (i = 0; i <= master_mode_max; i++) {\n> \t\tif (!strncmp(master_mode_table[i], buf,\n> \t\t\t strlen(master_mode_table[i]))) {\n> +\t\t\tif (!priv->clk_enabled) {\n> +\t\t\t\t/* Clock should be enabled first */\n> +\t\t\t\tpriv->clk_enabled = true;\n> +\t\t\t\tclk_enable(priv->clk);\n> +\t\t\t}\n> \t\t\tregmap_update_bits(priv->regmap, TIM_CR2, mask,\n> \t\t\t\t\t i << shift);\n> \t\t\t/* Make sure that registers are updated */\n> @@ -438,7 +446,6 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev,\n> \t\t\t\t int val, int val2, long mask)\n> {\n> \tstruct stm32_timer_trigger *priv = iio_priv(indio_dev);\n> -\tu32 dat;\n> \n> \tswitch (mask) {\n> \tcase IIO_CHAN_INFO_RAW:\n> @@ -450,17 +457,19 @@ static int stm32_counter_write_raw(struct iio_dev *indio_dev,\n> \n> \tcase IIO_CHAN_INFO_ENABLE:\n> \t\tif (val) {\n> -\t\t\tregmap_read(priv->regmap, TIM_CR1, &dat);\n> -\t\t\tif (!(dat & TIM_CR1_CEN))\n> +\t\t\tif (!priv->clk_enabled) {\n> +\t\t\t\tpriv->clk_enabled = true;\n> \t\t\t\tclk_enable(priv->clk);\n> +\t\t\t}\n> \t\t\tregmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,\n> \t\t\t\t\t TIM_CR1_CEN);\n> \t\t} else {\n> -\t\t\tregmap_read(priv->regmap, TIM_CR1, &dat);\n> \t\t\tregmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,\n> \t\t\t\t\t 0);\n> -\t\t\tif (dat & TIM_CR1_CEN)\n> +\t\t\tif (priv->clk_enabled) {\n> +\t\t\t\tpriv->clk_enabled = false;\n> \t\t\t\tclk_disable(priv->clk);\n> +\t\t\t}\n> \t\t}\n> \t\treturn 0;\n> \t}\n> @@ -558,7 +567,6 @@ static int stm32_set_enable_mode(struct iio_dev *indio_dev,\n> {\n> \tstruct stm32_timer_trigger *priv = iio_priv(indio_dev);\n> \tint sms = stm32_enable_mode2sms(mode);\n> -\tu32 val;\n> \n> \tif (sms < 0)\n> \t\treturn sms;\n> @@ -566,10 +574,9 @@ static int stm32_set_enable_mode(struct iio_dev *indio_dev,\n> \t * Triggered mode sets CEN bit automatically by hardware. So, first\n> \t * enable counter clock, so it can use it. Keeps it in sync with CEN.\n> \t */\n> -\tif (sms == 6) {\n> -\t\tregmap_read(priv->regmap, TIM_CR1, &val);\n> -\t\tif (!(val & TIM_CR1_CEN))\n> -\t\t\tclk_enable(priv->clk);\n> +\tif (sms == 6 && !priv->clk_enabled) {\n> +\t\tclk_enable(priv->clk);\n> +\t\tpriv->clk_enabled = true;\n> \t}\n> \n> \tregmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);\n> @@ -848,6 +855,22 @@ static int stm32_timer_trigger_probe(struct platform_device *pdev)\n> \treturn 0;\n> }\n> \n> +static int stm32_timer_trigger_remove(struct platform_device *pdev)\n> +{\n> +\tstruct stm32_timer_trigger *priv = platform_get_drvdata(pdev);\n> +\tu32 val;\n> +\n> +\t/* Check if nobody else use the timer, then disable it */\n> +\tregmap_read(priv->regmap, TIM_CCER, &val);\n> +\tif (!(val & TIM_CCER_CCXE))\n> +\t\tregmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);\n> +\n> +\tif (priv->clk_enabled)\n> +\t\tclk_disable(priv->clk);\n> +\n> +\treturn 0;\n> +}\n\nThis looks racy to me. Given we did everything previously with devm\ncalls, which will run after this time, we are turning the timer off\nbefore the userspace interfaces are removed. If you need to do\nthis you probably also need to unwind the use of devm for anything\nthat needs this clock.\n\nIt's not immediately obvious how to clean up these timers cleanly\nthough as they seem to only be enabled on userspace configuration.\n\nAny attempt to prevent removal of the driver until a manual unwind\nis done by userspace would be risk prone, but that might be one\napproach. It's not as though anyone can force a removal of\none of these by pulling the cable out or anything.\n\n> +\n> static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {\n> \t.valids_table = valids_table,\n> \t.num_valids_table = ARRAY_SIZE(valids_table),\n> @@ -872,6 +895,7 @@ static int stm32_timer_trigger_probe(struct platform_device *pdev)\n> \n> static struct platform_driver stm32_timer_trigger_driver = {\n> \t.probe = stm32_timer_trigger_probe,\n> +\t.remove = stm32_timer_trigger_remove,\n> \t.driver = {\n> \t\t.name = \"stm32-timer-trigger\",\n> \t\t.of_match_table = stm32_trig_of_match,","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; 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