[{"id":1770070,"web_url":"http://patchwork.ozlabs.org/comment/1770070/","msgid":"<87y3pcmgv6.fsf@linux.intel.com>","list_archive_url":null,"date":"2017-09-18T10:38:21","subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","submitter":{"id":68254,"url":"http://patchwork.ozlabs.org/api/people/68254/","name":"Felipe Balbi","email":"balbi@kernel.org"},"content":"Hi,\n\nAndrzej Pietrasiewicz writes:\n> From: Vivek Gautam \n>\n> Adding phy calibration sequence for USB 3.0 DRD PHY present on\n> Exynos5420/5800 systems.\n> This calibration facilitates setting certain PHY parameters viz.\n> the Loss-of-Signal (LOS) Detector Threshold Level, as well as\n> Tx-Vboost-Level for Super-Speed operations.\n> Additionally we also set proper time to wait for RxDetect measurement,\n> for desired PHY reference clock, so as to solve issue with enumeration\n> of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive\n> on the controller.\n>\n> We are using CR_port for this purpose to send required data\n> to override the LOS values.\n>\n> On testing with USB 3.0 devices on USB 3.0 port present on\n> SMDK5420, and peach-pit boards should see following message:\n> usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd\n>\n> and without this patch, should see below shown message:\n> usb 1-1: new high-speed USB device number 2 using xhci-hcd\n>\n> [Also removed unnecessary extra lines in the register macro definitions]\n>\n> Signed-off-by: Vivek Gautam \n> [adapted to use phy_reset as entry point]\n> Signed-off-by: Andrzej Pietrasiewicz \n> ---\n> drivers/phy/samsung/phy-exynos5-usbdrd.c | 183 +++++++++++++++++++++++++++++++\n> drivers/usb/dwc3/core.c | 8 +-\n> 2 files changed, 189 insertions(+), 2 deletions(-)\n>\n> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c\n> index 7c41daa..f7de067 100644\n> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c\n> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c\n> @@ -89,7 +89,17 @@\n> #define PHYCLKRST_COMMONONN\t\t\tBIT(0)\n> \n> #define EXYNOS5_DRD_PHYREG0\t\t\t0x14\n> +#define PHYREG0_SSC_REF_CLK_SEL\t\t\tBIT(21)\n> +#define PHYREG0_SSC_RANGE\t\t\tBIT(20)\n> +#define PHYREG0_CR_WRITE\t\t\tBIT(19)\n> +#define PHYREG0_CR_READ\t\t\t\tBIT(18)\n> +#define PHYREG0_CR_DATA_IN(_x)\t\t\t((_x) << 2)\n> +#define PHYREG0_CR_CAP_DATA\t\t\tBIT(1)\n> +#define PHYREG0_CR_CAP_ADDR\t\t\tBIT(0)\n> +\n> #define EXYNOS5_DRD_PHYREG1\t\t\t0x18\n> +#define PHYREG1_CR_DATA_OUT(_x)\t\t\t((_x) << 1)\n> +#define PHYREG1_CR_ACK\t\t\t\tBIT(0)\n> \n> #define EXYNOS5_DRD_PHYPARAM0\t\t\t0x1c\n> \n> @@ -118,6 +128,25 @@\n> #define EXYNOS5_DRD_PHYRESUME\t\t\t0x34\n> #define EXYNOS5_DRD_LINKPORT\t\t\t0x44\n> \n> +/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */\n> +#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN\t\t(0x15)\n> +#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420\t\t\t(0x5 << 13)\n> +#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT\t\t(0x0 << 13)\n> +#define LOSLEVEL_OVRD_IN_EN\t\t\t\t(0x1 << 10)\n> +#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT\t\t(0x9 << 0)\n> +\n> +#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN\t(0x12)\n> +#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420\t\t(0x5 << 13)\n> +#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT\t\t(0x4 << 13)\n> +\n> +#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG\t\t(0x1010)\n> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M\t\t(0x4 << 4)\n> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M\t\t(0x8 << 4)\n> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M\t\t(0x8 << 4)\n> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M\t(0x20 << 4)\n> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5\t\t(0x20 << 4)\n> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M\t\t(0x40 << 4)\n> +\n> #define KHZ\t1000\n> #define MHZ\t(KHZ * KHZ)\n> \n> @@ -526,6 +555,151 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)\n> \treturn 0;\n> }\n> \n> +static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd,\n> +\t\t\t\t\t\tu32 val, u32 cmd)\n> +{\n> +\tu32 usec = 100;\n> +\tunsigned int result;\n> +\n> +\twritel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);\n> +\n> +\tdo {\n> +\t\tresult = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);\n> +\t\tif (result & PHYREG1_CR_ACK)\n> +\t\t\tbreak;\n> +\n> +\t\tudelay(1);\n> +\t} while (usec-- > 0);\n> +\n> +\tif (!usec) {\n> +\t\tdev_err(phy_drd->dev,\n> +\t\t\t\"CRPORT handshake timeout1 (0x%08x)\\n\", val);\n> +\t\treturn -ETIME;\n> +\t}\n> +\n> +\tusec = 100;\n> +\n> +\twritel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);\n> +\n> +\tdo {\n> +\t\tresult = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);\n> +\t\tif (!(result & PHYREG1_CR_ACK))\n> +\t\t\tbreak;\n> +\n> +\t\tudelay(1);\n> +\t} while (usec-- > 0);\n> +\n> +\tif (!usec) {\n> +\t\tdev_err(phy_drd->dev,\n> +\t\t\t\"CRPORT handshake timeout2 (0x%08x)\\n\", val);\n> +\t\treturn -ETIME;\n> +\t}\n> +\n> +\treturn 0;\n> +}\n> +\n> +static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd,\n> +\t\t\t\t\t\tu32 addr, u32 data)\n> +{\n> +\tint ret;\n> +\n> +\t/* Write Address */\n> +\twritel(PHYREG0_CR_DATA_IN(addr),\n> +\t\tphy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);\n> +\tret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr),\n> +\t\t\t\tPHYREG0_CR_CAP_ADDR);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\t/* Write Data */\n> +\twritel(PHYREG0_CR_DATA_IN(data),\n> +\t\tphy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);\n> +\tret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),\n> +\t\t\t\tPHYREG0_CR_CAP_DATA);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),\n> +\t\t\t\tPHYREG0_CR_WRITE);\n> +\n> +\treturn ret;\n> +}\n> +\n> +/*\n> + * Calibrate few PHY parameters using CR_PORT register to meet\n> + * SuperSpeed requirements on Exynos5420 and Exynos5800 systems,\n> + * which have 28nm USB 3.0 DRD PHY.\n> + */\n> +static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd)\n> +{\n> +\tunsigned int temp;\n> +\tint ret = 0;\n> +\n> +\t/*\n> +\t * Change los_bias to (0x5) for 28nm PHY from a\n> +\t * default value (0x0); los_level is set as default\n> +\t * (0x9) as also reflected in los_level[30:26] bits\n> +\t * of PHYPARAM0 register.\n> +\t */\n> +\ttemp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 |\n> +\t\tLOSLEVEL_OVRD_IN_EN |\n> +\t\tLOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT;\n> +\tret = crport_ctrl_write(phy_drd,\n> +\t\t\t\tEXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN,\n> +\t\t\t\ttemp);\n> +\tif (ret) {\n> +\t\tdev_err(phy_drd->dev,\n> +\t\t \"Failed setting Loss-of-Signal level for SuperSpeed\\n\");\n> +\t\treturn ret;\n> +\t}\n> +\n> +\t/*\n> +\t * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning,\n> +\t * to raise Tx signal level from its default value of (0x4)\n> +\t */\n> +\ttemp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420;\n> +\tret = crport_ctrl_write(phy_drd,\n> +\t\t\t\tEXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN,\n> +\t\t\t\ttemp);\n> +\tif (ret) {\n> +\t\tdev_err(phy_drd->dev,\n> +\t\t \"Failed setting Tx-Vboost-Level for SuperSpeed\\n\");\n> +\t\treturn ret;\n> +\t}\n> +\n> +\t/*\n> +\t * Set proper time to wait for RxDetect measurement, for\n> +\t * desired reference clock of PHY, by tuning the CR_PORT\n> +\t * register LANE0.TX_DEBUG which is internal to PHY.\n> +\t * This fixes issue with few USB 3.0 devices, which are\n> +\t * not detected (not even generate interrupts on the bus\n> +\t * on insertion) without this change.\n> +\t * e.g. Samsung SUM-TSB16S 3.0 USB drive.\n> +\t */\n> +\tswitch (phy_drd->extrefclk) {\n> +\tcase EXYNOS5_FSEL_50MHZ:\n> +\t\ttemp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M;\n> +\t\tbreak;\n> +\tcase EXYNOS5_FSEL_20MHZ:\n> +\tcase EXYNOS5_FSEL_19MHZ2:\n> +\t\ttemp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M;\n> +\t\tbreak;\n> +\tcase EXYNOS5_FSEL_24MHZ:\n> +\tdefault:\n> +\t\ttemp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M;\n> +\t\tbreak;\n> +\t}\n> +\n> +\tret = crport_ctrl_write(phy_drd,\n> +\t\t\t\tEXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG,\n> +\t\t\t\ttemp);\n> +\tif (ret)\n> +\t\tdev_err(phy_drd->dev,\n> +\t\t \"Failed setting RxDetect measurement time for SuperSpeed\\n\");\n> +\n> +\treturn ret;\n> +}\n> +\n> static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,\n> \t\t\t\t\tstruct of_phandle_args *args)\n> {\n> @@ -537,11 +711,20 @@ static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,\n> \treturn phy_drd->phys[args->args[0]].phy;\n> }\n> \n> +static int exynos5_usbdrd_phy_reset(struct phy *phy)\n> +{\n> +\tstruct phy_usb_instance *inst = phy_get_drvdata(phy);\n> +\tstruct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);\n> +\n> +\treturn exynos5420_usbdrd_phy_calibrate(phy_drd);\n> +}\n> +\n> static const struct phy_ops exynos5_usbdrd_phy_ops = {\n> \t.init\t\t= exynos5_usbdrd_phy_init,\n> \t.exit\t\t= exynos5_usbdrd_phy_exit,\n> \t.power_on\t= exynos5_usbdrd_phy_power_on,\n> \t.power_off\t= exynos5_usbdrd_phy_power_off,\n> +\t.reset\t\t= exynos5_usbdrd_phy_reset,\n> \t.owner\t\t= THIS_MODULE,\n> };\n> \n> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c\n> index 03474d3..1d5836e 100644\n> --- a/drivers/usb/dwc3/core.c\n> +++ b/drivers/usb/dwc3/core.c\n> @@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work)\n> \t\t} else {\n> \t\t\tif (dwc->usb2_phy)\n> \t\t\t\totg_set_vbus(dwc->usb2_phy->otg, true);\n> -\t\t\tif (dwc->usb2_generic_phy)\n> +\t\t\tif (dwc->usb2_generic_phy) {\n> \t\t\t\tphy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);\n> -\n> +\t\t\t\tphy_reset(dwc->usb2_generic_phy);\n\nit doesn't look like this is the best place to reset the phy. Also,\n->reset() doesn't seem to match correctly with a calibration. That seems\nto be more fitting to a ->power_on() or ->init() implementation.\n\nKishon, any comments?","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwjCg0PCSz9s7M\n\tfor ;\n\tMon, 18 Sep 2017 20:38:39 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751715AbdIRKih (ORCPT\n\t);\n\tMon, 18 Sep 2017 06:38:37 -0400","from mga03.intel.com ([134.134.136.65]:35368 \"EHLO mga03.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1751365AbdIRKih (ORCPT );\n\tMon, 18 Sep 2017 06:38:37 -0400","from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t18 Sep 2017 03:38:35 -0700","from pipin.fi.intel.com (HELO localhost) ([10.237.68.37])\n\tby fmsmga002.fm.intel.com with ESMTP; 18 Sep 2017 03:38:31 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,412,1500966000\"; \n\td=\"asc'?scan'208\";a=\"1220246265\"","From":"Felipe Balbi ","To":"Andrzej Pietrasiewicz ,\n\tlinux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org","Cc":"Andrzej Pietrasiewicz ,\n\tMarek Szyprowski ,\n\tBartlomiej Zolnierkiewicz ,\n\tKrzysztof Kozlowski , Kukjin Kim , \n\tRussell King ,\n\tMark Rutland , Rob Herring ,\n\tKishon Vijay Abraham I , \n\tGreg Kroah-Hartman ","Subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","In-Reply-To":"<1505729371-6509-1-git-send-email-andrzej.p@samsung.com>","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505729371-6509-1-git-send-email-andrzej.p@samsung.com>","Date":"Mon, 18 Sep 2017 13:38:21 +0300","Message-ID":"<87y3pcmgv6.fsf@linux.intel.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; boundary=\"=-=-=\";\n\tmicalg=pgp-sha512; protocol=\"application/pgp-signature\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1770082,"web_url":"http://patchwork.ozlabs.org/comment/1770082/","msgid":"","list_archive_url":null,"date":"2017-09-18T11:06:33","subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","submitter":{"id":14965,"url":"http://patchwork.ozlabs.org/api/people/14965/","name":"Kishon Vijay Abraham I","email":"kishon@ti.com"},"content":"Hi,\n\nOn Monday 18 September 2017 04:08 PM, Felipe Balbi wrote:\n> \n> Hi,\n> \n> Andrzej Pietrasiewicz writes:\n>> From: Vivek Gautam \n>>\n>> Adding phy calibration sequence for USB 3.0 DRD PHY present on\n>> Exynos5420/5800 systems.\n>> This calibration facilitates setting certain PHY parameters viz.\n>> the Loss-of-Signal (LOS) Detector Threshold Level, as well as\n>> Tx-Vboost-Level for Super-Speed operations.\n>> Additionally we also set proper time to wait for RxDetect measurement,\n>> for desired PHY reference clock, so as to solve issue with enumeration\n>> of few USB 3.0 devices, like Samsung SUM-TSB16S 3.0 USB drive\n>> on the controller.\n>>\n>> We are using CR_port for this purpose to send required data\n>> to override the LOS values.\n>>\n>> On testing with USB 3.0 devices on USB 3.0 port present on\n>> SMDK5420, and peach-pit boards should see following message:\n>> usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd\n>>\n>> and without this patch, should see below shown message:\n>> usb 1-1: new high-speed USB device number 2 using xhci-hcd\n>>\n>> [Also removed unnecessary extra lines in the register macro definitions]\n>>\n>> Signed-off-by: Vivek Gautam \n>> [adapted to use phy_reset as entry point]\n>> Signed-off-by: Andrzej Pietrasiewicz \n>> ---\n>> drivers/phy/samsung/phy-exynos5-usbdrd.c | 183 +++++++++++++++++++++++++++++++\n>> drivers/usb/dwc3/core.c | 8 +-\n>> 2 files changed, 189 insertions(+), 2 deletions(-)\n>>\n>> diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c\n>> index 7c41daa..f7de067 100644\n>> --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c\n>> +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c\n>> @@ -89,7 +89,17 @@\n>> #define PHYCLKRST_COMMONONN\t\t\tBIT(0)\n>> \n>> #define EXYNOS5_DRD_PHYREG0\t\t\t0x14\n>> +#define PHYREG0_SSC_REF_CLK_SEL\t\t\tBIT(21)\n>> +#define PHYREG0_SSC_RANGE\t\t\tBIT(20)\n>> +#define PHYREG0_CR_WRITE\t\t\tBIT(19)\n>> +#define PHYREG0_CR_READ\t\t\t\tBIT(18)\n>> +#define PHYREG0_CR_DATA_IN(_x)\t\t\t((_x) << 2)\n>> +#define PHYREG0_CR_CAP_DATA\t\t\tBIT(1)\n>> +#define PHYREG0_CR_CAP_ADDR\t\t\tBIT(0)\n>> +\n>> #define EXYNOS5_DRD_PHYREG1\t\t\t0x18\n>> +#define PHYREG1_CR_DATA_OUT(_x)\t\t\t((_x) << 1)\n>> +#define PHYREG1_CR_ACK\t\t\t\tBIT(0)\n>> \n>> #define EXYNOS5_DRD_PHYPARAM0\t\t\t0x1c\n>> \n>> @@ -118,6 +128,25 @@\n>> #define EXYNOS5_DRD_PHYRESUME\t\t\t0x34\n>> #define EXYNOS5_DRD_LINKPORT\t\t\t0x44\n>> \n>> +/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */\n>> +#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN\t\t(0x15)\n>> +#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420\t\t\t(0x5 << 13)\n>> +#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT\t\t(0x0 << 13)\n>> +#define LOSLEVEL_OVRD_IN_EN\t\t\t\t(0x1 << 10)\n>> +#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT\t\t(0x9 << 0)\n>> +\n>> +#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN\t(0x12)\n>> +#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420\t\t(0x5 << 13)\n>> +#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT\t\t(0x4 << 13)\n>> +\n>> +#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG\t\t(0x1010)\n>> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M\t\t(0x4 << 4)\n>> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M\t\t(0x8 << 4)\n>> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M\t\t(0x8 << 4)\n>> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M\t(0x20 << 4)\n>> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5\t\t(0x20 << 4)\n>> +#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M\t\t(0x40 << 4)\n>> +\n>> #define KHZ\t1000\n>> #define MHZ\t(KHZ * KHZ)\n>> \n>> @@ -526,6 +555,151 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)\n>> \treturn 0;\n>> }\n>> \n>> +static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd,\n>> +\t\t\t\t\t\tu32 val, u32 cmd)\n>> +{\n>> +\tu32 usec = 100;\n>> +\tunsigned int result;\n>> +\n>> +\twritel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);\n>> +\n>> +\tdo {\n>> +\t\tresult = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);\n>> +\t\tif (result & PHYREG1_CR_ACK)\n>> +\t\t\tbreak;\n>> +\n>> +\t\tudelay(1);\n>> +\t} while (usec-- > 0);\n>> +\n>> +\tif (!usec) {\n>> +\t\tdev_err(phy_drd->dev,\n>> +\t\t\t\"CRPORT handshake timeout1 (0x%08x)\\n\", val);\n>> +\t\treturn -ETIME;\n>> +\t}\n>> +\n>> +\tusec = 100;\n>> +\n>> +\twritel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);\n>> +\n>> +\tdo {\n>> +\t\tresult = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1);\n>> +\t\tif (!(result & PHYREG1_CR_ACK))\n>> +\t\t\tbreak;\n>> +\n>> +\t\tudelay(1);\n>> +\t} while (usec-- > 0);\n>> +\n>> +\tif (!usec) {\n>> +\t\tdev_err(phy_drd->dev,\n>> +\t\t\t\"CRPORT handshake timeout2 (0x%08x)\\n\", val);\n>> +\t\treturn -ETIME;\n>> +\t}\n>> +\n>> +\treturn 0;\n>> +}\n>> +\n>> +static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd,\n>> +\t\t\t\t\t\tu32 addr, u32 data)\n>> +{\n>> +\tint ret;\n>> +\n>> +\t/* Write Address */\n>> +\twritel(PHYREG0_CR_DATA_IN(addr),\n>> +\t\tphy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);\n>> +\tret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr),\n>> +\t\t\t\tPHYREG0_CR_CAP_ADDR);\n>> +\tif (ret)\n>> +\t\treturn ret;\n>> +\n>> +\t/* Write Data */\n>> +\twritel(PHYREG0_CR_DATA_IN(data),\n>> +\t\tphy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);\n>> +\tret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),\n>> +\t\t\t\tPHYREG0_CR_CAP_DATA);\n>> +\tif (ret)\n>> +\t\treturn ret;\n>> +\n>> +\tret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),\n>> +\t\t\t\tPHYREG0_CR_WRITE);\n>> +\n>> +\treturn ret;\n>> +}\n>> +\n>> +/*\n>> + * Calibrate few PHY parameters using CR_PORT register to meet\n>> + * SuperSpeed requirements on Exynos5420 and Exynos5800 systems,\n>> + * which have 28nm USB 3.0 DRD PHY.\n>> + */\n>> +static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd)\n>> +{\n>> +\tunsigned int temp;\n>> +\tint ret = 0;\n>> +\n>> +\t/*\n>> +\t * Change los_bias to (0x5) for 28nm PHY from a\n>> +\t * default value (0x0); los_level is set as default\n>> +\t * (0x9) as also reflected in los_level[30:26] bits\n>> +\t * of PHYPARAM0 register.\n>> +\t */\n>> +\ttemp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 |\n>> +\t\tLOSLEVEL_OVRD_IN_EN |\n>> +\t\tLOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT;\n>> +\tret = crport_ctrl_write(phy_drd,\n>> +\t\t\t\tEXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN,\n>> +\t\t\t\ttemp);\n>> +\tif (ret) {\n>> +\t\tdev_err(phy_drd->dev,\n>> +\t\t \"Failed setting Loss-of-Signal level for SuperSpeed\\n\");\n>> +\t\treturn ret;\n>> +\t}\n>> +\n>> +\t/*\n>> +\t * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning,\n>> +\t * to raise Tx signal level from its default value of (0x4)\n>> +\t */\n>> +\ttemp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420;\n>> +\tret = crport_ctrl_write(phy_drd,\n>> +\t\t\t\tEXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN,\n>> +\t\t\t\ttemp);\n>> +\tif (ret) {\n>> +\t\tdev_err(phy_drd->dev,\n>> +\t\t \"Failed setting Tx-Vboost-Level for SuperSpeed\\n\");\n>> +\t\treturn ret;\n>> +\t}\n>> +\n>> +\t/*\n>> +\t * Set proper time to wait for RxDetect measurement, for\n>> +\t * desired reference clock of PHY, by tuning the CR_PORT\n>> +\t * register LANE0.TX_DEBUG which is internal to PHY.\n>> +\t * This fixes issue with few USB 3.0 devices, which are\n>> +\t * not detected (not even generate interrupts on the bus\n>> +\t * on insertion) without this change.\n>> +\t * e.g. Samsung SUM-TSB16S 3.0 USB drive.\n>> +\t */\n>> +\tswitch (phy_drd->extrefclk) {\n>> +\tcase EXYNOS5_FSEL_50MHZ:\n>> +\t\ttemp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M;\n>> +\t\tbreak;\n>> +\tcase EXYNOS5_FSEL_20MHZ:\n>> +\tcase EXYNOS5_FSEL_19MHZ2:\n>> +\t\ttemp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M;\n>> +\t\tbreak;\n>> +\tcase EXYNOS5_FSEL_24MHZ:\n>> +\tdefault:\n>> +\t\ttemp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M;\n>> +\t\tbreak;\n>> +\t}\n>> +\n>> +\tret = crport_ctrl_write(phy_drd,\n>> +\t\t\t\tEXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG,\n>> +\t\t\t\ttemp);\n>> +\tif (ret)\n>> +\t\tdev_err(phy_drd->dev,\n>> +\t\t \"Failed setting RxDetect measurement time for SuperSpeed\\n\");\n>> +\n>> +\treturn ret;\n>> +}\n>> +\n>> static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,\n>> \t\t\t\t\tstruct of_phandle_args *args)\n>> {\n>> @@ -537,11 +711,20 @@ static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,\n>> \treturn phy_drd->phys[args->args[0]].phy;\n>> }\n>> \n>> +static int exynos5_usbdrd_phy_reset(struct phy *phy)\n>> +{\n>> +\tstruct phy_usb_instance *inst = phy_get_drvdata(phy);\n>> +\tstruct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);\n>> +\n>> +\treturn exynos5420_usbdrd_phy_calibrate(phy_drd);\n>> +}\n>> +\n>> static const struct phy_ops exynos5_usbdrd_phy_ops = {\n>> \t.init\t\t= exynos5_usbdrd_phy_init,\n>> \t.exit\t\t= exynos5_usbdrd_phy_exit,\n>> \t.power_on\t= exynos5_usbdrd_phy_power_on,\n>> \t.power_off\t= exynos5_usbdrd_phy_power_off,\n>> +\t.reset\t\t= exynos5_usbdrd_phy_reset,\n>> \t.owner\t\t= THIS_MODULE,\n>> };\n>> \n>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c\n>> index 03474d3..1d5836e 100644\n>> --- a/drivers/usb/dwc3/core.c\n>> +++ b/drivers/usb/dwc3/core.c\n>> @@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work)\n>> \t\t} else {\n>> \t\t\tif (dwc->usb2_phy)\n>> \t\t\t\totg_set_vbus(dwc->usb2_phy->otg, true);\n>> -\t\t\tif (dwc->usb2_generic_phy)\n>> +\t\t\tif (dwc->usb2_generic_phy) {\n>> \t\t\t\tphy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);\n>> -\n>> +\t\t\t\tphy_reset(dwc->usb2_generic_phy);\n> \n> it doesn't look like this is the best place to reset the phy. Also,\n\nright, phy_reset is done during initialization before phy_power_on/phy_init or\nin error cases.\n\n> ->reset() doesn't seem to match correctly with a calibration. That seems\n> to be more fitting to a ->power_on() or ->init() implementation.\n\nyeah, the initial patch seems to calibrate in phy_init(). Not sure why it's\nmodified.\n\nThanks\nKishon\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"KGwevNWe\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwjrv5dffz9s7c\n\tfor ;\n\tMon, 18 Sep 2017 21:07:27 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753390AbdIRLH0 (ORCPT\n\t);\n\tMon, 18 Sep 2017 07:07:26 -0400","from fllnx210.ext.ti.com ([198.47.19.17]:61914 \"EHLO\n\tfllnx210.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1752473AbdIRLHY (ORCPT\n\t); Mon, 18 Sep 2017 07:07:24 -0400","from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby fllnx210.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8IB6d6R020684; \n\tMon, 18 Sep 2017 06:06:39 -0500","from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8IB6dla014734; \n\tMon, 18 Sep 2017 06:06:39 -0500","from DFLE100.ent.ti.com (10.64.6.21) by DFLE105.ent.ti.com\n\t(10.64.6.26) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tMon, 18 Sep 2017 06:06:39 -0500","from dflp32.itg.ti.com (10.64.6.15) by DFLE100.ent.ti.com\n\t(10.64.6.21) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Mon, 18 Sep 2017 06:06:39 -0500","from [172.24.190.233] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8IB6YvD023644;\n\tMon, 18 Sep 2017 06:06:35 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1505732799;\n\tbh=HpYtHZfwBRuNuy2H1N1AzukZaMZuvdQ34KprPV4mKbk=;\n\th=Subject:To:References:CC:From:Date:In-Reply-To;\n\tb=KGwevNWe3gH1d1+PUtVRs4K7vlmQ0YeXrECEE7dtK1NpBielR4leH7QclKolFKits\n\tSexRUZKrm2kcssM3rOTel68x3jQGxosTcDGFRTmdN8HXKIJNPlygxGwSIFZ87AmVNs\n\tafxMsVkTmgAbyfM4bjUKG7pshHfy+tgh0SokHrX8=","Subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","To":"Felipe Balbi ,\n\tAndrzej Pietrasiewicz ,\n\t, ,\n\t, ","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505729371-6509-1-git-send-email-andrzej.p@samsung.com>\n\t<87y3pcmgv6.fsf@linux.intel.com>","CC":"Marek Szyprowski ,\n\tBartlomiej Zolnierkiewicz ,\n\tKrzysztof Kozlowski , Kukjin Kim , \n\tRussell King ,\n\tMark Rutland , Rob Herring ,\n\tGreg Kroah-Hartman ","From":"Kishon Vijay Abraham I ","Message-ID":"","Date":"Mon, 18 Sep 2017 16:36:33 +0530","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.7.0","MIME-Version":"1.0","In-Reply-To":"<87y3pcmgv6.fsf@linux.intel.com>","Content-Type":"text/plain; charset=\"windows-1252\"","Content-Transfer-Encoding":"7bit","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1770087,"web_url":"http://patchwork.ozlabs.org/comment/1770087/","msgid":"","list_archive_url":null,"date":"2017-09-18T11:19:20","subject":"Re: [PATCH 0/2] dwc3 on XU3 and XU4","submitter":{"id":66060,"url":"http://patchwork.ozlabs.org/api/people/66060/","name":"Anand Moon","email":"linux.amoon@gmail.com"},"content":"Hi Andrzej,\n\nOn 18 September 2017 at 15:32, Andrzej Pietrasiewicz\n wrote:\n> Hi all,\n>\n> this short series addresses two issues.\n>\n> The first issue is devices not enumerating when connected to an Odroid XU4,\n> to its 3.0 root hub. The interplay between refactoring certain parts of\n> dwc3's code and handling the SUSPHY quirk results in the said problem.\n> Please see: https://patchwork.kernel.org/patch/9535235/\n> Actually using the quirk solves it.\n>\n> The second issue is devices not enumerating and/or wrongly enumerating\n> as high speed instead of super speed on an Odroid XU3. There was a patch\n> series from Vivek Gautam in circulation, but it got lost somehow.\n> Please see:\n>\n> https://lkml.org/lkml/2014/9/2/166\n> https://lkml.org/lkml/2015/2/2/257\n>\n> I adapted his patch so that it does not use a hacky solution to force\n> additional initialization in order for calibration to happen.\n> Instead I used the .reset() in phy_ops. I could have used the .set_mode(),\n> but the calibration must happen only after dwc3_host_init() but\n> phy_set_mode() is called either after of before it. With this patch\n> enumeration happens correctly and a super speed device is recognized as such.\n>\n> Rebased onto v4.13. It also applies cleanly to Felipe's testing/next.\n>\n> Andrzej Pietrasiewicz (1):\n> ARM: dts: exynos: Add dwc3 SUSPHY quirk\n>\n> Vivek Gautam (1):\n> phy: exynos5-usbdrd: Calibrate LOS levels for exynos5420/5800\n>\n> arch/arm/boot/dts/exynos54xx.dtsi | 2 +\n> drivers/phy/samsung/phy-exynos5-usbdrd.c | 183 +++++++++++++++++++++++++++++++\n> drivers/usb/dwc3/core.c | 8 +-\n> 3 files changed, 191 insertions(+), 2 deletions(-)\n>\n\nThanks for rending this patch series.\n\nI would like to suggestion some more pointer to this issue.\nBoth the usb 2.0 phy and usb 3.0 tune and calibrate are missing in the\ncurrent driver.\nLately I have searched on this topic on github so accidentally landed on.\n\n[0] https://github.com/wanam/Adam-Kernel-GalaxyS6-G920F/blob/master/drivers/usb/phy/phy-samsung-usb3-cal.c\n[1] https://github.com/wanam/Adam-Kernel-GalaxyS6-G920F/blob/master/drivers/usb/phy/phy-samsung-usb2-cal.c\n\nI have tried to mapped few of the change and was able to partially\nstabilize the driver.\n\nBut few of the changes are mixed with other platform soc probably Exynos 5433.\n\nWould it be possible for you to look into into this new approach to\nfix and stabilize this driver.\n\nBest Regards\n-Anand Moon\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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charset=\"UTF-8\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1770090,"web_url":"http://patchwork.ozlabs.org/comment/1770090/","msgid":"<96001441-2a67-ac9c-a606-eac66138d09e@samsung.com>","list_archive_url":null,"date":"2017-09-18T11:27:14","subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","submitter":{"id":9958,"url":"http://patchwork.ozlabs.org/api/people/9958/","name":"Andrzej Pietrasiewicz","email":"andrzej.p@samsung.com"},"content":"W dniu 18.09.2017 o 13:06, Kishon Vijay Abraham I pisze:\n> Hi,\n> \n> On Monday 18 September 2017 04:08 PM, Felipe Balbi wrote:\n>>\n>> Hi,\n>>\n>> Andrzej Pietrasiewicz writes:\n>>> From: Vivek Gautam \n>>>\n>>> Adding phy calibration sequence for USB 3.0 DRD PHY present on\n>>> Exynos5420/5800 systems.\n\n\n\n>>> \n>>> +static int exynos5_usbdrd_phy_reset(struct phy *phy)\n>>> +{\n>>> +\tstruct phy_usb_instance *inst = phy_get_drvdata(phy);\n>>> +\tstruct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);\n>>> +\n>>> +\treturn exynos5420_usbdrd_phy_calibrate(phy_drd);\n>>> +}\n>>> +\n>>> static const struct phy_ops exynos5_usbdrd_phy_ops = {\n>>> \t.init\t\t= exynos5_usbdrd_phy_init,\n>>> \t.exit\t\t= exynos5_usbdrd_phy_exit,\n>>> \t.power_on\t= exynos5_usbdrd_phy_power_on,\n>>> \t.power_off\t= exynos5_usbdrd_phy_power_off,\n>>> +\t.reset\t\t= exynos5_usbdrd_phy_reset,\n>>> \t.owner\t\t= THIS_MODULE,\n>>> };\n>>> \n>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c\n>>> index 03474d3..1d5836e 100644\n>>> --- a/drivers/usb/dwc3/core.c\n>>> +++ b/drivers/usb/dwc3/core.c\n>>> @@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work)\n>>> \t\t} else {\n>>> \t\t\tif (dwc->usb2_phy)\n>>> \t\t\t\totg_set_vbus(dwc->usb2_phy->otg, true);\n>>> -\t\t\tif (dwc->usb2_generic_phy)\n>>> +\t\t\tif (dwc->usb2_generic_phy) {\n>>> \t\t\t\tphy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);\n>>> -\n>>> +\t\t\t\tphy_reset(dwc->usb2_generic_phy);\n>>\n>> it doesn't look like this is the best place to reset the phy. Also,\n> \n> right, phy_reset is done during initialization before phy_power_on/phy_init or\n> in error cases.\n> \n>> ->reset() doesn't seem to match correctly with a calibration. That seems\n>> to be more fitting to a ->power_on() or ->init() implementation.\n> \n> yeah, the initial patch seems to calibrate in phy_init(). Not sure why it's\n> modified.\n\nThe original patch used a hack like below, in xhci_plat_probe():\n\n+ /* Initialize and power-on USB 3.0 PHY */\n+ xhci->shared_hcd->phy->init_count = 0;\n+ ret = phy_init(xhci->shared_hcd->phy);\n+ if (ret)\n+ goto dealloc_usb3_hcd;\n+\n+ xhci->shared_hcd->phy->power_count = 0;\n+ ret = phy_power_on(xhci->shared_hcd->phy);\n+ if (ret) {\n+ phy_exit(xhci->shared_hcd->phy);\n+ goto dealloc_usb3_hcd;\n+ }\n+\n\nManually setting init_count to 0 in order for the subsequent phy_init() to\nhappen probably does not look good.\n\nThe calibration is clearly needed. However, I don't have any strong opinions\non from which place exactly to trigger the calibration process.\nThe original patch did not make it upstream, but if that patch is ok,\nit is perfectly fine with me to drop my version and take that one instead.\n\nAndrzej\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwkJ32Sjwz9s7M\n\tfor ;\n\tMon, 18 Sep 2017 21:27:31 +1000 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(BST)","from eusmgms2.samsung.com (unknown [182.198.249.180]) by\n\teucas1p2.samsung.com (KnoxPortal) with ESMTP id\n\t20170918112723eucas1p2f8a8e88677e776dae98356d72d3150ee~lcSJo0Wus1816018160eucas1p2Z;\n\tMon, 18 Sep 2017 11:27:23 +0000 (GMT)","from eusync3.samsung.com ( [203.254.199.213]) by\n\teusmgms2.samsung.com (EUCPMTA) with SMTP id 03.43.20118.A9DAFB95;\n\tMon, 18 Sep 2017 12:27:22 +0100 (BST)","from [106.116.147.122] by eusync3.samsung.com (Oracle\n\tCommunications Messaging Server 7.0.5.31.0 64bit (built May 5 2014))\n\twith ESMTPA id <0OWH008183TL2P20@eusync3.samsung.com>;\n\tMon, 18 Sep 2017 12:27:22 +0100 (BST)"],"X-AuditID":"cbfec7f1-f793a6d00000326b-5b-59bfad9b16db","MIME-version":"1.0","Content-type":"text/plain; charset=\"windows-1252\"; format=\"flowed\"","Subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","To":"Kishon Vijay Abraham I , Felipe Balbi , \n\tlinux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org","Cc":"Marek Szyprowski ,\n\tBartlomiej Zolnierkiewicz ,\n\tKrzysztof Kozlowski , Kukjin Kim , \n\tRussell King ,\n\tMark Rutland , Rob Herring ,\n\tGreg Kroah-Hartman ","From":"Andrzej Pietrasiewicz ","Message-id":"<96001441-2a67-ac9c-a606-eac66138d09e@samsung.com>","Date":"Mon, 18 Sep 2017 13:27:14 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","In-reply-to":"","Content-language":"en-US","Content-transfer-encoding":"8bit","X-Brightmail-Tracker":["H4sIAAAAAAAAA01Sa0hTYRju29nOjtLsOG+vF7ImBZZpWtTJ0jSiTj8K/5X+qEYeL+RUdlRa\n\tBBnifZm38oZm1gyHNp0ylVBxmoqB25pZGt5Q8fZjXgg0RNKdCf573u99vvd9noeXwMQmgQcR\n\tn5jCyBOlCRLcnq8b2Dacq2rqiTxf1OhOtZRrBNRA1ryQet8/IqAyPmpw6s3cKkYZF5Q4ZTA0\n\tCynt3JiAKjd086i6+kyM0r/tQlRT/6SQUv0y8ajMrn5hmAPdWNOIaPOYCaO16lyc7qluFNKt\n\tn17SBW1qRA/+bufRm9rjEUSU/bVoJiE+jZEHhD62j1N+NeLJ3a7P1uaLeelowjEP2RFAXoSa\n\tiQaMw65gnNLgecieEJMqBOWFaj5XbCJY2dLxDn506xaEXKMewWTHBr7fEJGOsFUyxd/HGBkO\n\tM3WdAo60hCCnasZKciIfwFxJtXWsM2lAoCxbshYYaeKBfqgC7bNw8gJ09eYgbmwo/FkqtSrk\n\tk6ega3jd+u6yN8mo3d7TRBB2ZDBMtyJusxtkZI7bVHhD7+gin5NdI4SN9escvgnfzH9tpp1g\n\tZbBNyGEvMJfkW/UAWYKgeXzNVrQjaBoYEnCsq9A3aBJwGxygWFeG7YsAUgQ5WWKOQsOrRbWN\n\tHg5Ky5QtyHoemOZysULkXXkosspDkVUeMlF5yEQt4quRM5PKymIZNsiflcrY1MRY/ydJMi3a\n\tO7Tvu4PrHcgyFKxHJIEkR0Utq92RYoE0jVXI9AgITOIsCmvoiRSLoqWK54w86ZE8NYFh9ciT\n\t4EvcRCFRWZFiMlaawjxlmGRGftDlEXYe6UghSq7zu9npUJSc3TKitNzaVd3R0id+aI54Rlxa\n\tCPpc5nUs5N/kyG4t5vsh5rX7su7+zsOqaTylQKbI9ovVl0Xdq88/vdLR+0X5Ltqc7hNwu5rt\n\tq9hRXTZbZgN9bpT+9J1yGXVfdMnum108+SJmSBFzdzjeb7kl4+zA+hVjg2OBVMJn46SBZzA5\n\tK/0P2t4u6mQDAAA=","H4sIAAAAAAAAA+NgFlrKIsWRmVeSWpSXmKPExsVy+t/xq7qz1u6PNHi028Zi44z1rBbH2p6w\n\tW8w/co7VonnxejaL/sevmS0uPO1hszh/fgO7xabH11gtZpzfx2SxaFkrs8WhqXsZLdYeuctu\n\tsfT6RSaL1r1H2B34PNbMW8PocfnaRWaPTas62Tz2z13D7rF5Sb1H35ZVjB7Hb2xn8vi8SS6A\n\tI4rLJiU1J7MstUjfLoEro2f3BbaCfWIVH55MYmpgvCXYxcjJISFgIrFv21N2CFtM4sK99Wxd\n\tjFwcQgJLGCU6dqxgA0nwCghK/Jh8jwXEZhawlVjwfh0LRNELRonen7uYQRLCAhESjyfPBUuI\n\tCJxnlFj78zUjiMMscJlJ4tHRqVAtS5gkzs/fDjaLTcBYYu/BDkaIHXYSt19MARvFIqAqsffU\n\tR6A4B4co0NgNG/lBTE4BK4n7mxkhrhCXaG69CXWRvMTBK89ZJjAKzkJy7Cwkx85C0jILScsC\n\tRpZVjCKppcW56bnFRnrFibnFpXnpesn5uZsYgZG37djPLTsYu94FH2IU4GBU4uHd8HpfpBBr\n\tYllxZe4hRgkOZiURXoeV+yOFeFMSK6tSi/Lji0pzUosPMUpzsCiJ8/buWR0pJJCeWJKanZpa\n\tkFoEk2Xi4JRqYHQRkZh/5JsI10TbmcEJ2k7bsoSVWKz3dXA0TUz5rvtLQ2jFts9+W5UMtodo\n\t+/puON/7o5XjovjiSe5HDn8Jv6QSeSwlO8y/tFmHN7n+2r+vd7N2sF7JOOs2SeuJiVHp/GQO\n\twX2dLx0kOXackjO7n7HySPXE7N42RtGZWYHp2+M3yxyrkxftUmIpzkg01GIuKk4EAMxPCY24\n\tAgAA"],"X-CMS-MailID":"20170918112723eucas1p2f8a8e88677e776dae98356d72d3150ee","X-Msg-Generator":"CA","X-Sender-IP":"182.198.249.180","X-Local-Sender":"=?utf-8?q?Andrzej_Pietrasiewicz=1BSRPOL-Kernel_=28TP=29?=\n\t=?utf-8?b?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?=","X-Global-Sender":"=?utf-8?q?Andrzej_Tomasz_Pietrasiewicz=1BSRPOL-Kernel_?=\n\t=?utf-8?q?=28TP=29=1BSamsung_Electronics=1BSenior_Software_Enginee?=\n\t=?utf-8?q?r?=","X-Sender-Code":"=?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?=","CMS-TYPE":"201P","X-CMS-RootMailID":"20170918100944eucas1p2735d3d6a6ee562b927fb9dfaeb0d4090","X-RootMTR":"20170918100944eucas1p2735d3d6a6ee562b927fb9dfaeb0d4090","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505729371-6509-1-git-send-email-andrzej.p@samsung.com>\n\t<87y3pcmgv6.fsf@linux.intel.com>\n\t","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1770094,"web_url":"http://patchwork.ozlabs.org/comment/1770094/","msgid":"<5c90f022-5cb1-c746-6015-c93a58805cfe@samsung.com>","list_archive_url":null,"date":"2017-09-18T11:41:37","subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","submitter":{"id":9958,"url":"http://patchwork.ozlabs.org/api/people/9958/","name":"Andrzej Pietrasiewicz","email":"andrzej.p@samsung.com"},"content":"Hi,\n\nW dniu 18.09.2017 o 13:27, Andrzej Pietrasiewicz pisze:\n> W dniu 18.09.2017 o 13:06, Kishon Vijay Abraham I pisze:\n>> Hi,\n>>\n>> On Monday 18 September 2017 04:08 PM, Felipe Balbi wrote:\n>>>\n>>> Hi,\n>>>\n>>> Andrzej Pietrasiewicz writes:\n>>>> From: Vivek Gautam \n>>>>\n>>>> Adding phy calibration sequence for USB 3.0 DRD PHY present on\n>>>> Exynos5420/5800 systems.\n> \n> \n> \n>>>> \n>>>> +static int exynos5_usbdrd_phy_reset(struct phy *phy)\n>>>> +{\n>>>> +\tstruct phy_usb_instance *inst = phy_get_drvdata(phy);\n>>>> +\tstruct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);\n>>>> +\n>>>> +\treturn exynos5420_usbdrd_phy_calibrate(phy_drd);\n>>>> +}\n>>>> +\n>>>> static const struct phy_ops exynos5_usbdrd_phy_ops = {\n>>>> \t.init\t\t= exynos5_usbdrd_phy_init,\n>>>> \t.exit\t\t= exynos5_usbdrd_phy_exit,\n>>>> \t.power_on\t= exynos5_usbdrd_phy_power_on,\n>>>> \t.power_off\t= exynos5_usbdrd_phy_power_off,\n>>>> +\t.reset\t\t= exynos5_usbdrd_phy_reset,\n>>>> \t.owner\t\t= THIS_MODULE,\n>>>> };\n>>>> \n>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c\n>>>> index 03474d3..1d5836e 100644\n>>>> --- a/drivers/usb/dwc3/core.c\n>>>> +++ b/drivers/usb/dwc3/core.c\n>>>> @@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work)\n>>>> \t\t} else {\n>>>> \t\t\tif (dwc->usb2_phy)\n>>>> \t\t\t\totg_set_vbus(dwc->usb2_phy->otg, true);\n>>>> -\t\t\tif (dwc->usb2_generic_phy)\n>>>> +\t\t\tif (dwc->usb2_generic_phy) {\n>>>> \t\t\t\tphy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);\n>>>> -\n>>>> +\t\t\t\tphy_reset(dwc->usb2_generic_phy);\n>>>\n>>> it doesn't look like this is the best place to reset the phy. Also,\n>>\n>> right, phy_reset is done during initialization before phy_power_on/phy_init or\n>> in error cases.\n>>\n>>> ->reset() doesn't seem to match correctly with a calibration. That seems\n>>> to be more fitting to a ->power_on() or ->init() implementation.\n>>\n>> yeah, the initial patch seems to calibrate in phy_init(). Not sure why it's\n>> modified.\n> \n> The original patch used a hack like below, in xhci_plat_probe():\n> \n> + /* Initialize and power-on USB 3.0 PHY */\n> + xhci->shared_hcd->phy->init_count = 0;\n> + ret = phy_init(xhci->shared_hcd->phy);\n> + if (ret)\n> + goto dealloc_usb3_hcd;\n> +\n> + xhci->shared_hcd->phy->power_count = 0;\n> + ret = phy_power_on(xhci->shared_hcd->phy);\n> + if (ret) {\n> + phy_exit(xhci->shared_hcd->phy);\n> + goto dealloc_usb3_hcd;\n> + }\n> +\n> \n> Manually setting init_count to 0 in order for the subsequent phy_init() to\n> happen probably does not look good.\n> \n> The calibration is clearly needed. However, I don't have any strong opinions\n> on from which place exactly to trigger the calibration process.\n> The original patch did not make it upstream, but if that patch is ok,\n> it is perfectly fine with me to drop my version and take that one instead.\n\nMe bad, I did not write about an important issue.\nThe calibration must happen after usb_add_hcd(), otherwise\nusb_add_hcd() indirectly triggers overwriting the effects of calibration.\n\nAndrzej\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; 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exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","From":"Andrzej Pietrasiewicz ","To":"Kishon Vijay Abraham I , Felipe Balbi , \n\tlinux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org","Cc":"Marek Szyprowski ,\n\tBartlomiej Zolnierkiewicz ,\n\tKrzysztof Kozlowski , Kukjin Kim , \n\tRussell King ,\n\tMark Rutland , Rob Herring ,\n\tGreg Kroah-Hartman ","Message-id":"<5c90f022-5cb1-c746-6015-c93a58805cfe@samsung.com>","Date":"Mon, 18 Sep 2017 13:41:37 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","In-reply-to":"<96001441-2a67-ac9c-a606-eac66138d09e@samsung.com>","Content-language":"en-US","Content-transfer-encoding":"8bit","X-Brightmail-Tracker":["H4sIAAAAAAAAA02SbUhTURjHOffebVdrcp2WJ7OkgWBCZpl1KTWFlPsl2CdrWtjIi4rOl01F\n\tZ6SyHL5lkixtoJW6UUPZvPmS+TJcMo3AKebMLBGmOJMwMdIhSro7Yd9+5zz///Oc58/BUcEM\n\tJxDPzCmgZTmSbCHXG+uzOK0XnEaTOOJ34zWyu9nAIS2qZR75amySQyrbDVzymX0dJadW6rik\n\t1WrkkYzdxiGbrSMI2aarREmzehiQXWM/eaR2bhohK4fHeHE+VGdrJ6BmbNMoxeiruZSppZNH\n\tve8oo+p79IAa/9aPUFvMWRGe7B2dRmdnFtGyi7EPvDNaO2qwPOZUsYMZRMvBnl8N8MIhcQWu\n\tvHGiLJ+EU4sGbg3wxgWEFkCG+QjYwxaAC7Za7Mixu7PtVukArNA2uAp8whfuNC66GCXi4VLb\n\tAIcVOQB8smEHhwU/4i60N7a4RFwiEg6PVrlG+BNWAOuaHNjhASWmEWieeAnYtrFwv82EHDJG\n\thMBuW5+LTxx0mmKcLvYibsLhp3uAHR0AlZXz7mcEw9Gvq66mkGjjwdmtOYRd4hbcNnVzWPaD\n\tv8Z7eCwHweqqUYQ1NAJonP/jdvcD2GWZcDtuwE/j0xx2hA983td0ECB+cM+HVSoBK6Fgxare\n\tLY+HdRuLGBvGAgItLyrQBhCs8QhN4xGaxmMLjccWrwGmB/50oVyaTssvh8slUnlhTnr4w1wp\n\tAw6+2pf98c0PYGPiuhkQOBAe53evj4gFHEmRvERqBhBHhf78uHcmsYCfJilR0LLcVFlhNi03\n\tg9M4JgzgxySrxAIiXVJAZ9F0Hi07qiK4V2A5iFiOL4kWTg7+0N0puyeyD4lT7ecfFydszeSL\n\tUhwJpVNRM7nLmlrtrD2Bm5i0Eb/2/Z9SP+b7eU6ftFl0O25Sf65U0ntsQJEi3lxTqcPvhxgi\n\tY0JFmX+V2qs69Xb+pLHPOLu7lNQrClOpzyRGKcDQo9asoPXQtzntEdL6EAUjxOQZkkthqEwu\n\t+Q/8dxDVZgMAAA==","H4sIAAAAAAAAA+NgFlrGIsWRmVeSWpSXmKPExsVy+t/xq7o/N+yPNHjVy2uxccZ6VotjbU/Y\n\tLeYfOcdq0bx4PZtF/+PXzBYXnvawWZw/v4HdYtPja6wWM87vY7JYtKyV2eLQ1L2MFmuP3GW3\n\tWHr9IpNF694j7A58HmvmrWH0uHztIrPHplWdbB77565h99i8pN6jb8sqRo/jN7YzeXzeJBfA\n\tEcVlk5Kak1mWWqRvl8CVMW9JF0vBJsmKF5t2Mzcw/hXuYuTkkBAwkfj94zsbhC0mceHeeiCb\n\ti0NIYAmjRO/8JcwgCV4BQYkfk++xgNjMArYSC96vY4EoesEo8fvjT7CEsECExOPJc8FsNgFj\n\tib0HOxhBikQEzjNKrP35GsxhFrjMJPHo6FSo9ptMEt+2HGGD2GEn8W/RfiYQm0VAVWLjtW1A\n\tNgeHKNDYDRv5QcKcAvYSe3v/MkKcIS7R3HoT6iR5iYNXnrNMYBScheTaWUiunYWkZRaSlgWM\n\tLKsYRVJLi3PTc4sN9YoTc4tL89L1kvNzNzECY2/bsZ+bdzBe2hh8iFGAg1GJh3fD632RQqyJ\n\tZcWVuYcYJTiYlUR4HVbujxTiTUmsrEotyo8vKs1JLT7EKM3BoiTO27tndaSQQHpiSWp2ampB\n\tahFMlomDU6qBcbZtgv3b7SbBzUv+7mo03PH+YAr3r/0xN32cnv7tjnxwfNvbGxq7xRdc2ZHh\n\tceLuS8U9XMaF3xau4fHwTPxzf0HZ3Y9FJ1y/MzBd6Irpmc57O+Yfx2F9vZyDpktajpYHrmBp\n\tt1rzdPuraN3QZdd/uVr+du1b3P7WP1b9JHepw72HK2pY8if90lZiKc5INNRiLipOBADB4f0f\n\tuQIAAA=="],"X-CMS-MailID":"20170918114145eucas1p14b04988c05909b55c0b50b9777800aea","X-Msg-Generator":"CA","X-Sender-IP":"182.198.249.179","X-Local-Sender":"=?utf-8?q?Andrzej_Pietrasiewicz=1BSRPOL-Kernel_=28TP=29?=\n\t=?utf-8?b?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?=","X-Global-Sender":"=?utf-8?q?Andrzej_Tomasz_Pietrasiewicz=1BSRPOL-Kernel_?=\n\t=?utf-8?q?=28TP=29=1BSamsung_Electronics=1BSenior_Software_Enginee?=\n\t=?utf-8?q?r?=","X-Sender-Code":"=?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?=","CMS-TYPE":"201P","X-CMS-RootMailID":"20170918100944eucas1p2735d3d6a6ee562b927fb9dfaeb0d4090","X-RootMTR":"20170918100944eucas1p2735d3d6a6ee562b927fb9dfaeb0d4090","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505729371-6509-1-git-send-email-andrzej.p@samsung.com>\n\t<87y3pcmgv6.fsf@linux.intel.com>\n\t\n\t<96001441-2a67-ac9c-a606-eac66138d09e@samsung.com>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1770133,"web_url":"http://patchwork.ozlabs.org/comment/1770133/","msgid":"<87vakgmb24.fsf@linux.intel.com>","list_archive_url":null,"date":"2017-09-18T12:43:47","subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","submitter":{"id":68254,"url":"http://patchwork.ozlabs.org/api/people/68254/","name":"Felipe Balbi","email":"balbi@kernel.org"},"content":"Hi,\n\nAndrzej Pietrasiewicz writes:\n>>>>> +static int exynos5_usbdrd_phy_reset(struct phy *phy)\n>>>>> +{\n>>>>> +\tstruct phy_usb_instance *inst = phy_get_drvdata(phy);\n>>>>> +\tstruct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);\n>>>>> +\n>>>>> +\treturn exynos5420_usbdrd_phy_calibrate(phy_drd);\n>>>>> +}\n>>>>> +\n>>>>> static const struct phy_ops exynos5_usbdrd_phy_ops = {\n>>>>> \t.init\t\t= exynos5_usbdrd_phy_init,\n>>>>> \t.exit\t\t= exynos5_usbdrd_phy_exit,\n>>>>> \t.power_on\t= exynos5_usbdrd_phy_power_on,\n>>>>> \t.power_off\t= exynos5_usbdrd_phy_power_off,\n>>>>> +\t.reset\t\t= exynos5_usbdrd_phy_reset,\n>>>>> \t.owner\t\t= THIS_MODULE,\n>>>>> };\n>>>>> \n>>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c\n>>>>> index 03474d3..1d5836e 100644\n>>>>> --- a/drivers/usb/dwc3/core.c\n>>>>> +++ b/drivers/usb/dwc3/core.c\n>>>>> @@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work)\n>>>>> \t\t} else {\n>>>>> \t\t\tif (dwc->usb2_phy)\n>>>>> \t\t\t\totg_set_vbus(dwc->usb2_phy->otg, true);\n>>>>> -\t\t\tif (dwc->usb2_generic_phy)\n>>>>> +\t\t\tif (dwc->usb2_generic_phy) {\n>>>>> \t\t\t\tphy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);\n>>>>> -\n>>>>> +\t\t\t\tphy_reset(dwc->usb2_generic_phy);\n>>>>\n>>>> it doesn't look like this is the best place to reset the phy. Also,\n>>>\n>>> right, phy_reset is done during initialization before phy_power_on/phy_init or\n>>> in error cases.\n>>>\n>>>> ->reset() doesn't seem to match correctly with a calibration. That seems\n>>>> to be more fitting to a ->power_on() or ->init() implementation.\n>>>\n>>> yeah, the initial patch seems to calibrate in phy_init(). Not sure why it's\n>>> modified.\n>> \n>> The original patch used a hack like below, in xhci_plat_probe():\n>> \n>> + /* Initialize and power-on USB 3.0 PHY */\n>> + xhci->shared_hcd->phy->init_count = 0;\n>> + ret = phy_init(xhci->shared_hcd->phy);\n>> + if (ret)\n>> + goto dealloc_usb3_hcd;\n>> +\n>> + xhci->shared_hcd->phy->power_count = 0;\n>> + ret = phy_power_on(xhci->shared_hcd->phy);\n>> + if (ret) {\n>> + phy_exit(xhci->shared_hcd->phy);\n>> + goto dealloc_usb3_hcd;\n>> + }\n>> +\n>> \n>> Manually setting init_count to 0 in order for the subsequent phy_init() to\n>> happen probably does not look good.\n>> \n>> The calibration is clearly needed. However, I don't have any strong opinions\n>> on from which place exactly to trigger the calibration process.\n>> The original patch did not make it upstream, but if that patch is ok,\n>> it is perfectly fine with me to drop my version and take that one instead.\n>\n> Me bad, I did not write about an important issue.\n> The calibration must happen after usb_add_hcd(), otherwise\n> usb_add_hcd() indirectly triggers overwriting the effects of calibration.\n\nin that case, you should do that from xhci-plat indeed. I think the\nwhole idea with init_count is just to make sure you don't initialize it\ntwice.\n\nOne thing's for sure, ->reset() doesn't seem to be the matching callback\nfor you to use and, given your explanation above, dwc3 doesn't seem to\nbe the right place to fiddle with that.\n\nSeems like we need an extension of the generic PHY framework to cope\nwith your requirement.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwm0V25T5z9s7c\n\tfor ;\n\tMon, 18 Sep 2017 22:44:10 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S932294AbdIRMoI (ORCPT );\n\tMon, 18 Sep 2017 08:44:08 -0400","from mga05.intel.com ([192.55.52.43]:14789 \"EHLO mga05.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S932292AbdIRMoI (ORCPT );\n\tMon, 18 Sep 2017 08:44:08 -0400","from orsmga004.jf.intel.com ([10.7.209.38])\n\tby fmsmga105.fm.intel.com with ESMTP; 18 Sep 2017 05:44:07 -0700","from pipin.fi.intel.com (HELO localhost) ([10.237.68.37])\n\tby orsmga004.jf.intel.com with ESMTP; 18 Sep 2017 05:44:03 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,412,1500966000\"; \n\td=\"asc'?scan'208\";a=\"129804346\"","From":"Felipe Balbi ","To":"Andrzej Pietrasiewicz ,\n\tKishon Vijay Abraham I ,\n\tlinux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org","Cc":"Marek Szyprowski ,\n\tBartlomiej Zolnierkiewicz ,\n\tKrzysztof Kozlowski , Kukjin Kim , \n\tRussell King ,\n\tMark Rutland , Rob Herring ,\n\tGreg Kroah-Hartman ","Subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","In-Reply-To":"<5c90f022-5cb1-c746-6015-c93a58805cfe@samsung.com>","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505729371-6509-1-git-send-email-andrzej.p@samsung.com>\n\t<87y3pcmgv6.fsf@linux.intel.com>\n\t\n\t<96001441-2a67-ac9c-a606-eac66138d09e@samsung.com>\n\t<5c90f022-5cb1-c746-6015-c93a58805cfe@samsung.com>","Date":"Mon, 18 Sep 2017 15:43:47 +0300","Message-ID":"<87vakgmb24.fsf@linux.intel.com>","MIME-Version":"1.0","Content-Type":"multipart/signed; boundary=\"=-=-=\";\n\tmicalg=pgp-sha512; protocol=\"application/pgp-signature\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1770197,"web_url":"http://patchwork.ozlabs.org/comment/1770197/","msgid":"<7d87727a-e65e-f25b-0cdc-fe6ff0b7bb90@samsung.com>","list_archive_url":null,"date":"2017-09-18T14:20:22","subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","submitter":{"id":9958,"url":"http://patchwork.ozlabs.org/api/people/9958/","name":"Andrzej Pietrasiewicz","email":"andrzej.p@samsung.com"},"content":"Hi,\n\nW dniu 18.09.2017 o 14:43, Felipe Balbi pisze:\n> \n> Hi,\n> \n> Andrzej Pietrasiewicz writes:\n>>>>>> +static int exynos5_usbdrd_phy_reset(struct phy *phy)\n>>>>>> +{\n>>>>>> +\tstruct phy_usb_instance *inst = phy_get_drvdata(phy);\n>>>>>> +\tstruct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);\n>>>>>> +\n>>>>>> +\treturn exynos5420_usbdrd_phy_calibrate(phy_drd);\n>>>>>> +}\n>>>>>> +\n>>>>>> static const struct phy_ops exynos5_usbdrd_phy_ops = {\n>>>>>> \t.init\t\t= exynos5_usbdrd_phy_init,\n>>>>>> \t.exit\t\t= exynos5_usbdrd_phy_exit,\n>>>>>> \t.power_on\t= exynos5_usbdrd_phy_power_on,\n>>>>>> \t.power_off\t= exynos5_usbdrd_phy_power_off,\n>>>>>> +\t.reset\t\t= exynos5_usbdrd_phy_reset,\n>>>>>> \t.owner\t\t= THIS_MODULE,\n>>>>>> };\n>>>>>> \n>>>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c\n>>>>>> index 03474d3..1d5836e 100644\n>>>>>> --- a/drivers/usb/dwc3/core.c\n>>>>>> +++ b/drivers/usb/dwc3/core.c\n>>>>>> @@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work)\n>>>>>> \t\t} else {\n>>>>>> \t\t\tif (dwc->usb2_phy)\n>>>>>> \t\t\t\totg_set_vbus(dwc->usb2_phy->otg, true);\n>>>>>> -\t\t\tif (dwc->usb2_generic_phy)\n>>>>>> +\t\t\tif (dwc->usb2_generic_phy) {\n>>>>>> \t\t\t\tphy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);\n>>>>>> -\n>>>>>> +\t\t\t\tphy_reset(dwc->usb2_generic_phy);\n>>>>>\n>>>>> it doesn't look like this is the best place to reset the phy. Also,\n>>>>\n>>>> right, phy_reset is done during initialization before phy_power_on/phy_init or\n>>>> in error cases.\n>>>>\n>>>>> ->reset() doesn't seem to match correctly with a calibration. That seems\n>>>>> to be more fitting to a ->power_on() or ->init() implementation.\n>>>>\n>>>> yeah, the initial patch seems to calibrate in phy_init(). Not sure why it's\n>>>> modified.\n>>>\n>>> The original patch used a hack like below, in xhci_plat_probe():\n>>>\n>>> + /* Initialize and power-on USB 3.0 PHY */\n>>> + xhci->shared_hcd->phy->init_count = 0;\n>>> + ret = phy_init(xhci->shared_hcd->phy);\n>>> + if (ret)\n>>> + goto dealloc_usb3_hcd;\n>>> +\n>>> + xhci->shared_hcd->phy->power_count = 0;\n>>> + ret = phy_power_on(xhci->shared_hcd->phy);\n>>> + if (ret) {\n>>> + phy_exit(xhci->shared_hcd->phy);\n>>> + goto dealloc_usb3_hcd;\n>>> + }\n>>> +\n>>>\n>>> Manually setting init_count to 0 in order for the subsequent phy_init() to\n>>> happen probably does not look good.\n>>>\n>>> The calibration is clearly needed. However, I don't have any strong opinions\n>>> on from which place exactly to trigger the calibration process.\n>>> The original patch did not make it upstream, but if that patch is ok,\n>>> it is perfectly fine with me to drop my version and take that one instead.\n>>\n>> Me bad, I did not write about an important issue.\n>> The calibration must happen after usb_add_hcd(), otherwise\n>> usb_add_hcd() indirectly triggers overwriting the effects of calibration.\n> \n> in that case, you should do that from xhci-plat indeed. I think the\n> whole idea with init_count is just to make sure you don't initialize it\n> twice.\n\nAs far as I understand the code in question the desired result is exactly the opposite:\nto make sure it _does_ initialize twice, otherwise after the first initialization the\ncalibration results were lost. In other words, in the code snippet above,\nin xhci_plat_probe() the phy_init() was creatively (ab)used in order to force\nthe calibration at a desired moment, while in the original invocation of phy_init()\nthe calibration result was merely a short-term side effect discarded soon afterwards.\n\n> \n> One thing's for sure, ->reset() doesn't seem to be the matching callback\n> for you to use and, given your explanation above, dwc3 doesn't seem to\n> be the right place to fiddle with that.\n> \n> Seems like we need an extension of the generic PHY framework to cope\n> with your requirement.\n>\n\nHere are old patches from Vivek:\n\nhttps://lkml.org/lkml/2014/9/2/166\n\nIn particular:\n\nhttps://lkml.org/lkml/2014/9/2/170\n\nPlease see the discussion that follows the latter.\n\nAll in all, is adding the calibrate() method to phy_ops the way to go or not?\n\nAndrzej\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xwp7w49nBz9s7c\n\tfor ;\n\tTue, 19 Sep 2017 00:20:44 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1753895AbdIROUj (ORCPT\n\t);\n\tMon, 18 Sep 2017 10:20:39 -0400","from mailout2.w1.samsung.com ([210.118.77.12]:56151 \"EHLO\n\tmailout2.w1.samsung.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1753437AbdIROUg (ORCPT\n\t); Mon, 18 Sep 2017 10:20:36 -0400","from eucas1p1.samsung.com (unknown [182.198.249.206])\n\tby mailout2.w1.samsung.com (KnoxPortal) with ESMTP id\n\t20170918142033euoutp02129eed2b7da2398e07f12bb5a6432059~lepWtMqBS0206202062euoutp02F;\n\tMon, 18 Sep 2017 14:20:33 +0000 (GMT)","from eusmges2.samsung.com (unknown [203.254.199.241]) by\n\teucas1p2.samsung.com (KnoxPortal) with ESMTP id\n\t20170918142031eucas1p2a5a24d49330f6656da7e83c98c444ff2~lepUN-46p1088210882eucas1p2y;\n\tMon, 18 Sep 2017 14:20:31 +0000 (GMT)","from eucas1p2.samsung.com ( [182.198.249.207]) by\n\teusmges2.samsung.com (EUCPMTA) with SMTP id 36.D4.12907.E26DFB95;\n\tMon, 18 Sep 2017 15:20:30 +0100 (BST)","from eusmgms2.samsung.com (unknown [182.198.249.180]) by\n\teucas1p2.samsung.com (KnoxPortal) with ESMTP id\n\t20170918142030eucas1p2a795b2a7918ca2273453b9aea1ce5d8b~lepTUpoPo1063410634eucas1p2f;\n\tMon, 18 Sep 2017 14:20:30 +0000 (GMT)","from eusync2.samsung.com ( [203.254.199.212]) by\n\teusmgms2.samsung.com (EUCPMTA) with SMTP id 2B.70.20118.E26DFB95;\n\tMon, 18 Sep 2017 15:20:30 +0100 (BST)","from [106.116.147.122] by eusync2.samsung.com (Oracle\n\tCommunications Messaging Server 7.0.5.31.0 64bit (built May 5 2014))\n\twith ESMTPA id <0OWH00K54BU54D10@eusync2.samsung.com>;\n\tMon, 18 Sep 2017 15:20:29 +0100 (BST)"],"X-AuditID":"cbfec7f1-f793a6d00000326b-97-59bfd62e3dbe","MIME-version":"1.0","Content-type":"text/plain; charset=\"utf-8\"; format=\"flowed\"","Subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","To":"Felipe Balbi , Kishon Vijay Abraham I , \n\tlinux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org","Cc":"Marek Szyprowski ,\n\tBartlomiej Zolnierkiewicz ,\n\tKrzysztof Kozlowski , Kukjin Kim , \n\tRussell King ,\n\tMark Rutland , Rob Herring ,\n\tGreg Kroah-Hartman ","From":"Andrzej Pietrasiewicz ","Message-id":"<7d87727a-e65e-f25b-0cdc-fe6ff0b7bb90@samsung.com>","Date":"Mon, 18 Sep 2017 16:20:22 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","In-reply-to":"<87vakgmb24.fsf@linux.intel.com>","Content-language":"en-US","Content-transfer-encoding":"8bit","X-Brightmail-Tracker":["H4sIAAAAAAAAA02SbUhTURjHOffe7d6NJndT87QiaSFR4jQVuVhKgcUl+tAXK6UXh158yU3Z\n\tVckiNGViJjkd5RuauSY0FXWKC0rF+TIhbA5lTqVpqU2UUhu9KCQ5r4Hffs85/+f/nP/DIVCJ\n\tjScl0lU5jFqlyJTxhVjv6JYtRO4YSAgzuOVUV00HjxotWcKpl8MfeVSxvoNPVSyuodTEcjmf\n\tstk6ccq06OBRNbZ+hGpu0aCU5XkfoNqHP+GUYdqOUJq+YfyCD93W2AboSYcdpU3GJ3x6oKEN\n\tp7tfF9DPeoyAtjrNCO0xHb9GJArPpzCZ6XmMOjQ2SZg2NRecPXbivvnHCFoIZqVlQEBAMhKu\n\tTloBx4fhhKuDXwaEhIQ0AGh2beBc4QHQ4yzCygCx1/GtSMydtwDodPei3m4RKYZ/dC7MyygZ\n\tDb/uaHhelpArAM5WZnjZl7wJF3UNmLfZj7QB2NjyE/UWKGlHoGWsdu8dfDIC9g2WAs41Fg5V\n\tdO45YWQQ1K1v873sv+s0YdpCvCwgQ6C76TvgJgfAYs3M/isC4eCUe28aJJtxWO204FyEOLix\n\tnctl9oWr1h6c42NwUvd0X68DsHNmY78wA9g+OsbjVOfgkNXO4yb4wKreapQzFcHSEgknoeFj\n\tt3FffhGWr7swbl/dKJzX/UW0ILDuwMrqDqys7kCIugMhmgBmBH5MLqtMZdhwOatQsrmqVHly\n\tltIEdr/Zhx3r5luwPhZtASQBZIdEXWv9CRKeIo/NV1oAJFCZn8jXNpAgEaUo8h8w6qy76txM\n\thrWAowQmCxDFJJYkSMhURQ5zj2GyGfX/W4QQSAuB/l34qfEFKp7vkUf8urTWrE2Kq2hiPyOC\n\t+tvJWfP1La03ipIMLhdmmn5YOx73JQaRnp6tfDUVCfRdiCaoQLzp/+LK9d8hYlHYER/RiCvy\n\tzftHutgoCgWqjELtSkEork6vCp8xngyMcrbeGYzXr91aWM7WOrLtc8KlyzFXg2UYm6Y4ewZV\n\ts4p/4+QQaGIDAAA=","H4sIAAAAAAAAA+NgFlrCIsWRmVeSWpSXmKPExsVy+t/xK7p61/ZHGqzvZrLYOGM9q8Wxtifs\n\tFvOPnGO1aF68ns2i//FrZosLT3vYLM6f38BusenxNVaLGef3MVksWtbKbHFo6l5Gi7VH7rJb\n\tLL1+kcmide8Rdgc+jzXz1jB6XL52kdlj06pONo/9c9ewe2xeUu/Rt2UVo8fxG9uZPD5vkgvg\n\tiOKySUnNySxLLdK3S+DKuHJbu+CEYsX2T0eZGxhvSXUxcnBICJhIvG0S7GLkBDLFJC7cW8/W\n\txcjFISSwhFFi8cY/7CAJXgFBiR+T77GA2MwCZhJfXh5mhSh6wShx5NdeJpCEsECExOPJc1lA\n\tEiIC5xklTt35BOYwC1xmknh0dCoLRMtGZokzE46BzWITMJbYe7CDEWKHncTh/g2sIDaLgKrE\n\t5Pe/2EDuEwUau2EjP0iYU0BX4vmCd4wQZ4hLNLfehDpJXuLglecsExgFZyG5dhaSa2chaZmF\n\tpGUBI8sqRpHU0uLc9NxiI73ixNzi0rx0veT83E2MwLjbduznlh2MXe+CDzEKcDAq8fBueL0v\n\tUog1say4MvcQowQHs5IIr/D5/ZFCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeXv3rI4UEkhPLEnN\n\tTk0tSC2CyTJxcEo1MO6dcEynV1/WZYvYnp75rFYuDufc7h6ftS9qvsY7dvvtuZfd027Nv2Eh\n\tE8Kimp0k/VBqskXYHn4bmZ8m5RPdGLOuHv7+Onxr2SbOo/UW/vGxtcY9OUcWOWQIs+d+sVcM\n\tDNgrf3SS0J/WI81/l+deMj9lJVay8viCW6YTz26cEpQU7RrMI7ZhqRJLcUaioRZzUXEiAD0o\n\t4hK3AgAA"],"X-CMS-MailID":"20170918142030eucas1p2a795b2a7918ca2273453b9aea1ce5d8b","X-Msg-Generator":"CA","X-Sender-IP":"182.198.249.180","X-Local-Sender":"=?utf-8?q?Andrzej_Pietrasiewicz=1BSRPOL-Kernel_=28TP=29?=\n\t=?utf-8?b?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?=","X-Global-Sender":"=?utf-8?q?Andrzej_Tomasz_Pietrasiewicz=1BSRPOL-Kernel_?=\n\t=?utf-8?q?=28TP=29=1BSamsung_Electronics=1BSenior_Software_Enginee?=\n\t=?utf-8?q?r?=","X-Sender-Code":"=?utf-8?q?C10=1BEHQ=1BC10CD02CD027392?=","CMS-TYPE":"201P","X-CMS-RootMailID":"20170918100944eucas1p2735d3d6a6ee562b927fb9dfaeb0d4090","X-RootMTR":"20170918100944eucas1p2735d3d6a6ee562b927fb9dfaeb0d4090","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505729371-6509-1-git-send-email-andrzej.p@samsung.com>\n\t<87y3pcmgv6.fsf@linux.intel.com>\n\t\n\t<96001441-2a67-ac9c-a606-eac66138d09e@samsung.com>\n\t<5c90f022-5cb1-c746-6015-c93a58805cfe@samsung.com>\n\t<87vakgmb24.fsf@linux.intel.com>","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1771233,"web_url":"http://patchwork.ozlabs.org/comment/1771233/","msgid":"<20170919174038.2sspjvadt6ggka65@kozik-lap>","list_archive_url":null,"date":"2017-09-19T17:40:38","subject":"Re: [PATCH 1/2] ARM: dts: exynos: Add dwc3 SUSPHY quirk","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On Mon, Sep 18, 2017 at 12:02:13PM +0200, Andrzej Pietrasiewicz wrote:\n> Odroid XU4 board does not enumerate SuperSpeed devices.\n> This patch makes exynos5 series chips use USB SUSPHY quirk,\n> which solves the problem.\n> \n> Signed-off-by: Andrzej Pietrasiewicz \n> ---\n> arch/arm/boot/dts/exynos54xx.dtsi | 2 ++\n> 1 file changed, 2 insertions(+)\n\nMakes sense to me... was it tested also on XU3 and XU?\n\nBest regards,\nKrzysztof\n\n> \n> diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi\n> index 0389e8a..8ca4fef 100644\n> --- a/arch/arm/boot/dts/exynos54xx.dtsi\n> +++ b/arch/arm/boot/dts/exynos54xx.dtsi\n> @@ -134,6 +134,7 @@\n> \t\t\t\tinterrupts = ;\n> \t\t\t\tphys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;\n> \t\t\t\tphy-names = \"usb2-phy\", \"usb3-phy\";\n> +\t\t\t\tsnps,dis_u3_susphy_quirk;\n> \t\t\t};\n> \t\t};\n> \n> @@ -154,6 +155,7 @@\n> \t\t\t\treg = <0x12400000 0x10000>;\n> \t\t\t\tphys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;\n> \t\t\t\tphy-names = \"usb2-phy\", \"usb3-phy\";\n> +\t\t\t\tsnps,dis_u3_susphy_quirk;\n> \t\t\t};\n> \t\t};\n> \n> -- \n> 1.9.1\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 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[84.226.254.92])\n\tby smtp.googlemail.com with ESMTPSA id\n\ta10sm6089915eda.37.2017.09.19.10.40.40\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tTue, 19 Sep 2017 10:40:40 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=zQVX9u3Ep0eoeoEmFxbCdLyAOlj81bSUd31wf4671bM=;\n\tb=fU4/sCA2cxwH7d/7tyQy55Wy2wZrieIJdqcn2Za7kO6yMTBtqgGsAkJ6t60fojg9AW\n\tsoBuKxzWZl7r946o1JpqMn1pnUzxS9sZfc/MQ1KTRAGqt9QjjpP9uqQGQEuoO3R0PS4V\n\tIqvRl6z+hPFwg7gltQOpPubLMLxY2KfZGOJ40A9N/66YbDdTIjG7LEaah3SE9vcsdhMj\n\tj5eRivv7veTBYm94HlrMgiCrlMJ/JdXkhiR5sWKBKGG/EXi8+KOl0oHiWyNnYvjhPMdJ\n\tE72ELxhdkzt6fTCPwTja6aLQTLQvz9A1tyWbEp6EUgpA7ngRTlFAiHQmyvTkd/MqoKU7\n\t4iNA==","X-Gm-Message-State":"AHPjjUj5SK4fBlOBGbiH9AOWY5AjDKQOj4+/v+ab0WY6Eb42o4svTRYe\n\t3Iyx9Fv1B4Gfre2i1gAC+5E=","X-Google-Smtp-Source":"AOwi7QCwtrBNQ5GF2FroQpSNrOfEqwW3oCl+NmVXQNHbays3k1HckhximvHsg8DdBGiAmGTJtsaMzQ==","X-Received":"by 10.80.146.35 with SMTP id i32mr2549126eda.10.1505842842176;\n\tTue, 19 Sep 2017 10:40:42 -0700 (PDT)","Date":"Tue, 19 Sep 2017 19:40:38 +0200","From":"Krzysztof Kozlowski ","To":"Andrzej Pietrasiewicz ","Cc":"linux-samsung-soc@vger.kernel.org, linux-usb@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,\n\tMarek Szyprowski ,\n\tBartlomiej Zolnierkiewicz ,\n\tKukjin Kim , Russell King , \n\tMark Rutland , Rob Herring ,\n\tKishon Vijay Abraham I , Felipe Balbi , \n\tGreg Kroah-Hartman ","Subject":"Re: [PATCH 1/2] ARM: dts: exynos: Add dwc3 SUSPHY quirk","Message-ID":"<20170919174038.2sspjvadt6ggka65@kozik-lap>","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505728934-6200-2-git-send-email-andrzej.p@samsung.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","In-Reply-To":"<1505728934-6200-2-git-send-email-andrzej.p@samsung.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1771266,"web_url":"http://patchwork.ozlabs.org/comment/1771266/","msgid":"","list_archive_url":null,"date":"2017-09-19T18:10:00","subject":"Re: [PATCH 1/2] ARM: dts: exynos: Add dwc3 SUSPHY quirk","submitter":{"id":65641,"url":"http://patchwork.ozlabs.org/api/people/65641/","name":"Robin Murphy","email":"robin.murphy@arm.com"},"content":"On 19/09/17 18:40, Krzysztof Kozlowski wrote:\n> On Mon, Sep 18, 2017 at 12:02:13PM +0200, Andrzej Pietrasiewicz wrote:\n>> Odroid XU4 board does not enumerate SuperSpeed devices.\n>> This patch makes exynos5 series chips use USB SUSPHY quirk,\n>> which solves the problem.\n>>\n>> Signed-off-by: Andrzej Pietrasiewicz \n>> ---\n>> arch/arm/boot/dts/exynos54xx.dtsi | 2 ++\n>> 1 file changed, 2 insertions(+)\n> \n> Makes sense to me... was it tested also on XU3 and XU?\n\nWell, it at least doesn't make USB3 on my XU any more or less broken\nthan it was before ;) (both ports still report an over-current condition\neven with nothing plugged in - I suspect there's probably still some\npinctrl/regulator stuff missing)\n\nRobin.\n\n> \n> Best regards,\n> Krzysztof\n> \n>>\n>> diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi\n>> index 0389e8a..8ca4fef 100644\n>> --- a/arch/arm/boot/dts/exynos54xx.dtsi\n>> +++ b/arch/arm/boot/dts/exynos54xx.dtsi\n>> @@ -134,6 +134,7 @@\n>> \t\t\t\tinterrupts = ;\n>> \t\t\t\tphys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;\n>> \t\t\t\tphy-names = \"usb2-phy\", \"usb3-phy\";\n>> +\t\t\t\tsnps,dis_u3_susphy_quirk;\n>> \t\t\t};\n>> \t\t};\n>> \n>> @@ -154,6 +155,7 @@\n>> \t\t\t\treg = <0x12400000 0x10000>;\n>> \t\t\t\tphys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;\n>> \t\t\t\tphy-names = \"usb2-phy\", \"usb3-phy\";\n>> +\t\t\t\tsnps,dis_u3_susphy_quirk;\n>> \t\t\t};\n>> \t\t};\n>> \n>> -- \n>> 1.9.1\n>>\n> \n> _______________________________________________\n> linux-arm-kernel mailing list\n> linux-arm-kernel@lists.infradead.org\n> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel\n> \n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxWBC36G8z9sPm\n\tfor ;\n\tWed, 20 Sep 2017 04:10:11 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751001AbdISSKJ (ORCPT\n\t);\n\tTue, 19 Sep 2017 14:10:09 -0400","from foss.arm.com ([217.140.101.70]:53714 \"EHLO foss.arm.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750919AbdISSKJ (ORCPT );\n\tTue, 19 Sep 2017 14:10:09 -0400","from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249])\n\tby usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B98171435;\n\tTue, 19 Sep 2017 11:10:08 -0700 (PDT)","from [10.1.210.88] (e110467-lin.cambridge.arm.com [10.1.210.88])\n\tby usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id\n\t4AEB13F483; Tue, 19 Sep 2017 11:10:06 -0700 (PDT)"],"Subject":"Re: [PATCH 1/2] ARM: dts: exynos: Add dwc3 SUSPHY quirk","To":"Krzysztof Kozlowski ,\n\tAndrzej Pietrasiewicz ","Cc":"Mark Rutland , devicetree@vger.kernel.org,\n\tlinux-samsung-soc@vger.kernel.org,\n\tBartlomiej Zolnierkiewicz ,\n\tGreg Kroah-Hartman ,\n\tlinux-usb@vger.kernel.org, Russell King ,\n\tRob Herring ,\n\tKishon Vijay Abraham I , \n\tKukjin Kim , Felipe Balbi ,\n\tlinux-arm-kernel@lists.infradead.org,\n\tMarek Szyprowski ","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505728934-6200-2-git-send-email-andrzej.p@samsung.com>\n\t<20170919174038.2sspjvadt6ggka65@kozik-lap>","From":"Robin Murphy ","Message-ID":"","Date":"Tue, 19 Sep 2017 19:10:00 +0100","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<20170919174038.2sspjvadt6ggka65@kozik-lap>","Content-Type":"text/plain; charset=utf-8","Content-Language":"en-US","Content-Transfer-Encoding":"7bit","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1772685,"web_url":"http://patchwork.ozlabs.org/comment/1772685/","msgid":"","list_archive_url":null,"date":"2017-09-21T11:07:52","subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","submitter":{"id":14965,"url":"http://patchwork.ozlabs.org/api/people/14965/","name":"Kishon Vijay Abraham I","email":"kishon@ti.com"},"content":"Hi,\n\nOn Monday 18 September 2017 07:50 PM, Andrzej Pietrasiewicz wrote:\n> Hi,\n> \n> W dniu 18.09.2017 o 14:43, Felipe Balbi pisze:\n>>\n>> Hi,\n>>\n>> Andrzej Pietrasiewicz writes:\n>>>>>>> +static int exynos5_usbdrd_phy_reset(struct phy *phy)\n>>>>>>> +{\n>>>>>>> + struct phy_usb_instance *inst = phy_get_drvdata(phy);\n>>>>>>> + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);\n>>>>>>> +\n>>>>>>> + return exynos5420_usbdrd_phy_calibrate(phy_drd);\n>>>>>>> +}\n>>>>>>> +\n>>>>>>> static const struct phy_ops exynos5_usbdrd_phy_ops = {\n>>>>>>> .init = exynos5_usbdrd_phy_init,\n>>>>>>> .exit = exynos5_usbdrd_phy_exit,\n>>>>>>> .power_on = exynos5_usbdrd_phy_power_on,\n>>>>>>> .power_off = exynos5_usbdrd_phy_power_off,\n>>>>>>> + .reset = exynos5_usbdrd_phy_reset,\n>>>>>>> .owner = THIS_MODULE,\n>>>>>>> };\n>>>>>>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c\n>>>>>>> index 03474d3..1d5836e 100644\n>>>>>>> --- a/drivers/usb/dwc3/core.c\n>>>>>>> +++ b/drivers/usb/dwc3/core.c\n>>>>>>> @@ -156,9 +156,10 @@ static void __dwc3_set_mode(struct work_struct *work)\n>>>>>>> } else {\n>>>>>>> if (dwc->usb2_phy)\n>>>>>>> otg_set_vbus(dwc->usb2_phy->otg, true);\n>>>>>>> - if (dwc->usb2_generic_phy)\n>>>>>>> + if (dwc->usb2_generic_phy) {\n>>>>>>> phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);\n>>>>>>> -\n>>>>>>> + phy_reset(dwc->usb2_generic_phy);\n>>>>>>\n>>>>>> it doesn't look like this is the best place to reset the phy. Also,\n>>>>>\n>>>>> right, phy_reset is done during initialization before\n>>>>> phy_power_on/phy_init or\n>>>>> in error cases.\n>>>>>\n>>>>>> ->reset() doesn't seem to match correctly with a calibration. That seems\n>>>>>> to be more fitting to a ->power_on() or ->init() implementation.\n>>>>>\n>>>>> yeah, the initial patch seems to calibrate in phy_init(). Not sure why it's\n>>>>> modified.\n>>>>\n>>>> The original patch used a hack like below, in xhci_plat_probe():\n>>>>\n>>>> + /* Initialize and power-on USB 3.0 PHY */\n>>>> + xhci->shared_hcd->phy->init_count = 0;\n>>>> + ret = phy_init(xhci->shared_hcd->phy);\n>>>> + if (ret)\n>>>> + goto dealloc_usb3_hcd;\n>>>> +\n>>>> + xhci->shared_hcd->phy->power_count = 0;\n>>>> + ret = phy_power_on(xhci->shared_hcd->phy);\n>>>> + if (ret) {\n>>>> + phy_exit(xhci->shared_hcd->phy);\n>>>> + goto dealloc_usb3_hcd;\n>>>> + }\n>>>> +\n>>>>\n>>>> Manually setting init_count to 0 in order for the subsequent phy_init() to\n>>>> happen probably does not look good.\n>>>>\n>>>> The calibration is clearly needed. However, I don't have any strong opinions\n>>>> on from which place exactly to trigger the calibration process.\n>>>> The original patch did not make it upstream, but if that patch is ok,\n>>>> it is perfectly fine with me to drop my version and take that one instead.\n>>>\n>>> Me bad, I did not write about an important issue.\n>>> The calibration must happen after usb_add_hcd(), otherwise\n>>> usb_add_hcd() indirectly triggers overwriting the effects of calibration.\n>>\n>> in that case, you should do that from xhci-plat indeed. I think the\n>> whole idea with init_count is just to make sure you don't initialize it\n>> twice.\n> \n> As far as I understand the code in question the desired result is exactly the\n> opposite:\n> to make sure it _does_ initialize twice, otherwise after the first\n> initialization the\n> calibration results were lost. In other words, in the code snippet above,\n> in xhci_plat_probe() the phy_init() was creatively (ab)used in order to force\n> the calibration at a desired moment, while in the original invocation of\n> phy_init()\n> the calibration result was merely a short-term side effect discarded soon\n> afterwards.\n> \n>>\n>> One thing's for sure, ->reset() doesn't seem to be the matching callback\n>> for you to use and, given your explanation above, dwc3 doesn't seem to\n>> be the right place to fiddle with that.\n>>\n>> Seems like we need an extension of the generic PHY framework to cope\n>> with your requirement.\n>>\n> \n> Here are old patches from Vivek:\n> \n> https://lkml.org/lkml/2014/9/2/166\n> \n> In particular:\n> \n> https://lkml.org/lkml/2014/9/2/170\n> \n> Please see the discussion that follows the latter.\n> \n> All in all, is adding the calibrate() method to phy_ops the way to go or not?\n\nAdding calibrate is fine but doing init() and power_on() in one driver and\ncalibrate() in another doesn't look correct. Why not let xhci do init() and\npower_on() of phy instead of dwc3?\n\nThanks\nKishon\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=ti.com header.i=@ti.com header.b=\"KssUi14B\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xyYkx13Tqz9ryk\n\tfor ;\n\tThu, 21 Sep 2017 21:08:41 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751726AbdIULIj (ORCPT\n\t);\n\tThu, 21 Sep 2017 07:08:39 -0400","from lelnx193.ext.ti.com ([198.47.27.77]:55537 \"EHLO\n\tlelnx193.ext.ti.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751661AbdIULIi (ORCPT\n\t); Thu, 21 Sep 2017 07:08:38 -0400","from dlelxv90.itg.ti.com ([172.17.2.17])\n\tby lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v8LB7vDq025558; \n\tThu, 21 Sep 2017 06:07:57 -0500","from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25])\n\tby dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LB7vPd013867; \n\tThu, 21 Sep 2017 06:07:57 -0500","from DFLE112.ent.ti.com (10.64.6.33) by DFLE104.ent.ti.com\n\t(10.64.6.25) with Microsoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.1.845.34;\n\tThu, 21 Sep 2017 06:07:57 -0500","from dlep33.itg.ti.com (157.170.170.75) by DFLE112.ent.ti.com\n\t(10.64.6.33) with Microsoft SMTP Server (version=TLS1_0,\n\tcipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.845.34 via Frontend\n\tTransport; Thu, 21 Sep 2017 06:07:57 -0500","from [172.24.190.233] (ileax41-snat.itg.ti.com [10.172.224.153])\n\tby dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id v8LB7rkJ020337;\n\tThu, 21 Sep 2017 06:07:53 -0500"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com;\n\ts=ti-com-17Q1; t=1505992077;\n\tbh=XscPAVxsafeGEK7qbSwijaDqpluoZEw18XgE6RKpW58=;\n\th=Subject:To:References:CC:From:Date:In-Reply-To;\n\tb=KssUi14B7eyiWPzJvegnx/6j3aV4Ra9KnJOCGIEUWlxLEQ7VRbY7ZolsDbYZgBlrO\n\t0Si3KKEBUU1ntqXjwD/Gtk4LttpIucoMlbPBbxjxxKMw+7Z6RFGFfKD0M6d++R9AYG\n\tvnNP9cXk0lo/tEEZVKB8+NVoUQO9iukcxT2KroO8=","Subject":"Re: [PATCH 2/2] phy: exynos5-usbdrd: Calibrate LOS levels for\n\texynos5420/5800","To":"Andrzej Pietrasiewicz ,\n\tFelipe Balbi ,\n\t, ,\n\t, ","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505729371-6509-1-git-send-email-andrzej.p@samsung.com>\n\t<87y3pcmgv6.fsf@linux.intel.com>\n\t\n\t<96001441-2a67-ac9c-a606-eac66138d09e@samsung.com>\n\t<5c90f022-5cb1-c746-6015-c93a58805cfe@samsung.com>\n\t<87vakgmb24.fsf@linux.intel.com>\n\t<7d87727a-e65e-f25b-0cdc-fe6ff0b7bb90@samsung.com>","CC":"Marek Szyprowski ,\n\tBartlomiej Zolnierkiewicz ,\n\tKrzysztof Kozlowski , Kukjin Kim , \n\tRussell King ,\n\tMark Rutland , Rob Herring ,\n\tGreg Kroah-Hartman ","From":"Kishon Vijay Abraham I ","Message-ID":"","Date":"Thu, 21 Sep 2017 16:37:52 +0530","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.7.0","MIME-Version":"1.0","In-Reply-To":"<7d87727a-e65e-f25b-0cdc-fe6ff0b7bb90@samsung.com>","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"7bit","X-EXCLAIMER-MD-CONFIG":"e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1773353,"web_url":"http://patchwork.ozlabs.org/comment/1773353/","msgid":"<894725fe-595b-45dc-e567-41caf48a012b@samsung.com>","list_archive_url":null,"date":"2017-09-22T08:18:54","subject":"Re: [PATCH 1/2] ARM: dts: exynos: Add dwc3 SUSPHY quirk","submitter":{"id":9958,"url":"http://patchwork.ozlabs.org/api/people/9958/","name":"Andrzej Pietrasiewicz","email":"andrzej.p@samsung.com"},"content":"Hi,\n\nW dniu 19.09.2017 o 20:10, Robin Murphy pisze:\n> On 19/09/17 18:40, Krzysztof Kozlowski wrote:\n>> On Mon, Sep 18, 2017 at 12:02:13PM +0200, Andrzej Pietrasiewicz wrote:\n>>> Odroid XU4 board does not enumerate SuperSpeed devices.\n>>> This patch makes exynos5 series chips use USB SUSPHY quirk,\n>>> which solves the problem.\n>>>\n>>> Signed-off-by: Andrzej Pietrasiewicz \n>>> ---\n>>> arch/arm/boot/dts/exynos54xx.dtsi | 2 ++\n>>> 1 file changed, 2 insertions(+)\n>>\n>> Makes sense to me... was it tested also on XU3 and XU?\n> \n> Well, it at least doesn't make USB3 on my XU any more or less broken\n> than it was before ;) (both ports still report an over-current condition\n> even with nothing plugged in - I suspect there's probably still some\n> pinctrl/regulator stuff missing)\n> \n> Robin.\n> \nSimilar with XU3: nothing is any more or less broken with this patch\ncompared to the situation without the patch.\n\nAndrzej\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) 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[PATCH 1/2] ARM: dts: exynos: Add dwc3 SUSPHY quirk","submitter":{"id":68952,"url":"http://patchwork.ozlabs.org/api/people/68952/","name":"Krzysztof Kozlowski","email":"krzk@kernel.org"},"content":"On Fri, Sep 22, 2017 at 10:18:54AM +0200, Andrzej Pietrasiewicz wrote:\n> Hi,\n> \n> W dniu 19.09.2017 o 20:10, Robin Murphy pisze:\n> > On 19/09/17 18:40, Krzysztof Kozlowski wrote:\n> > > On Mon, Sep 18, 2017 at 12:02:13PM +0200, Andrzej Pietrasiewicz wrote:\n> > > > Odroid XU4 board does not enumerate SuperSpeed devices.\n> > > > This patch makes exynos5 series chips use USB SUSPHY quirk,\n> > > > which solves the problem.\n> > > > \n> > > > Signed-off-by: Andrzej Pietrasiewicz \n> > > > ---\n> > > > arch/arm/boot/dts/exynos54xx.dtsi | 2 ++\n> > > > 1 file changed, 2 insertions(+)\n> > > \n> > > Makes sense to me... was it tested also on XU3 and XU?\n> > \n> > Well, it at least doesn't make USB3 on my XU any more or less broken\n> > than it was before ;) (both ports still report an over-current condition\n> > even with nothing plugged in - I suspect there's probably still some\n> > pinctrl/regulator stuff missing)\n> > \n> > Robin.\n> > \n> Similar with XU3: nothing is any more or less broken with this patch\n> compared to the situation without the patch.\n\nOK, thanks, applied!\n\nBest regards,\nKrzysztof\n\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 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[84.226.254.92])\n\tby smtp.googlemail.com with ESMTPSA id\n\tr39sm6084495edr.95.2017.09.25.11.49.59\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tMon, 25 Sep 2017 11:50:00 -0700 (PDT)"],"X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:content-transfer-encoding\n\t:in-reply-to:user-agent;\n\tbh=zwLjLEJdUP/VaxFpnDg0aa1E7/K3PaYNzaWHzR8b5ZM=;\n\tb=oKL1qtdTZswWJVRt2tafEMdKvr1s49RgZHsbPIeR8tDLio7xhF6i43hzw41E//zLAb\n\tOK2dxbIATV7egB2ToUi3WfdqQYHfbPefYcQ8SXFj0qYlneu36Aiw3S3pbfnSewmuUAlK\n\tYjLazMISxJvdujy+HGGL/alJngrYW0AnJE7lTUAf/xyU8SNjgv4xSjEHeZBUW+JmvesM\n\t2S1FVixx0BodgwU0HQjCRYG8fwabpBR48zJeqYILTnbCM4Kk6hOxkEtUv6OZavcB1Ej7\n\t36Jnbet7psyZQmT61PqQd2SSJu69qjVQ2qZFoaKhbzUrNMRedyANb6pMH4ohfjiAY5MI\n\tM3Wg==","X-Gm-Message-State":"AHPjjUiKnTeZXt2HGKAFiky875DTGPsDjH/SZMfAU3LuP3EKYsASb2em\n\tWfbR9+vH9XIxq/fgrSzMCKs=","X-Google-Smtp-Source":"AOwi7QAoCfM0aZufJNh/WYj4It1S8YHn9ibqAP7dxdMz17Dvx4w3IlI5sLusraJtwtESS35oiIwtzw==","X-Received":"by 10.80.215.3 with SMTP id t3mr14997174edi.45.1506365401101;\n\tMon, 25 Sep 2017 11:50:01 -0700 (PDT)","Date":"Mon, 25 Sep 2017 20:49:58 +0200","From":"Krzysztof Kozlowski ","To":"Andrzej Pietrasiewicz ","Cc":"Robin Murphy , Mark Rutland ,\n\tdevicetree@vger.kernel.org, linux-samsung-soc@vger.kernel.org,\n\tBartlomiej Zolnierkiewicz ,\n\tGreg Kroah-Hartman ,\n\tlinux-usb@vger.kernel.org, Russell King ,\n\tRob Herring ,\n\tKishon Vijay Abraham I , \n\tKukjin Kim , Felipe Balbi ,\n\tlinux-arm-kernel@lists.infradead.org,\n\tMarek Szyprowski ","Subject":"Re: [PATCH 1/2] ARM: dts: exynos: Add dwc3 SUSPHY quirk","Message-ID":"<20170925184958.quneytvejne2pjyb@kozik-lap>","References":"<1505728934-6200-1-git-send-email-andrzej.p@samsung.com>\n\t\n\t<1505728934-6200-2-git-send-email-andrzej.p@samsung.com>\n\t<20170919174038.2sspjvadt6ggka65@kozik-lap>\n\t\n\t<894725fe-595b-45dc-e567-41caf48a012b@samsung.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Disposition":"inline","Content-Transfer-Encoding":"8BIT","In-Reply-To":"<894725fe-595b-45dc-e567-41caf48a012b@samsung.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]