[{"id":1774731,"web_url":"http://patchwork.ozlabs.org/comment/1774731/","msgid":"<33dbaf5d-f51a-c148-460b-9079a2696fb1@xs4all.nl>","list_archive_url":null,"date":"2017-09-25T13:24:13","subject":"Re: [PATCH v2 5/5] media: atmel-isc: Rework the format list","submitter":{"id":723,"url":"http://patchwork.ozlabs.org/api/people/723/","name":"Hans Verkuil","email":"hverkuil@xs4all.nl"},"content":"Hi Wenyou,\n\nOn 18/09/17 08:39, Wenyou Yang wrote:\n> To improve the readability of code, split the format array into two,\n> one for the format description, other for the register configuration.\n> Meanwhile, add the flag member to indicate the format can be achieved\n> from the sensor or be produced by the controller, and rename members\n> related to the register configuration.\n> \n> Also add more formats support: GREY, ARGB444, ARGB555 and ARGB32.\n> \n> Signed-off-by: Wenyou Yang \n\nThis looks better. Just a few comments, see below.\n\n> ---\n> \n> Changes in v2:\n> - Add the new patch to remove the unnecessary member from\n> isc_subdev_entity struct.\n> - Rebase on the patch set,\n> [PATCH 0/6] [media] Atmel: Adjustments for seven function implementations\n> https://www.mail-archive.com/linux-media@vger.kernel.org/msg118342.html\n> \n> drivers/media/platform/atmel/atmel-isc.c | 524 ++++++++++++++++++++++++-------\n> 1 file changed, 405 insertions(+), 119 deletions(-)\n> \n> diff --git a/drivers/media/platform/atmel/atmel-isc.c b/drivers/media/platform/atmel/atmel-isc.c\n> index 2d876903da71..90bd0b28a975 100644\n> --- a/drivers/media/platform/atmel/atmel-isc.c\n> +++ b/drivers/media/platform/atmel/atmel-isc.c\n> @@ -89,34 +89,56 @@ struct isc_subdev_entity {\n> \tstruct list_head list;\n> };\n> \n> +#define FMT_FLAG_FROM_SENSOR\t\tBIT(0)\n> +#define FMT_FLAG_FROM_CONTROLLER\tBIT(1)\n\nDocument the meaning of these flags.\n\n> +\n> /*\n> * struct isc_format - ISC media bus format information\n> * @fourcc:\t\tFourcc code for this format\n> * @mbus_code:\t\tV4L2 media bus format code.\n> + * flags:\t\tIndicate format from sensor or converted by controller\n> * @bpp:\t\tBits per pixel (when stored in memory)\n> - * @reg_bps:\t\treg value for bits per sample\n> *\t\t\t(when transferred over a bus)\n> - * @pipeline:\t\tpipeline switch\n> * @sd_support:\t\tSubdev supports this format\n> * @isc_support:\tISC can convert raw format to this format\n> */\n> +\n> struct isc_format {\n> \tu32\tfourcc;\n> \tu32\tmbus_code;\n> +\tu32\tflags;\n> \tu8\tbpp;\n> \n> -\tu32\treg_bps;\n> -\tu32\treg_bay_cfg;\n> -\tu32\treg_rlp_mode;\n> -\tu32\treg_dcfg_imode;\n> -\tu32\treg_dctrl_dview;\n> -\n> -\tu32\tpipeline;\n> -\n> \tbool\tsd_support;\n> \tbool\tisc_support;\n> };\n> \n> +/* Pipeline bitmap */\n> +#define WB_ENABLE\tBIT(0)\n> +#define CFA_ENABLE\tBIT(1)\n> +#define CC_ENABLE\tBIT(2)\n> +#define GAM_ENABLE\tBIT(3)\n> +#define GAM_BENABLE\tBIT(4)\n> +#define GAM_GENABLE\tBIT(5)\n> +#define GAM_RENABLE\tBIT(6)\n> +#define CSC_ENABLE\tBIT(7)\n> +#define CBC_ENABLE\tBIT(8)\n> +#define SUB422_ENABLE\tBIT(9)\n> +#define SUB420_ENABLE\tBIT(10)\n> +\n> +#define GAM_ENABLES\t(GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)\n> +\n> +struct fmt_config {\n> +\tu32\tfourcc;\n> +\n> +\tu32\tpfe_cfg0_bps;\n> +\tu32\tcfa_baycfg;\n> +\tu32\trlp_cfg_mode;\n> +\tu32\tdcfg_imode;\n> +\tu32\tdctrl_dview;\n> +\n> +\tu32\tbits_pipeline;\n> +};\n> \n> #define HIST_ENTRIES\t\t512\n> #define HIST_BAYER\t\t(ISC_HIS_CFG_MODE_B + 1)\n> @@ -181,80 +203,321 @@ struct isc_device {\n> \tstruct list_head\t\tsubdev_entities;\n> };\n> \n> -#define RAW_FMT_IND_START 0\n> -#define RAW_FMT_IND_END 11\n> -#define ISC_FMT_IND_START 12\n> -#define ISC_FMT_IND_END 14\n> -\n> -static struct isc_format isc_formats[] = {\n> -\t{ V4L2_PIX_FMT_SBGGR8, MEDIA_BUS_FMT_SBGGR8_1X8, 8,\n> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,\n> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_SGBRG8, MEDIA_BUS_FMT_SGBRG8_1X8, 8,\n> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT8,\n> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_SGRBG8, MEDIA_BUS_FMT_SGRBG8_1X8, 8,\n> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT8,\n> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_SRGGB8, MEDIA_BUS_FMT_SRGGB8_1X8, 8,\n> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT8,\n> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\n> -\t{ V4L2_PIX_FMT_SBGGR10, MEDIA_BUS_FMT_SBGGR10_1X10, 16,\n> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT10,\n> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_SGBRG10, MEDIA_BUS_FMT_SGBRG10_1X10, 16,\n> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT10,\n> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_SGRBG10, MEDIA_BUS_FMT_SGRBG10_1X10, 16,\n> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT10,\n> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_SRGGB10, MEDIA_BUS_FMT_SRGGB10_1X10, 16,\n> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT10,\n> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\n> -\t{ V4L2_PIX_FMT_SBGGR12, MEDIA_BUS_FMT_SBGGR12_1X12, 16,\n> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT12,\n> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_SGBRG12, MEDIA_BUS_FMT_SGBRG12_1X12, 16,\n> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT12,\n> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_SGRBG12, MEDIA_BUS_FMT_SGRBG12_1X12, 16,\n> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT12,\n> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_SRGGB12, MEDIA_BUS_FMT_SRGGB12_1X12, 16,\n> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT12,\n> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> -\n> -\t{ V4L2_PIX_FMT_YUV420, 0x0, 12,\n> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,\n> -\t ISC_DCFG_IMODE_YC420P, ISC_DCTRL_DVIEW_PLANAR, 0x7fb,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_YUV422P, 0x0, 16,\n> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,\n> -\t ISC_DCFG_IMODE_YC422P, ISC_DCTRL_DVIEW_PLANAR, 0x3fb,\n> -\t false, false },\n> -\t{ V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_RGB565_2X8_LE, 16,\n> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_RGB565,\n> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x7b,\n> -\t false, false },\n> -\n> -\t{ V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_YUYV8_2X8, 16,\n> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,\n> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n> -\t false, false },\n> +#define MAX_RAW_FMT_INDEX\t11\n\nDo you still need this? The FMT_FLAG_FROM_SENSOR already tells you if it\nis a raw format or not.\n\nAs far as I can tell you can drop this define.\n\nRegards,\n\n\tHans\n\n> +static struct isc_format formats_list[] = {\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR8_1X8,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 8,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG8_1X8,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 8,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG8_1X8,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 8,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB8_1X8,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 8,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR10_1X10,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG10_1X10,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG10_1X10,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB10_1X10,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR12_1X12,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG12_1X12,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG12_1X12,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB12_1X12,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV420,\n> +\t\t.mbus_code\t= 0x0,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n> +\t\t.bpp\t\t= 12,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV422P,\n> +\t\t.mbus_code\t= 0x0,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_Y8_1X8,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER |\n> +\t\t\t\t FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 8,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB444,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB555,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_RGB565_2X8_LE,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB32,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_ARGB8888_1X32,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n> +\t\t.bpp\t\t= 32,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n> +\t\t.mbus_code\t= MEDIA_BUS_FMT_YUYV8_2X8,\n> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER |\n> +\t\t\t\t FMT_FLAG_FROM_SENSOR,\n> +\t\t.bpp\t\t= 16,\n> +\t},\n> +};\n> +\n> +struct fmt_config fmt_configs_list[] = {\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT10,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT10,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT10,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT10,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT12,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT12,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT12,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT12,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0,\n> +\t},\n> +\t{\n> +\t\t.fourcc = V4L2_PIX_FMT_YUV420,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_YYCC,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_YC420P,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PLANAR,\n> +\t\t.bits_pipeline\t= SUB420_ENABLE | SUB422_ENABLE |\n> +\t\t\t\t CBC_ENABLE | CSC_ENABLE |\n> +\t\t\t\t GAM_ENABLES |\n> +\t\t\t\t CFA_ENABLE | WB_ENABLE,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV422P,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_YYCC,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_YC422P,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PLANAR,\n> +\t\t.bits_pipeline\t= SUB422_ENABLE |\n> +\t\t\t\t CBC_ENABLE | CSC_ENABLE |\n> +\t\t\t\t GAM_ENABLES |\n> +\t\t\t\t CFA_ENABLE | WB_ENABLE,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DATY8,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= CBC_ENABLE | CSC_ENABLE |\n> +\t\t\t\t GAM_ENABLES |\n> +\t\t\t\t CFA_ENABLE | WB_ENABLE,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB444,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_ARGB444,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= GAM_ENABLES | CFA_ENABLE | WB_ENABLE,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB555,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_ARGB555,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= GAM_ENABLES | CFA_ENABLE | WB_ENABLE,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_RGB565,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= GAM_ENABLES | CFA_ENABLE | WB_ENABLE,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB32,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_ARGB32,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED32,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= GAM_ENABLES | CFA_ENABLE | WB_ENABLE,\n> +\t},\n> +\t{\n> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n> +\t\t.bits_pipeline\t= 0x0\n> +\t},\n> };\n> \n> #define GAMMA_MAX\t2\n> @@ -616,11 +879,27 @@ static inline bool sensor_is_preferred(const struct isc_format *isc_fmt)\n> \t\t!isc_fmt->isc_support;\n> }\n> \n> +static struct fmt_config *get_fmt_config(u32 fourcc)\n> +{\n> +\tstruct fmt_config *config;\n> +\tint i;\n> +\n> +\tconfig = &fmt_configs_list[0];\n> +\tfor (i = 0; i < ARRAY_SIZE(fmt_configs_list); i++) {\n> +\t\tif (config->fourcc == fourcc)\n> +\t\t\treturn config;\n> +\n> +\t\tconfig++;\n> +\t}\n> +\treturn NULL;\n> +}\n> +\n> static void isc_start_dma(struct isc_device *isc)\n> {\n> \tstruct regmap *regmap = isc->regmap;\n> \tstruct v4l2_pix_format *pixfmt = &isc->fmt.fmt.pix;\n> \tu32 sizeimage = pixfmt->sizeimage;\n> +\tstruct fmt_config *config = get_fmt_config(isc->current_fmt->fourcc);\n> \tu32 dctrl_dview;\n> \tdma_addr_t addr0;\n> \n> @@ -643,7 +922,7 @@ static void isc_start_dma(struct isc_device *isc)\n> \tif (sensor_is_preferred(isc->current_fmt))\n> \t\tdctrl_dview = ISC_DCTRL_DVIEW_PACKED;\n> \telse\n> -\t\tdctrl_dview = isc->current_fmt->reg_dctrl_dview;\n> +\t\tdctrl_dview = config->dctrl_dview;\n> \n> \tregmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);\n> \tregmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);\n> @@ -653,6 +932,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)\n> {\n> \tstruct regmap *regmap = isc->regmap;\n> \tstruct isc_ctrls *ctrls = &isc->ctrls;\n> +\tstruct fmt_config *config = get_fmt_config(isc->raw_fmt->fourcc);\n> \tu32 val, bay_cfg;\n> \tconst u32 *gamma;\n> \tunsigned int i;\n> @@ -666,7 +946,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)\n> \tif (!pipeline)\n> \t\treturn;\n> \n> -\tbay_cfg = isc->raw_fmt->reg_bay_cfg;\n> +\tbay_cfg = config->cfa_baycfg;\n> \n> \tregmap_write(regmap, ISC_WB_CFG, bay_cfg);\n> \tregmap_write(regmap, ISC_WB_O_RGR, 0x0);\n> @@ -719,11 +999,13 @@ static void isc_set_histogram(struct isc_device *isc)\n> {\n> \tstruct regmap *regmap = isc->regmap;\n> \tstruct isc_ctrls *ctrls = &isc->ctrls;\n> +\tstruct fmt_config *config = get_fmt_config(isc->raw_fmt->fourcc);\n> \n> \tif (ctrls->awb && (ctrls->hist_stat != HIST_ENABLED)) {\n> -\t\tregmap_write(regmap, ISC_HIS_CFG, ISC_HIS_CFG_MODE_R |\n> -\t\t (isc->raw_fmt->reg_bay_cfg << ISC_HIS_CFG_BAYSEL_SHIFT) |\n> -\t\t ISC_HIS_CFG_RAR);\n> +\t\tregmap_write(regmap, ISC_HIS_CFG,\n> +\t\t\t ISC_HIS_CFG_MODE_R |\n> +\t\t\t (config->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT) |\n> +\t\t\t ISC_HIS_CFG_RAR);\n> \t\tregmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);\n> \t\tregmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);\n> \t\tctrls->hist_id = ISC_HIS_CFG_MODE_R;\n> @@ -740,8 +1022,10 @@ static void isc_set_histogram(struct isc_device *isc)\n> }\n> \n> static inline void isc_get_param(const struct isc_format *fmt,\n> -\t\t\t\t u32 *rlp_mode, u32 *dcfg)\n> +\t\t\t\t u32 *rlp_mode, u32 *dcfg)\n> {\n> +\tstruct fmt_config *config = get_fmt_config(fmt->fourcc);\n> +\n> \t*dcfg = ISC_DCFG_YMBSIZE_BEATS8;\n> \n> \tswitch (fmt->fourcc) {\n> @@ -753,8 +1037,8 @@ static inline void isc_get_param(const struct isc_format *fmt,\n> \tcase V4L2_PIX_FMT_SGBRG12:\n> \tcase V4L2_PIX_FMT_SGRBG12:\n> \tcase V4L2_PIX_FMT_SRGGB12:\n> -\t\t*rlp_mode = fmt->reg_rlp_mode;\n> -\t\t*dcfg |= fmt->reg_dcfg_imode;\n> +\t\t*rlp_mode = config->rlp_cfg_mode;\n> +\t\t*dcfg |= config->dcfg_imode;\n> \t\tbreak;\n> \tdefault:\n> \t\t*rlp_mode = ISC_RLP_CFG_MODE_DAT8;\n> @@ -767,20 +1051,22 @@ static int isc_configure(struct isc_device *isc)\n> {\n> \tstruct regmap *regmap = isc->regmap;\n> \tconst struct isc_format *current_fmt = isc->current_fmt;\n> +\tstruct fmt_config *curfmt_config = get_fmt_config(current_fmt->fourcc);\n> +\tstruct fmt_config *rawfmt_config = get_fmt_config(isc->raw_fmt->fourcc);\n> \tstruct isc_subdev_entity *subdev = isc->current_subdev;\n> \tu32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;\n> \n> \tif (sensor_is_preferred(current_fmt)) {\n> -\t\tpfe_cfg0 = current_fmt->reg_bps;\n> +\t\tpfe_cfg0 = curfmt_config->pfe_cfg0_bps;\n> \t\tpipeline = 0x0;\n> \t\tisc_get_param(current_fmt, &rlp_mode, &dcfg);\n> \t\tisc->ctrls.hist_stat = HIST_INIT;\n> \t} else {\n> -\t\tpfe_cfg0 = isc->raw_fmt->reg_bps;\n> -\t\tpipeline = current_fmt->pipeline;\n> -\t\trlp_mode = current_fmt->reg_rlp_mode;\n> -\t\tdcfg = current_fmt->reg_dcfg_imode | ISC_DCFG_YMBSIZE_BEATS8 |\n> -\t\t ISC_DCFG_CMBSIZE_BEATS8;\n> +\t\tpfe_cfg0 = rawfmt_config->pfe_cfg0_bps;\n> +\t\tpipeline = curfmt_config->bits_pipeline;\n> +\t\trlp_mode = curfmt_config->rlp_cfg_mode;\n> +\t\tdcfg = curfmt_config->dcfg_imode |\n> +\t\t ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n> \t}\n> \n> \tpfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;\n> @@ -1365,6 +1651,7 @@ static void isc_awb_work(struct work_struct *w)\n> \tstruct isc_device *isc =\n> \t\tcontainer_of(w, struct isc_device, awb_work);\n> \tstruct regmap *regmap = isc->regmap;\n> +\tstruct fmt_config *config = get_fmt_config(isc->raw_fmt->fourcc);\n> \tstruct isc_ctrls *ctrls = &isc->ctrls;\n> \tu32 hist_id = ctrls->hist_id;\n> \tu32 baysel;\n> @@ -1382,7 +1669,7 @@ static void isc_awb_work(struct work_struct *w)\n> \t}\n> \n> \tctrls->hist_id = hist_id;\n> -\tbaysel = isc->raw_fmt->reg_bay_cfg << ISC_HIS_CFG_BAYSEL_SHIFT;\n> +\tbaysel = config->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;\n> \n> \tpm_runtime_get_sync(isc->dev);\n> \n> @@ -1483,10 +1770,10 @@ static void isc_async_unbind(struct v4l2_async_notifier *notifier,\n> \n> static struct isc_format *find_format_by_code(unsigned int code, int *index)\n> {\n> -\tstruct isc_format *fmt = &isc_formats[0];\n> +\tstruct isc_format *fmt = &formats_list[0];\n> \tunsigned int i;\n> \n> -\tfor (i = 0; i < ARRAY_SIZE(isc_formats); i++) {\n> +\tfor (i = 0; i < ARRAY_SIZE(formats_list); i++) {\n> \t\tif (fmt->mbus_code == code) {\n> \t\t\t*index = i;\n> \t\t\treturn fmt;\n> @@ -1503,37 +1790,36 @@ static int isc_formats_init(struct isc_device *isc)\n> \tstruct isc_format *fmt;\n> \tstruct v4l2_subdev *subdev = isc->current_subdev->sd;\n> \tunsigned int num_fmts, i, j;\n> +\tu32 list_size = ARRAY_SIZE(formats_list);\n> \tstruct v4l2_subdev_mbus_code_enum mbus_code = {\n> \t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n> \t};\n> \n> -\tfmt = &isc_formats[0];\n> -\tfor (i = 0; i < ARRAY_SIZE(isc_formats); i++) {\n> -\t\tfmt->isc_support = false;\n> -\t\tfmt->sd_support = false;\n> -\n> -\t\tfmt++;\n> -\t}\n> -\n> \twhile (!v4l2_subdev_call(subdev, pad, enum_mbus_code,\n> \t NULL, &mbus_code)) {\n> \t\tmbus_code.index++;\n> +\n> \t\tfmt = find_format_by_code(mbus_code.code, &i);\n> -\t\tif (!fmt)\n> +\t\tif ((!fmt) || (!(fmt->flags & FMT_FLAG_FROM_SENSOR)))\n> \t\t\tcontinue;\n> \n> \t\tfmt->sd_support = true;\n> \n> -\t\tif (i <= RAW_FMT_IND_END) {\n> -\t\t\tfor (j = ISC_FMT_IND_START; j <= ISC_FMT_IND_END; j++)\n> -\t\t\t\tisc_formats[j].isc_support = true;\n> -\n> +\t\tif (i <= MAX_RAW_FMT_INDEX)\n> \t\t\tisc->raw_fmt = fmt;\n> -\t\t}\n> \t}\n> \n> -\tfmt = &isc_formats[0];\n> -\tfor (i = 0, num_fmts = 0; i < ARRAY_SIZE(isc_formats); i++) {\n> +\tfmt = &formats_list[0];\n> +\tfor (i = 0; i < list_size; i++) {\n> +\t\tif (fmt->flags & FMT_FLAG_FROM_CONTROLLER)\n> +\t\t\tfmt->isc_support = true;\n> +\n> +\t\tfmt++;\n> +\t}\n> +\n> +\tfmt = &formats_list[0];\n> +\tnum_fmts = 0;\n> +\tfor (i = 0; i < list_size; i++) {\n> \t\tif (fmt->isc_support || fmt->sd_support)\n> \t\t\tnum_fmts++;\n> \n> @@ -1550,8 +1836,8 @@ static int isc_formats_init(struct isc_device *isc)\n> \tif (!isc->user_formats)\n> \t\treturn -ENOMEM;\n> \n> -\tfmt = &isc_formats[0];\n> -\tfor (i = 0, j = 0; i < ARRAY_SIZE(isc_formats); i++) {\n> +\tfmt = &formats_list[0];\n> +\tfor (i = 0, j = 0; i < list_size; i++) {\n> \t\tif (fmt->isc_support || fmt->sd_support)\n> \t\t\tisc->user_formats[j++] = fmt;\n> \n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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bh=OSJ/4viDmbVYLWyn3gRY1A6bVK7cUVaM5a3M1Zuvik0=;\n\tb=cXL8fAbyY7KXIM\n\thAxnM3lqlzNH4vSmFwOx7VICn/XCNPg9BlcQHmwr0NP56Yz+tLg4NACcPyc90QRwcACqgnuygnCNk\n\tFlqQLhWUuWIvla/d9PZYlZjDvx7mC6kESYOGha50NxrNFZ5G3UfP1PDydCJuLoyuoOeZGqbRVclrx\n\tfCK1ppKxNpIRRB41o0Ro9hRnGwEuG0A92gi1Weq+ajmDizXz6UO4TJ+5LnJsrsx7SkIK4LiaeL4fg\n\tX0mL8bXoeQEmlmakZ3Qu+VsvoMCL3+FQJFMAY1K3sGV+H3KkYB6VY4oPjdpYMY8l6OYemloykdkhX\n\tW9C6CmBjDKA7Ff5zURZA==;","Subject":"Re: [PATCH v2 5/5] media: atmel-isc: Rework the format list","To":"Wenyou Yang ,\n\tMauro Carvalho Chehab ","References":"<20170918063925.6372-1-wenyou.yang@microchip.com>\n\t<20170918063925.6372-6-wenyou.yang@microchip.com>","From":"Hans Verkuil ","Message-ID":"<33dbaf5d-f51a-c148-460b-9079a2696fb1@xs4all.nl>","Date":"Mon, 25 Sep 2017 15:24:13 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101\n\tThunderbird/45.7.1","MIME-Version":"1.0","In-Reply-To":"<20170918063925.6372-6-wenyou.yang@microchip.com>","X-CMAE-Envelope":"MS4wfK8OmpSRm+hTZ7qmuEk6a4viW2DHBkqb6JD1FUkTCOckYJjJNBVu7miaklBdv4ToUPk8fJmxWxOMr94rLDOtl8ISwM47y5r2CTxihsINPl9cXfltT389\n\tr/uR+x0NvgHLButy3TsT9g4vgMpnWzVuftlWuZ4kPE3yGsEvI7FRnVZndx4Ffv5FoSctDhf0vBFrtFZaLixVmxKy7SL5yRAr1TFT3qivOLmjNMgJTIPdwVk2\n\tj4WqcNM0X2TOPXvru7lRpag+iWdiMiYtXDczO9sJXkHRsVPfCgD132ci+xFLksziB+8GqG8LjMPjjZXsco1y0XQv4uWHA9rxNXVasSuFchFrAxtaKHvT9xpB\n\tgSYrpgrggLgiVtfusqeZ/p1UEKRCsTv9ImHgyCqL/QRYqBSCeul7fDGik/5HmtZepT6CIbjA/5qTDGSwQ2iqexTVE8e71w==","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170925_062446_861432_75FAB458 ","X-CRM114-Status":"GOOD ( 16.82 )","X-Spam-Score":"-2.6 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.6 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [194.109.24.24 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4)\n\t[194.109.24.24 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Jonathan Corbet , linux-kernel@vger.kernel.org,\n\tSakari Ailus ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tLinux Media Mailing List ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776035,"web_url":"http://patchwork.ozlabs.org/comment/1776035/","msgid":"<2557b706-9786-0d81-08d5-b61547ddb3e1@Microchip.com>","list_archive_url":null,"date":"2017-09-27T05:15:25","subject":"Re: [PATCH v2 5/5] media: atmel-isc: Rework the format list","submitter":{"id":69532,"url":"http://patchwork.ozlabs.org/api/people/69532/","name":"Wenyou Yang","email":"Wenyou.Yang@microchip.com"},"content":"Hi Hans,\n\nThank  you very much for your review.\n\nOn 2017/9/25 21:24, Hans Verkuil wrote:\n> Hi Wenyou,\n>\n> On 18/09/17 08:39, Wenyou Yang wrote:\n>> To improve the readability of code, split the format array into two,\n>> one for the format description, other for the register configuration.\n>> Meanwhile, add the flag member to indicate the format can be achieved\n>> from the sensor or be produced by the controller, and rename members\n>> related to the register configuration.\n>>\n>> Also add more formats support: GREY, ARGB444, ARGB555 and ARGB32.\n>>\n>> Signed-off-by: Wenyou Yang \n> This looks better. Just a few comments, see below.\n>\n>> ---\n>>\n>> Changes in v2:\n>> - Add the new patch to remove the unnecessary member from\n>> isc_subdev_entity struct.\n>> - Rebase on the patch set,\n>> [PATCH 0/6] [media] Atmel: Adjustments for seven function implementations\n>> https://www.mail-archive.com/linux-media@vger.kernel.org/msg118342.html\n>>\n>> drivers/media/platform/atmel/atmel-isc.c | 524 ++++++++++++++++++++++++-------\n>> 1 file changed, 405 insertions(+), 119 deletions(-)\n>>\n>> diff --git a/drivers/media/platform/atmel/atmel-isc.c b/drivers/media/platform/atmel/atmel-isc.c\n>> index 2d876903da71..90bd0b28a975 100644\n>> --- a/drivers/media/platform/atmel/atmel-isc.c\n>> +++ b/drivers/media/platform/atmel/atmel-isc.c\n>> @@ -89,34 +89,56 @@ struct isc_subdev_entity {\n>> \tstruct list_head list;\n>> };\n>> \n>> +#define FMT_FLAG_FROM_SENSOR\t\tBIT(0)\n>> +#define FMT_FLAG_FROM_CONTROLLER\tBIT(1)\n> Document the meaning of these flags.\nWill add it in next version.\n>\n>> +\n>> /*\n>> * struct isc_format - ISC media bus format information\n>> * @fourcc:\t\tFourcc code for this format\n>> * @mbus_code:\t\tV4L2 media bus format code.\n>> + * flags:\t\tIndicate format from sensor or converted by controller\n>> * @bpp:\t\tBits per pixel (when stored in memory)\n>> - * @reg_bps:\t\treg value for bits per sample\n>> *\t\t\t(when transferred over a bus)\n>> - * @pipeline:\t\tpipeline switch\n>> * @sd_support:\t\tSubdev supports this format\n>> * @isc_support:\tISC can convert raw format to this format\n>> */\n>> +\n>> struct isc_format {\n>> \tu32\tfourcc;\n>> \tu32\tmbus_code;\n>> +\tu32\tflags;\n>> \tu8\tbpp;\n>> \n>> -\tu32\treg_bps;\n>> -\tu32\treg_bay_cfg;\n>> -\tu32\treg_rlp_mode;\n>> -\tu32\treg_dcfg_imode;\n>> -\tu32\treg_dctrl_dview;\n>> -\n>> -\tu32\tpipeline;\n>> -\n>> \tbool\tsd_support;\n>> \tbool\tisc_support;\n>> };\n>> \n>> +/* Pipeline bitmap */\n>> +#define WB_ENABLE\tBIT(0)\n>> +#define CFA_ENABLE\tBIT(1)\n>> +#define CC_ENABLE\tBIT(2)\n>> +#define GAM_ENABLE\tBIT(3)\n>> +#define GAM_BENABLE\tBIT(4)\n>> +#define GAM_GENABLE\tBIT(5)\n>> +#define GAM_RENABLE\tBIT(6)\n>> +#define CSC_ENABLE\tBIT(7)\n>> +#define CBC_ENABLE\tBIT(8)\n>> +#define SUB422_ENABLE\tBIT(9)\n>> +#define SUB420_ENABLE\tBIT(10)\n>> +\n>> +#define GAM_ENABLES\t(GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)\n>> +\n>> +struct fmt_config {\n>> +\tu32\tfourcc;\n>> +\n>> +\tu32\tpfe_cfg0_bps;\n>> +\tu32\tcfa_baycfg;\n>> +\tu32\trlp_cfg_mode;\n>> +\tu32\tdcfg_imode;\n>> +\tu32\tdctrl_dview;\n>> +\n>> +\tu32\tbits_pipeline;\n>> +};\n>> \n>> #define HIST_ENTRIES\t\t512\n>> #define HIST_BAYER\t\t(ISC_HIS_CFG_MODE_B + 1)\n>> @@ -181,80 +203,321 @@ struct isc_device {\n>> \tstruct list_head\t\tsubdev_entities;\n>> };\n>> \n>> -#define RAW_FMT_IND_START 0\n>> -#define RAW_FMT_IND_END 11\n>> -#define ISC_FMT_IND_START 12\n>> -#define ISC_FMT_IND_END 14\n>> -\n>> -static struct isc_format isc_formats[] = {\n>> -\t{ V4L2_PIX_FMT_SBGGR8, MEDIA_BUS_FMT_SBGGR8_1X8, 8,\n>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,\n>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_SGBRG8, MEDIA_BUS_FMT_SGBRG8_1X8, 8,\n>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT8,\n>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_SGRBG8, MEDIA_BUS_FMT_SGRBG8_1X8, 8,\n>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT8,\n>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_SRGGB8, MEDIA_BUS_FMT_SRGGB8_1X8, 8,\n>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT8,\n>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\n>> -\t{ V4L2_PIX_FMT_SBGGR10, MEDIA_BUS_FMT_SBGGR10_1X10, 16,\n>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT10,\n>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_SGBRG10, MEDIA_BUS_FMT_SGBRG10_1X10, 16,\n>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT10,\n>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_SGRBG10, MEDIA_BUS_FMT_SGRBG10_1X10, 16,\n>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT10,\n>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_SRGGB10, MEDIA_BUS_FMT_SRGGB10_1X10, 16,\n>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT10,\n>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\n>> -\t{ V4L2_PIX_FMT_SBGGR12, MEDIA_BUS_FMT_SBGGR12_1X12, 16,\n>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT12,\n>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_SGBRG12, MEDIA_BUS_FMT_SGBRG12_1X12, 16,\n>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT12,\n>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_SGRBG12, MEDIA_BUS_FMT_SGRBG12_1X12, 16,\n>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT12,\n>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_SRGGB12, MEDIA_BUS_FMT_SRGGB12_1X12, 16,\n>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT12,\n>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> -\n>> -\t{ V4L2_PIX_FMT_YUV420, 0x0, 12,\n>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,\n>> -\t ISC_DCFG_IMODE_YC420P, ISC_DCTRL_DVIEW_PLANAR, 0x7fb,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_YUV422P, 0x0, 16,\n>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,\n>> -\t ISC_DCFG_IMODE_YC422P, ISC_DCTRL_DVIEW_PLANAR, 0x3fb,\n>> -\t false, false },\n>> -\t{ V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_RGB565_2X8_LE, 16,\n>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_RGB565,\n>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x7b,\n>> -\t false, false },\n>> -\n>> -\t{ V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_YUYV8_2X8, 16,\n>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,\n>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>> -\t false, false },\n>> +#define MAX_RAW_FMT_INDEX\t11\n> Do you still need this? The FMT_FLAG_FROM_SENSOR already tells you if it\n> is a raw format or not.\n>\n> As far as I can tell you can drop this define.\nThe MAX_RAW_FMT_INDEX is used to get the raw format supported by the sensor.\nSome sensor provide more formats other than the raw format, so the \nFMT_FLAG_FROM_SENSOR is not enough.\n\n> Regards,\n>\n> \tHans\n\nBest Regards,\nWenyou Yang\n>> +static struct isc_format formats_list[] = {\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR8_1X8,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 8,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG8_1X8,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 8,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG8_1X8,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 8,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB8_1X8,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 8,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR10_1X10,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG10_1X10,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG10_1X10,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB10_1X10,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SBGGR12_1X12,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGBRG12_1X12,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SGRBG12_1X12,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_SRGGB12_1X12,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV420,\n>> +\t\t.mbus_code\t= 0x0,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n>> +\t\t.bpp\t\t= 12,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV422P,\n>> +\t\t.mbus_code\t= 0x0,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_Y8_1X8,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER |\n>> +\t\t\t\t FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 8,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB444,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB555,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_RGB565_2X8_LE,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB32,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_ARGB8888_1X32,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER,\n>> +\t\t.bpp\t\t= 32,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n>> +\t\t.mbus_code\t= MEDIA_BUS_FMT_YUYV8_2X8,\n>> +\t\t.flags\t\t= FMT_FLAG_FROM_CONTROLLER |\n>> +\t\t\t\t FMT_FLAG_FROM_SENSOR,\n>> +\t\t.bpp\t\t= 16,\n>> +\t},\n>> +};\n>> +\n>> +struct fmt_config fmt_configs_list[] = {\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR8,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG8,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG8,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB8,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR10,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT10,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG10,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT10,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG10,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT10,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB10,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TEN,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT10,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SBGGR12,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT12,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGBRG12,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GBGB,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT12,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SGRBG12,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_GRGR,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT12,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_SRGGB12,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFG_CFG0_BPS_TWELVE,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_RGRG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT12,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc = V4L2_PIX_FMT_YUV420,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_YYCC,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_YC420P,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PLANAR,\n>> +\t\t.bits_pipeline\t= SUB420_ENABLE | SUB422_ENABLE |\n>> +\t\t\t\t CBC_ENABLE | CSC_ENABLE |\n>> +\t\t\t\t GAM_ENABLES |\n>> +\t\t\t\t CFA_ENABLE | WB_ENABLE,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUV422P,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_YYCC,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_YC422P,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PLANAR,\n>> +\t\t.bits_pipeline\t= SUB422_ENABLE |\n>> +\t\t\t\t CBC_ENABLE | CSC_ENABLE |\n>> +\t\t\t\t GAM_ENABLES |\n>> +\t\t\t\t CFA_ENABLE | WB_ENABLE,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_GREY,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DATY8,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= CBC_ENABLE | CSC_ENABLE |\n>> +\t\t\t\t GAM_ENABLES |\n>> +\t\t\t\t CFA_ENABLE | WB_ENABLE,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB444,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_ARGB444,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= GAM_ENABLES | CFA_ENABLE | WB_ENABLE,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB555,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_ARGB555,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= GAM_ENABLES | CFA_ENABLE | WB_ENABLE,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_RGB565,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_RGB565,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED16,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= GAM_ENABLES | CFA_ENABLE | WB_ENABLE,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_ARGB32,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_ARGB32,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED32,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= GAM_ENABLES | CFA_ENABLE | WB_ENABLE,\n>> +\t},\n>> +\t{\n>> +\t\t.fourcc\t\t= V4L2_PIX_FMT_YUYV,\n>> +\t\t.pfe_cfg0_bps\t= ISC_PFE_CFG0_BPS_EIGHT,\n>> +\t\t.cfa_baycfg\t= ISC_BAY_CFG_BGBG,\n>> +\t\t.rlp_cfg_mode\t= ISC_RLP_CFG_MODE_DAT8,\n>> +\t\t.dcfg_imode\t= ISC_DCFG_IMODE_PACKED8,\n>> +\t\t.dctrl_dview\t= ISC_DCTRL_DVIEW_PACKED,\n>> +\t\t.bits_pipeline\t= 0x0\n>> +\t},\n>> };\n>> \n>> #define GAMMA_MAX\t2\n>> @@ -616,11 +879,27 @@ static inline bool sensor_is_preferred(const struct isc_format *isc_fmt)\n>> \t\t!isc_fmt->isc_support;\n>> }\n>> \n>> +static struct fmt_config *get_fmt_config(u32 fourcc)\n>> +{\n>> +\tstruct fmt_config *config;\n>> +\tint i;\n>> +\n>> +\tconfig = &fmt_configs_list[0];\n>> +\tfor (i = 0; i < ARRAY_SIZE(fmt_configs_list); i++) {\n>> +\t\tif (config->fourcc == fourcc)\n>> +\t\t\treturn config;\n>> +\n>> +\t\tconfig++;\n>> +\t}\n>> +\treturn NULL;\n>> +}\n>> +\n>> static void isc_start_dma(struct isc_device *isc)\n>> {\n>> \tstruct regmap *regmap = isc->regmap;\n>> \tstruct v4l2_pix_format *pixfmt = &isc->fmt.fmt.pix;\n>> \tu32 sizeimage = pixfmt->sizeimage;\n>> +\tstruct fmt_config *config = get_fmt_config(isc->current_fmt->fourcc);\n>> \tu32 dctrl_dview;\n>> \tdma_addr_t addr0;\n>> \n>> @@ -643,7 +922,7 @@ static void isc_start_dma(struct isc_device *isc)\n>> \tif (sensor_is_preferred(isc->current_fmt))\n>> \t\tdctrl_dview = ISC_DCTRL_DVIEW_PACKED;\n>> \telse\n>> -\t\tdctrl_dview = isc->current_fmt->reg_dctrl_dview;\n>> +\t\tdctrl_dview = config->dctrl_dview;\n>> \n>> \tregmap_write(regmap, ISC_DCTRL, dctrl_dview | ISC_DCTRL_IE_IS);\n>> \tregmap_write(regmap, ISC_CTRLEN, ISC_CTRL_CAPTURE);\n>> @@ -653,6 +932,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)\n>> {\n>> \tstruct regmap *regmap = isc->regmap;\n>> \tstruct isc_ctrls *ctrls = &isc->ctrls;\n>> +\tstruct fmt_config *config = get_fmt_config(isc->raw_fmt->fourcc);\n>> \tu32 val, bay_cfg;\n>> \tconst u32 *gamma;\n>> \tunsigned int i;\n>> @@ -666,7 +946,7 @@ static void isc_set_pipeline(struct isc_device *isc, u32 pipeline)\n>> \tif (!pipeline)\n>> \t\treturn;\n>> \n>> -\tbay_cfg = isc->raw_fmt->reg_bay_cfg;\n>> +\tbay_cfg = config->cfa_baycfg;\n>> \n>> \tregmap_write(regmap, ISC_WB_CFG, bay_cfg);\n>> \tregmap_write(regmap, ISC_WB_O_RGR, 0x0);\n>> @@ -719,11 +999,13 @@ static void isc_set_histogram(struct isc_device *isc)\n>> {\n>> \tstruct regmap *regmap = isc->regmap;\n>> \tstruct isc_ctrls *ctrls = &isc->ctrls;\n>> +\tstruct fmt_config *config = get_fmt_config(isc->raw_fmt->fourcc);\n>> \n>> \tif (ctrls->awb && (ctrls->hist_stat != HIST_ENABLED)) {\n>> -\t\tregmap_write(regmap, ISC_HIS_CFG, ISC_HIS_CFG_MODE_R |\n>> -\t\t (isc->raw_fmt->reg_bay_cfg << ISC_HIS_CFG_BAYSEL_SHIFT) |\n>> -\t\t ISC_HIS_CFG_RAR);\n>> +\t\tregmap_write(regmap, ISC_HIS_CFG,\n>> +\t\t\t ISC_HIS_CFG_MODE_R |\n>> +\t\t\t (config->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT) |\n>> +\t\t\t ISC_HIS_CFG_RAR);\n>> \t\tregmap_write(regmap, ISC_HIS_CTRL, ISC_HIS_CTRL_EN);\n>> \t\tregmap_write(regmap, ISC_INTEN, ISC_INT_HISDONE);\n>> \t\tctrls->hist_id = ISC_HIS_CFG_MODE_R;\n>> @@ -740,8 +1022,10 @@ static void isc_set_histogram(struct isc_device *isc)\n>> }\n>> \n>> static inline void isc_get_param(const struct isc_format *fmt,\n>> -\t\t\t\t u32 *rlp_mode, u32 *dcfg)\n>> +\t\t\t\t u32 *rlp_mode, u32 *dcfg)\n>> {\n>> +\tstruct fmt_config *config = get_fmt_config(fmt->fourcc);\n>> +\n>> \t*dcfg = ISC_DCFG_YMBSIZE_BEATS8;\n>> \n>> \tswitch (fmt->fourcc) {\n>> @@ -753,8 +1037,8 @@ static inline void isc_get_param(const struct isc_format *fmt,\n>> \tcase V4L2_PIX_FMT_SGBRG12:\n>> \tcase V4L2_PIX_FMT_SGRBG12:\n>> \tcase V4L2_PIX_FMT_SRGGB12:\n>> -\t\t*rlp_mode = fmt->reg_rlp_mode;\n>> -\t\t*dcfg |= fmt->reg_dcfg_imode;\n>> +\t\t*rlp_mode = config->rlp_cfg_mode;\n>> +\t\t*dcfg |= config->dcfg_imode;\n>> \t\tbreak;\n>> \tdefault:\n>> \t\t*rlp_mode = ISC_RLP_CFG_MODE_DAT8;\n>> @@ -767,20 +1051,22 @@ static int isc_configure(struct isc_device *isc)\n>> {\n>> \tstruct regmap *regmap = isc->regmap;\n>> \tconst struct isc_format *current_fmt = isc->current_fmt;\n>> +\tstruct fmt_config *curfmt_config = get_fmt_config(current_fmt->fourcc);\n>> +\tstruct fmt_config *rawfmt_config = get_fmt_config(isc->raw_fmt->fourcc);\n>> \tstruct isc_subdev_entity *subdev = isc->current_subdev;\n>> \tu32 pfe_cfg0, rlp_mode, dcfg, mask, pipeline;\n>> \n>> \tif (sensor_is_preferred(current_fmt)) {\n>> -\t\tpfe_cfg0 = current_fmt->reg_bps;\n>> +\t\tpfe_cfg0 = curfmt_config->pfe_cfg0_bps;\n>> \t\tpipeline = 0x0;\n>> \t\tisc_get_param(current_fmt, &rlp_mode, &dcfg);\n>> \t\tisc->ctrls.hist_stat = HIST_INIT;\n>> \t} else {\n>> -\t\tpfe_cfg0 = isc->raw_fmt->reg_bps;\n>> -\t\tpipeline = current_fmt->pipeline;\n>> -\t\trlp_mode = current_fmt->reg_rlp_mode;\n>> -\t\tdcfg = current_fmt->reg_dcfg_imode | ISC_DCFG_YMBSIZE_BEATS8 |\n>> -\t\t ISC_DCFG_CMBSIZE_BEATS8;\n>> +\t\tpfe_cfg0 = rawfmt_config->pfe_cfg0_bps;\n>> +\t\tpipeline = curfmt_config->bits_pipeline;\n>> +\t\trlp_mode = curfmt_config->rlp_cfg_mode;\n>> +\t\tdcfg = curfmt_config->dcfg_imode |\n>> +\t\t ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;\n>> \t}\n>> \n>> \tpfe_cfg0 |= subdev->pfe_cfg0 | ISC_PFE_CFG0_MODE_PROGRESSIVE;\n>> @@ -1365,6 +1651,7 @@ static void isc_awb_work(struct work_struct *w)\n>> \tstruct isc_device *isc =\n>> \t\tcontainer_of(w, struct isc_device, awb_work);\n>> \tstruct regmap *regmap = isc->regmap;\n>> +\tstruct fmt_config *config = get_fmt_config(isc->raw_fmt->fourcc);\n>> \tstruct isc_ctrls *ctrls = &isc->ctrls;\n>> \tu32 hist_id = ctrls->hist_id;\n>> \tu32 baysel;\n>> @@ -1382,7 +1669,7 @@ static void isc_awb_work(struct work_struct *w)\n>> \t}\n>> \n>> \tctrls->hist_id = hist_id;\n>> -\tbaysel = isc->raw_fmt->reg_bay_cfg << ISC_HIS_CFG_BAYSEL_SHIFT;\n>> +\tbaysel = config->cfa_baycfg << ISC_HIS_CFG_BAYSEL_SHIFT;\n>> \n>> \tpm_runtime_get_sync(isc->dev);\n>> \n>> @@ -1483,10 +1770,10 @@ static void isc_async_unbind(struct v4l2_async_notifier *notifier,\n>> \n>> static struct isc_format *find_format_by_code(unsigned int code, int *index)\n>> {\n>> -\tstruct isc_format *fmt = &isc_formats[0];\n>> +\tstruct isc_format *fmt = &formats_list[0];\n>> \tunsigned int i;\n>> \n>> -\tfor (i = 0; i < ARRAY_SIZE(isc_formats); i++) {\n>> +\tfor (i = 0; i < ARRAY_SIZE(formats_list); i++) {\n>> \t\tif (fmt->mbus_code == code) {\n>> \t\t\t*index = i;\n>> \t\t\treturn fmt;\n>> @@ -1503,37 +1790,36 @@ static int isc_formats_init(struct isc_device *isc)\n>> \tstruct isc_format *fmt;\n>> \tstruct v4l2_subdev *subdev = isc->current_subdev->sd;\n>> \tunsigned int num_fmts, i, j;\n>> +\tu32 list_size = ARRAY_SIZE(formats_list);\n>> \tstruct v4l2_subdev_mbus_code_enum mbus_code = {\n>> \t\t.which = V4L2_SUBDEV_FORMAT_ACTIVE,\n>> \t};\n>> \n>> -\tfmt = &isc_formats[0];\n>> -\tfor (i = 0; i < ARRAY_SIZE(isc_formats); i++) {\n>> -\t\tfmt->isc_support = false;\n>> -\t\tfmt->sd_support = false;\n>> -\n>> -\t\tfmt++;\n>> -\t}\n>> -\n>> \twhile (!v4l2_subdev_call(subdev, pad, enum_mbus_code,\n>> \t NULL, &mbus_code)) {\n>> \t\tmbus_code.index++;\n>> +\n>> \t\tfmt = find_format_by_code(mbus_code.code, &i);\n>> -\t\tif (!fmt)\n>> +\t\tif ((!fmt) || (!(fmt->flags & FMT_FLAG_FROM_SENSOR)))\n>> \t\t\tcontinue;\n>> \n>> \t\tfmt->sd_support = true;\n>> \n>> -\t\tif (i <= RAW_FMT_IND_END) {\n>> -\t\t\tfor (j = ISC_FMT_IND_START; j <= ISC_FMT_IND_END; j++)\n>> -\t\t\t\tisc_formats[j].isc_support = true;\n>> -\n>> +\t\tif (i <= MAX_RAW_FMT_INDEX)\n>> \t\t\tisc->raw_fmt = fmt;\n>> -\t\t}\n>> \t}\n>> \n>> -\tfmt = &isc_formats[0];\n>> -\tfor (i = 0, num_fmts = 0; i < ARRAY_SIZE(isc_formats); i++) {\n>> +\tfmt = &formats_list[0];\n>> +\tfor (i = 0; i < list_size; i++) {\n>> +\t\tif (fmt->flags & FMT_FLAG_FROM_CONTROLLER)\n>> +\t\t\tfmt->isc_support = true;\n>> +\n>> +\t\tfmt++;\n>> +\t}\n>> +\n>> +\tfmt = &formats_list[0];\n>> +\tnum_fmts = 0;\n>> +\tfor (i = 0; i < list_size; i++) {\n>> \t\tif (fmt->isc_support || fmt->sd_support)\n>> \t\t\tnum_fmts++;\n>> \n>> @@ -1550,8 +1836,8 @@ static int isc_formats_init(struct isc_device *isc)\n>> \tif (!isc->user_formats)\n>> \t\treturn -ENOMEM;\n>> \n>> -\tfmt = &isc_formats[0];\n>> -\tfor (i = 0, j = 0; i < ARRAY_SIZE(isc_formats); i++) {\n>> +\tfmt = &formats_list[0];\n>> +\tfor (i = 0, j = 0; i < list_size; i++) {\n>> \t\tif (fmt->isc_support || fmt->sd_support)\n>> \t\t\tisc->user_formats[j++] = fmt;\n>> \n>>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) 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h=Sender:Content-Type:\n\tContent-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive:\n\tList-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From:\n\tReferences:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date:\n\tResent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner;\n\tbh=qUhtDKVES1cEh3P7uK/xEBIEI7C4j8/Ib25IwQC1itE=;\n\tb=HKOhQvyroPaowpcbDMo7zW6EJ\n\tGcS5byjxVWvb4gxh6TyliNFHjm4kOPo6sbOOmLcARmIG4qydFx3JrrUt/8iXFrMjvIa8Sx9ZvMn0L\n\toLCtmH2kko+WeN34IxTLULWUEZrndlIuqcDTu+heGz7SDxkr6YCnXgI/2XVPyttc93TKaW7sUB6vX\n\t6e4G3E+SvSDCQzSLhgzTdae1DfRnpRuaeHihI+eIesXIBly63+Ak12eDjSMPS3MxrpTzL3aAHpyEg\n\tS4HIymFvT753ftbFb7mUW1LValAda8P8D3jBpHKnR95CnF14q+ATlClbbaJyUgWzWc8Outr7tRyC6\n\tIFYKX9flA==;","X-IronPort-AV":"E=Sophos;i=\"5.42,443,1500966000\"; d=\"scan'208\";a=\"7385690\"","Subject":"Re: [PATCH v2 5/5] media: atmel-isc: Rework the format list","To":"Hans Verkuil , Mauro Carvalho Chehab\n\t","References":"<20170918063925.6372-1-wenyou.yang@microchip.com>\n\t<20170918063925.6372-6-wenyou.yang@microchip.com>\n\t<33dbaf5d-f51a-c148-460b-9079a2696fb1@xs4all.nl>","From":"\"Yang, Wenyou\" ","Message-ID":"<2557b706-9786-0d81-08d5-b61547ddb3e1@Microchip.com>","Date":"Wed, 27 Sep 2017 13:15:25 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<33dbaf5d-f51a-c148-460b-9079a2696fb1@xs4all.nl>","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170926_221558_011209_EB7E5D2E ","X-CRM114-Status":"GOOD ( 16.66 )","X-Spam-Score":"-2.6 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.6 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [68.232.153.233 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Jonathan Corbet , linux-kernel@vger.kernel.org,\n\tSakari Ailus ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tLinux Media Mailing List ","Content-Transfer-Encoding":"quoted-printable","Content-Type":"text/plain; charset=\"windows-1252\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776081,"web_url":"http://patchwork.ozlabs.org/comment/1776081/","msgid":"<20170927071626.mok5h3ckisyipy53@valkosipuli.retiisi.org.uk>","list_archive_url":null,"date":"2017-09-27T07:16:26","subject":"Re: [PATCH v2 1/5] media: atmel_isc: Add spin lock for clock enable\n\tops","submitter":{"id":1593,"url":"http://patchwork.ozlabs.org/api/people/1593/","name":"Sakari Ailus","email":"sakari.ailus@iki.fi"},"content":"Hi Wenyou,\n\nOn subject:\n\ns/_/-/\n\nOn Mon, Sep 18, 2017 at 02:39:21PM +0800, Wenyou Yang wrote:\n> Add the spin lock for the clock enable and disable operations.\n> \n> Signed-off-by: Wenyou Yang \n> ---\n> \n> Changes in v2: None\n> \n> drivers/media/platform/atmel/atmel-isc.c | 14 +++++++++++++-\n> 1 file changed, 13 insertions(+), 1 deletion(-)\n> \n> diff --git a/drivers/media/platform/atmel/atmel-isc.c b/drivers/media/platform/atmel/atmel-isc.c\n> index 2f8e345d297e..78114193af4c 100644\n> --- a/drivers/media/platform/atmel/atmel-isc.c\n> +++ b/drivers/media/platform/atmel/atmel-isc.c\n> @@ -65,6 +65,7 @@ struct isc_clk {\n> \tstruct clk_hw hw;\n> \tstruct clk *clk;\n> \tstruct regmap *regmap;\n> +\tspinlock_t\t*lock;\n\nCan this work? I don't see lock being assigned anywhere. Did you mean\n\n\tspinlock_t\tlock;\n\n?\n\n> \tu8\t\tid;\n> \tu8\t\tparent_id;\n> \tu32\t\tdiv;\n> @@ -312,26 +313,37 @@ static int isc_clk_enable(struct clk_hw *hw)\n> \tstruct isc_clk *isc_clk = to_isc_clk(hw);\n> \tu32 id = isc_clk->id;\n> \tstruct regmap *regmap = isc_clk->regmap;\n> +\tunsigned long flags;\n> +\tunsigned int status;\n> \n> \tdev_dbg(isc_clk->dev, \"ISC CLK: %s, div = %d, parent id = %d\\n\",\n> \t\t__func__, isc_clk->div, isc_clk->parent_id);\n> \n> +\tspin_lock_irqsave(isc_clk->lock, flags);\n> \tregmap_update_bits(regmap, ISC_CLKCFG,\n> \t\t\t ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),\n> \t\t\t (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |\n> \t\t\t (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));\n> \n> \tregmap_write(regmap, ISC_CLKEN, ISC_CLK(id));\n> +\tspin_unlock_irqrestore(isc_clk->lock, flags);\n> \n> -\treturn 0;\n> +\tregmap_read(regmap, ISC_CLKSR, &status);\n> +\tif (status & ISC_CLK(id))\n> +\t\treturn 0;\n> +\telse\n> +\t\treturn -EINVAL;\n> }\n> \n> static void isc_clk_disable(struct clk_hw *hw)\n> {\n> \tstruct isc_clk *isc_clk = to_isc_clk(hw);\n> \tu32 id = isc_clk->id;\n> +\tunsigned long flags;\n> \n> +\tspin_lock_irqsave(isc_clk->lock, flags);\n> \tregmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));\n> +\tspin_unlock_irqrestore(isc_clk->lock, flags);\n> }\n> \n> static int isc_clk_is_enabled(struct clk_hw *hw)","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Wed, 27 Sep 2017 10:16:27 +0300"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=dSK7YzX01WMNr77lHnyeNJi8/oYyU9G/41qnmxDk2dE=;\n\tb=ZbX0qexjXAl/kR\n\tiYVDe8ZMVDQJDNjWWCU75hshA+1xLA+LzmwTj15kJjf0zoyhWhDcaZufAOLoUFvDpVXpZioM4yYZB\n\t5cI89go2mqAb1y46jeJ7ZWipdnHaCSBLP9fdgBJ2WASA6lC/TjvqSIlvcM4WtORSZf3IksdDd/I3u\n\tTqigJUnw3ciaEkQTIyg/wZxHbXjCP+dTEkdsLImmUWAarqKtkPo0DwBhEV1HP4VFd+h8RGTT3/pbo\n\tK2bNcdK8HL/nIyVdU4xdC6zfWP2oKXYqND8+R5AaUS1JfRD3wD2SYbCkc60T5Nw+PXZ1BPeg8PWCo\n\tIuIVrpobTicA513YUbmA==;","Date":"Wed, 27 Sep 2017 10:16:26 +0300","From":"Sakari Ailus ","To":"Wenyou Yang ","Subject":"Re: [PATCH v2 1/5] media: atmel_isc: Add spin lock for clock enable\n\tops","Message-ID":"<20170927071626.mok5h3ckisyipy53@valkosipuli.retiisi.org.uk>","References":"<20170918063925.6372-1-wenyou.yang@microchip.com>\n\t<20170918063925.6372-2-wenyou.yang@microchip.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170918063925.6372-2-wenyou.yang@microchip.com>","User-Agent":"NeoMutt/20170113 (1.7.2)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170927_001655_711542_A334EFB4 ","X-CRM114-Status":"GOOD ( 14.38 )","X-Spam-Score":"-1.9 (-)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t0.0 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level\n\tmail domains are different\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Hans Verkuil , Jonathan Corbet ,\n\tlinux-kernel@vger.kernel.org,\n\tMauro Carvalho Chehab , \n\tlinux-arm-kernel@lists.infradead.org,\n\tLinux Media Mailing List ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776115,"web_url":"http://patchwork.ozlabs.org/comment/1776115/","msgid":"","list_archive_url":null,"date":"2017-09-27T08:03:57","subject":"Re: [PATCH v2 5/5] media: atmel-isc: Rework the format list","submitter":{"id":723,"url":"http://patchwork.ozlabs.org/api/people/723/","name":"Hans Verkuil","email":"hverkuil@xs4all.nl"},"content":"On 09/27/2017 07:15 AM, Yang, Wenyou wrote:\n> Hi Hans,\n> \n> Thank  you very much for your review.\n> \n> On 2017/9/25 21:24, Hans Verkuil wrote:\n>> Hi Wenyou,\n>>\n>> On 18/09/17 08:39, Wenyou Yang wrote:\n>>> To improve the readability of code, split the format array into two,\n>>> one for the format description, other for the register configuration.\n>>> Meanwhile, add the flag member to indicate the format can be achieved\n>>> from the sensor or be produced by the controller, and rename members\n>>> related to the register configuration.\n>>>\n>>> Also add more formats support: GREY, ARGB444, ARGB555 and ARGB32.\n>>>\n>>> Signed-off-by: Wenyou Yang \n>> This looks better. Just a few comments, see below.\n>>\n>>> ---\n>>>\n>>> Changes in v2:\n>>> - Add the new patch to remove the unnecessary member from\n>>> isc_subdev_entity struct.\n>>> - Rebase on the patch set,\n>>> [PATCH 0/6] [media] Atmel: Adjustments for seven function implementations\n>>> https://www.mail-archive.com/linux-media@vger.kernel.org/msg118342.html\n>>>\n>>> drivers/media/platform/atmel/atmel-isc.c | 524 ++++++++++++++++++++++++-------\n>>> 1 file changed, 405 insertions(+), 119 deletions(-)\n>>>\n>>> diff --git a/drivers/media/platform/atmel/atmel-isc.c b/drivers/media/platform/atmel/atmel-isc.c\n>>> index 2d876903da71..90bd0b28a975 100644\n>>> --- a/drivers/media/platform/atmel/atmel-isc.c\n>>> +++ b/drivers/media/platform/atmel/atmel-isc.c\n>>> @@ -89,34 +89,56 @@ struct isc_subdev_entity {\n>>> \tstruct list_head list;\n>>> };\n>>> \n>>> +#define FMT_FLAG_FROM_SENSOR\t\tBIT(0)\n>>> +#define FMT_FLAG_FROM_CONTROLLER\tBIT(1)\n>> Document the meaning of these flags.\n> Will add it in next version.\n>>\n>>> +\n>>> /*\n>>> * struct isc_format - ISC media bus format information\n>>> * @fourcc:\t\tFourcc code for this format\n>>> * @mbus_code:\t\tV4L2 media bus format code.\n>>> + * flags:\t\tIndicate format from sensor or converted by controller\n>>> * @bpp:\t\tBits per pixel (when stored in memory)\n>>> - * @reg_bps:\t\treg value for bits per sample\n>>> *\t\t\t(when transferred over a bus)\n>>> - * @pipeline:\t\tpipeline switch\n>>> * @sd_support:\t\tSubdev supports this format\n>>> * @isc_support:\tISC can convert raw format to this format\n>>> */\n>>> +\n>>> struct isc_format {\n>>> \tu32\tfourcc;\n>>> \tu32\tmbus_code;\n>>> +\tu32\tflags;\n>>> \tu8\tbpp;\n>>> \n>>> -\tu32\treg_bps;\n>>> -\tu32\treg_bay_cfg;\n>>> -\tu32\treg_rlp_mode;\n>>> -\tu32\treg_dcfg_imode;\n>>> -\tu32\treg_dctrl_dview;\n>>> -\n>>> -\tu32\tpipeline;\n>>> -\n>>> \tbool\tsd_support;\n>>> \tbool\tisc_support;\n>>> };\n>>> \n>>> +/* Pipeline bitmap */\n>>> +#define WB_ENABLE\tBIT(0)\n>>> +#define CFA_ENABLE\tBIT(1)\n>>> +#define CC_ENABLE\tBIT(2)\n>>> +#define GAM_ENABLE\tBIT(3)\n>>> +#define GAM_BENABLE\tBIT(4)\n>>> +#define GAM_GENABLE\tBIT(5)\n>>> +#define GAM_RENABLE\tBIT(6)\n>>> +#define CSC_ENABLE\tBIT(7)\n>>> +#define CBC_ENABLE\tBIT(8)\n>>> +#define SUB422_ENABLE\tBIT(9)\n>>> +#define SUB420_ENABLE\tBIT(10)\n>>> +\n>>> +#define GAM_ENABLES\t(GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)\n>>> +\n>>> +struct fmt_config {\n>>> +\tu32\tfourcc;\n>>> +\n>>> +\tu32\tpfe_cfg0_bps;\n>>> +\tu32\tcfa_baycfg;\n>>> +\tu32\trlp_cfg_mode;\n>>> +\tu32\tdcfg_imode;\n>>> +\tu32\tdctrl_dview;\n>>> +\n>>> +\tu32\tbits_pipeline;\n>>> +};\n>>> \n>>> #define HIST_ENTRIES\t\t512\n>>> #define HIST_BAYER\t\t(ISC_HIS_CFG_MODE_B + 1)\n>>> @@ -181,80 +203,321 @@ struct isc_device {\n>>> \tstruct list_head\t\tsubdev_entities;\n>>> };\n>>> \n>>> -#define RAW_FMT_IND_START 0\n>>> -#define RAW_FMT_IND_END 11\n>>> -#define ISC_FMT_IND_START 12\n>>> -#define ISC_FMT_IND_END 14\n>>> -\n>>> -static struct isc_format isc_formats[] = {\n>>> -\t{ V4L2_PIX_FMT_SBGGR8, MEDIA_BUS_FMT_SBGGR8_1X8, 8,\n>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,\n>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_SGBRG8, MEDIA_BUS_FMT_SGBRG8_1X8, 8,\n>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT8,\n>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_SGRBG8, MEDIA_BUS_FMT_SGRBG8_1X8, 8,\n>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT8,\n>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_SRGGB8, MEDIA_BUS_FMT_SRGGB8_1X8, 8,\n>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT8,\n>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\n>>> -\t{ V4L2_PIX_FMT_SBGGR10, MEDIA_BUS_FMT_SBGGR10_1X10, 16,\n>>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT10,\n>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_SGBRG10, MEDIA_BUS_FMT_SGBRG10_1X10, 16,\n>>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT10,\n>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_SGRBG10, MEDIA_BUS_FMT_SGRBG10_1X10, 16,\n>>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT10,\n>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_SRGGB10, MEDIA_BUS_FMT_SRGGB10_1X10, 16,\n>>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT10,\n>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\n>>> -\t{ V4L2_PIX_FMT_SBGGR12, MEDIA_BUS_FMT_SBGGR12_1X12, 16,\n>>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT12,\n>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_SGBRG12, MEDIA_BUS_FMT_SGBRG12_1X12, 16,\n>>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT12,\n>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_SGRBG12, MEDIA_BUS_FMT_SGRBG12_1X12, 16,\n>>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT12,\n>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_SRGGB12, MEDIA_BUS_FMT_SRGGB12_1X12, 16,\n>>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT12,\n>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> -\n>>> -\t{ V4L2_PIX_FMT_YUV420, 0x0, 12,\n>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,\n>>> -\t ISC_DCFG_IMODE_YC420P, ISC_DCTRL_DVIEW_PLANAR, 0x7fb,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_YUV422P, 0x0, 16,\n>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,\n>>> -\t ISC_DCFG_IMODE_YC422P, ISC_DCTRL_DVIEW_PLANAR, 0x3fb,\n>>> -\t false, false },\n>>> -\t{ V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_RGB565_2X8_LE, 16,\n>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_RGB565,\n>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x7b,\n>>> -\t false, false },\n>>> -\n>>> -\t{ V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_YUYV8_2X8, 16,\n>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,\n>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>> -\t false, false },\n>>> +#define MAX_RAW_FMT_INDEX\t11\n>> Do you still need this? The FMT_FLAG_FROM_SENSOR already tells you if it\n>> is a raw format or not.\n>>\n>> As far as I can tell you can drop this define.\n> The MAX_RAW_FMT_INDEX is used to get the raw format supported by the sensor.\n> Some sensor provide more formats other than the raw format, so the \n> FMT_FLAG_FROM_SENSOR is not enough.\n\nSo, add a new flag. The problem with a define like that is that is easily\ncan get out-of-sync with the array. It's a fragile coding approach.\n\nRegards,\n\n\tHans","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"NF5rPWNt\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y29hg11Vmz9s7F\n\tfor ;\n\tWed, 27 Sep 2017 18:19:15 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dx7Yi-0001sQ-J8; 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Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<2557b706-9786-0d81-08d5-b61547ddb3e1@Microchip.com>","Content-Language":"en-US","X-CMAE-Envelope":"MS4wfIo1hDCIBKGiNZFav6yZWDFwT2q2Cau8bJ1nUfPrBcOD8S5LHBV/IZMBKrDQd7mTMb1c4cAXLi8gnkNEFOUJMxsRDvBcB1gSsz47ap8ACSXeaS61vREa\n\tjVxOOYdC/fqVtKEttZlipbvfFKA6cxoY61lTR04/aTMsi1HF7ZWCFtVJ3QTSiYDheYpLH0IOw5uV0KapiY7UZn1GUmApnRDyNJ5jFJcE/vBkbvZBevfUx88+\n\tkcc8ANGSVfnXJNQU6EvZ8hHki1Wf2CChZQZYmaqkJFgVrx43iGxy3kLyq7diGqMW4wjVUB2Jr7M3awdaz7zLyNXJQQBBMMuuch50ac7xIk0kWGFWbWAG069x\n\tUTW55SS6HbPOSlRdBZjg6cc19xtULT8QRc1xzK4Mf5w6Yb4m+K1S5X1/T7XcGlwN2ec7v0fL05xQjbTyFiGQthMw7k7z2sKxDDBnZfApmuAtmpO9RNUGZ1DB\n\tiD9Afl6gX3ggucskUb8LVHniQ7f8c31cWSSEF9ZH0EhEKxmQFL9+hQpZ60z5iBbRlVdVaezEzrg5+rkE","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170927_010430_057621_EB54570F ","X-CRM114-Status":"GOOD ( 17.57 )","X-Spam-Score":"-2.6 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.6 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [194.109.24.26 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[194.109.24.26 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Jonathan Corbet , linux-kernel@vger.kernel.org,\n\tSakari Ailus ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tLinux Media Mailing List ","Content-Type":"text/plain; charset=\"windows-1252\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776780,"web_url":"http://patchwork.ozlabs.org/comment/1776780/","msgid":"<38ec3518-556f-7d0c-932b-bb475de02c8b@Microchip.com>","list_archive_url":null,"date":"2017-09-28T05:32:42","subject":"Re: [PATCH v2 5/5] media: atmel-isc: Rework the format list","submitter":{"id":69532,"url":"http://patchwork.ozlabs.org/api/people/69532/","name":"Wenyou Yang","email":"Wenyou.Yang@microchip.com"},"content":"On 2017/9/27 16:03, Hans Verkuil wrote:\n> On 09/27/2017 07:15 AM, Yang, Wenyou wrote:\n>> Hi Hans,\n>>\n>> Thank  you very much for your review.\n>>\n>> On 2017/9/25 21:24, Hans Verkuil wrote:\n>>> Hi Wenyou,\n>>>\n>>> On 18/09/17 08:39, Wenyou Yang wrote:\n>>>> To improve the readability of code, split the format array into two,\n>>>> one for the format description, other for the register configuration.\n>>>> Meanwhile, add the flag member to indicate the format can be achieved\n>>>> from the sensor or be produced by the controller, and rename members\n>>>> related to the register configuration.\n>>>>\n>>>> Also add more formats support: GREY, ARGB444, ARGB555 and ARGB32.\n>>>>\n>>>> Signed-off-by: Wenyou Yang \n>>> This looks better. Just a few comments, see below.\n>>>\n>>>> ---\n>>>>\n>>>> Changes in v2:\n>>>> - Add the new patch to remove the unnecessary member from\n>>>> isc_subdev_entity struct.\n>>>> - Rebase on the patch set,\n>>>> [PATCH 0/6] [media] Atmel: Adjustments for seven function implementations\n>>>> https://www.mail-archive.com/linux-media@vger.kernel.org/msg118342.html\n>>>>\n>>>> drivers/media/platform/atmel/atmel-isc.c | 524 ++++++++++++++++++++++++-------\n>>>> 1 file changed, 405 insertions(+), 119 deletions(-)\n>>>>\n>>>> diff --git a/drivers/media/platform/atmel/atmel-isc.c b/drivers/media/platform/atmel/atmel-isc.c\n>>>> index 2d876903da71..90bd0b28a975 100644\n>>>> --- a/drivers/media/platform/atmel/atmel-isc.c\n>>>> +++ b/drivers/media/platform/atmel/atmel-isc.c\n>>>> @@ -89,34 +89,56 @@ struct isc_subdev_entity {\n>>>> \tstruct list_head list;\n>>>> };\n>>>> \n>>>> +#define FMT_FLAG_FROM_SENSOR\t\tBIT(0)\n>>>> +#define FMT_FLAG_FROM_CONTROLLER\tBIT(1)\n>>> Document the meaning of these flags.\n>> Will add it in next version.\n>>>> +\n>>>> /*\n>>>> * struct isc_format - ISC media bus format information\n>>>> * @fourcc:\t\tFourcc code for this format\n>>>> * @mbus_code:\t\tV4L2 media bus format code.\n>>>> + * flags:\t\tIndicate format from sensor or converted by controller\n>>>> * @bpp:\t\tBits per pixel (when stored in memory)\n>>>> - * @reg_bps:\t\treg value for bits per sample\n>>>> *\t\t\t(when transferred over a bus)\n>>>> - * @pipeline:\t\tpipeline switch\n>>>> * @sd_support:\t\tSubdev supports this format\n>>>> * @isc_support:\tISC can convert raw format to this format\n>>>> */\n>>>> +\n>>>> struct isc_format {\n>>>> \tu32\tfourcc;\n>>>> \tu32\tmbus_code;\n>>>> +\tu32\tflags;\n>>>> \tu8\tbpp;\n>>>> \n>>>> -\tu32\treg_bps;\n>>>> -\tu32\treg_bay_cfg;\n>>>> -\tu32\treg_rlp_mode;\n>>>> -\tu32\treg_dcfg_imode;\n>>>> -\tu32\treg_dctrl_dview;\n>>>> -\n>>>> -\tu32\tpipeline;\n>>>> -\n>>>> \tbool\tsd_support;\n>>>> \tbool\tisc_support;\n>>>> };\n>>>> \n>>>> +/* Pipeline bitmap */\n>>>> +#define WB_ENABLE\tBIT(0)\n>>>> +#define CFA_ENABLE\tBIT(1)\n>>>> +#define CC_ENABLE\tBIT(2)\n>>>> +#define GAM_ENABLE\tBIT(3)\n>>>> +#define GAM_BENABLE\tBIT(4)\n>>>> +#define GAM_GENABLE\tBIT(5)\n>>>> +#define GAM_RENABLE\tBIT(6)\n>>>> +#define CSC_ENABLE\tBIT(7)\n>>>> +#define CBC_ENABLE\tBIT(8)\n>>>> +#define SUB422_ENABLE\tBIT(9)\n>>>> +#define SUB420_ENABLE\tBIT(10)\n>>>> +\n>>>> +#define GAM_ENABLES\t(GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)\n>>>> +\n>>>> +struct fmt_config {\n>>>> +\tu32\tfourcc;\n>>>> +\n>>>> +\tu32\tpfe_cfg0_bps;\n>>>> +\tu32\tcfa_baycfg;\n>>>> +\tu32\trlp_cfg_mode;\n>>>> +\tu32\tdcfg_imode;\n>>>> +\tu32\tdctrl_dview;\n>>>> +\n>>>> +\tu32\tbits_pipeline;\n>>>> +};\n>>>> \n>>>> #define HIST_ENTRIES\t\t512\n>>>> #define HIST_BAYER\t\t(ISC_HIS_CFG_MODE_B + 1)\n>>>> @@ -181,80 +203,321 @@ struct isc_device {\n>>>> \tstruct list_head\t\tsubdev_entities;\n>>>> };\n>>>> \n>>>> -#define RAW_FMT_IND_START 0\n>>>> -#define RAW_FMT_IND_END 11\n>>>> -#define ISC_FMT_IND_START 12\n>>>> -#define ISC_FMT_IND_END 14\n>>>> -\n>>>> -static struct isc_format isc_formats[] = {\n>>>> -\t{ V4L2_PIX_FMT_SBGGR8, MEDIA_BUS_FMT_SBGGR8_1X8, 8,\n>>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,\n>>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_SGBRG8, MEDIA_BUS_FMT_SGBRG8_1X8, 8,\n>>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT8,\n>>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_SGRBG8, MEDIA_BUS_FMT_SGRBG8_1X8, 8,\n>>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT8,\n>>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_SRGGB8, MEDIA_BUS_FMT_SRGGB8_1X8, 8,\n>>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT8,\n>>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\n>>>> -\t{ V4L2_PIX_FMT_SBGGR10, MEDIA_BUS_FMT_SBGGR10_1X10, 16,\n>>>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT10,\n>>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_SGBRG10, MEDIA_BUS_FMT_SGBRG10_1X10, 16,\n>>>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT10,\n>>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_SGRBG10, MEDIA_BUS_FMT_SGRBG10_1X10, 16,\n>>>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT10,\n>>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_SRGGB10, MEDIA_BUS_FMT_SRGGB10_1X10, 16,\n>>>> -\t ISC_PFG_CFG0_BPS_TEN, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT10,\n>>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\n>>>> -\t{ V4L2_PIX_FMT_SBGGR12, MEDIA_BUS_FMT_SBGGR12_1X12, 16,\n>>>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT12,\n>>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_SGBRG12, MEDIA_BUS_FMT_SGBRG12_1X12, 16,\n>>>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GBGB, ISC_RLP_CFG_MODE_DAT12,\n>>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_SGRBG12, MEDIA_BUS_FMT_SGRBG12_1X12, 16,\n>>>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_GRGR, ISC_RLP_CFG_MODE_DAT12,\n>>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_SRGGB12, MEDIA_BUS_FMT_SRGGB12_1X12, 16,\n>>>> -\t ISC_PFG_CFG0_BPS_TWELVE, ISC_BAY_CFG_RGRG, ISC_RLP_CFG_MODE_DAT12,\n>>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> -\n>>>> -\t{ V4L2_PIX_FMT_YUV420, 0x0, 12,\n>>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,\n>>>> -\t ISC_DCFG_IMODE_YC420P, ISC_DCTRL_DVIEW_PLANAR, 0x7fb,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_YUV422P, 0x0, 16,\n>>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_YYCC,\n>>>> -\t ISC_DCFG_IMODE_YC422P, ISC_DCTRL_DVIEW_PLANAR, 0x3fb,\n>>>> -\t false, false },\n>>>> -\t{ V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_RGB565_2X8_LE, 16,\n>>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_RGB565,\n>>>> -\t ISC_DCFG_IMODE_PACKED16, ISC_DCTRL_DVIEW_PACKED, 0x7b,\n>>>> -\t false, false },\n>>>> -\n>>>> -\t{ V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_YUYV8_2X8, 16,\n>>>> -\t ISC_PFE_CFG0_BPS_EIGHT, ISC_BAY_CFG_BGBG, ISC_RLP_CFG_MODE_DAT8,\n>>>> -\t ISC_DCFG_IMODE_PACKED8, ISC_DCTRL_DVIEW_PACKED, 0x0,\n>>>> -\t false, false },\n>>>> +#define MAX_RAW_FMT_INDEX\t11\n>>> Do you still need this? The FMT_FLAG_FROM_SENSOR already tells you if it\n>>> is a raw format or not.\n>>>\n>>> As far as I can tell you can drop this define.\n>> The MAX_RAW_FMT_INDEX is used to get the raw format supported by the sensor.\n>> Some sensor provide more formats other than the raw format, so the\n>> FMT_FLAG_FROM_SENSOR is not enough.\n> So, add a new flag. The problem with a define like that is that is easily\n> can get out-of-sync with the array. It's a fragile coding approach.\nYes, adding a new flag is better.\nThanks.\n\nBest Regards,\nWenyou Yang","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"p93pH74X\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y2jyq4W0Sz9t5C\n\tfor ;\n\tThu, 28 Sep 2017 15:33:23 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dxRRj-0006D8-Nh; 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d=\"scan'208\";a=\"7430138\"","Subject":"Re: [PATCH v2 5/5] media: atmel-isc: Rework the format list","To":"Hans Verkuil , Mauro Carvalho Chehab\n\t","References":"<20170918063925.6372-1-wenyou.yang@microchip.com>\n\t<20170918063925.6372-6-wenyou.yang@microchip.com>\n\t<33dbaf5d-f51a-c148-460b-9079a2696fb1@xs4all.nl>\n\t<2557b706-9786-0d81-08d5-b61547ddb3e1@Microchip.com>\n\t","From":"\"Yang, Wenyou\" ","Message-ID":"<38ec3518-556f-7d0c-932b-bb475de02c8b@Microchip.com>","Date":"Thu, 28 Sep 2017 13:32:42 +0800","User-Agent":"Mozilla/5.0 (Windows NT 6.1; WOW64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"","Content-Language":"en-US","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170927_223311_422104_69991370 ","X-CRM114-Status":"GOOD ( 15.32 )","X-Spam-Score":"-2.6 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.6 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [68.232.153.233 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Jonathan Corbet , linux-kernel@vger.kernel.org,\n\tSakari Ailus ,\n\tlinux-arm-kernel@lists.infradead.org, \n\tLinux Media Mailing List ","Content-Transfer-Encoding":"quoted-printable","Content-Type":"text/plain; charset=\"windows-1252\"; Format=\"flowed\"","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1776789,"web_url":"http://patchwork.ozlabs.org/comment/1776789/","msgid":"","list_archive_url":null,"date":"2017-09-28T06:11:41","subject":"Re: [PATCH v2 1/5] media: atmel_isc: Add spin lock for clock enable\n\tops","submitter":{"id":69532,"url":"http://patchwork.ozlabs.org/api/people/69532/","name":"Wenyou Yang","email":"Wenyou.Yang@microchip.com"},"content":"Hi Sakari,\n\n\nOn 2017/9/27 15:16, Sakari Ailus wrote:\n> Hi Wenyou,\n>\n> On subject:\n>\n> s/_/-/\n>\n> On Mon, Sep 18, 2017 at 02:39:21PM +0800, Wenyou Yang wrote:\n>> Add the spin lock for the clock enable and disable operations.\n>>\n>> Signed-off-by: Wenyou Yang \n>> ---\n>>\n>> Changes in v2: None\n>>\n>> drivers/media/platform/atmel/atmel-isc.c | 14 +++++++++++++-\n>> 1 file changed, 13 insertions(+), 1 deletion(-)\n>>\n>> diff --git a/drivers/media/platform/atmel/atmel-isc.c b/drivers/media/platform/atmel/atmel-isc.c\n>> index 2f8e345d297e..78114193af4c 100644\n>> --- a/drivers/media/platform/atmel/atmel-isc.c\n>> +++ b/drivers/media/platform/atmel/atmel-isc.c\n>> @@ -65,6 +65,7 @@ struct isc_clk {\n>> \tstruct clk_hw hw;\n>> \tstruct clk *clk;\n>> \tstruct regmap *regmap;\n>> +\tspinlock_t\t*lock;\n> Can this work? I don't see lock being assigned anywhere. Did you mean\n>\n> \tspinlock_t\tlock;\n>\n> ?\nOoh. I made a mistake.\n\nThank you very much.\n>\n>> \tu8\t\tid;\n>> \tu8\t\tparent_id;\n>> \tu32\t\tdiv;\n>> @@ -312,26 +313,37 @@ static int isc_clk_enable(struct clk_hw *hw)\n>> \tstruct isc_clk *isc_clk = to_isc_clk(hw);\n>> \tu32 id = isc_clk->id;\n>> \tstruct regmap *regmap = isc_clk->regmap;\n>> +\tunsigned long flags;\n>> +\tunsigned int status;\n>> \n>> \tdev_dbg(isc_clk->dev, \"ISC CLK: %s, div = %d, parent id = %d\\n\",\n>> \t\t__func__, isc_clk->div, isc_clk->parent_id);\n>> \n>> +\tspin_lock_irqsave(isc_clk->lock, flags);\n>> \tregmap_update_bits(regmap, ISC_CLKCFG,\n>> \t\t\t ISC_CLKCFG_DIV_MASK(id) | ISC_CLKCFG_SEL_MASK(id),\n>> \t\t\t (isc_clk->div << ISC_CLKCFG_DIV_SHIFT(id)) |\n>> \t\t\t (isc_clk->parent_id << ISC_CLKCFG_SEL_SHIFT(id)));\n>> \n>> \tregmap_write(regmap, ISC_CLKEN, ISC_CLK(id));\n>> +\tspin_unlock_irqrestore(isc_clk->lock, flags);\n>> \n>> -\treturn 0;\n>> +\tregmap_read(regmap, ISC_CLKSR, &status);\n>> +\tif (status & ISC_CLK(id))\n>> +\t\treturn 0;\n>> +\telse\n>> +\t\treturn -EINVAL;\n>> }\n>> \n>> static void isc_clk_disable(struct clk_hw *hw)\n>> {\n>> \tstruct isc_clk *isc_clk = to_isc_clk(hw);\n>> \tu32 id = isc_clk->id;\n>> +\tunsigned long flags;\n>> \n>> +\tspin_lock_irqsave(isc_clk->lock, flags);\n>> \tregmap_write(isc_clk->regmap, ISC_CLKDIS, ISC_CLK(id));\n>> +\tspin_unlock_irqrestore(isc_clk->lock, flags);\n>> }\n>> \n>> static int isc_clk_is_enabled(struct clk_hw *hw)\nBest Regards,\nWenyou Yang","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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