[{"id":1778008,"web_url":"http://patchwork.ozlabs.org/comment/1778008/","msgid":"","list_archive_url":null,"date":"2017-10-01T12:19:11","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"content":"Hello Russel, Hi Kevin,\n\nOn Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n wrote:\n> This patchset adds support for booting the secondary CPU cores (and\n> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n> It is based on an earlier version from Carlo Caione - this helped me\n> a lot to get a better understanding of how SMP/CPU hotplug works\n> (compared to the code found in Amlogic's GPL kernel sources from\n> year 2015).\n>\n> Changes since v6 from [6]:\n> - rebased on top of v4.14-rc1 (which only corrected some line\n> numbers in the SCU patches)\nit's been two weeks since v6 and since then Linus Lüssing has\nconfirmed that this works fine on his Odroid-C1 as well (many thanks\nfor testing!): [7]\n\n> Changes since v5 from [5]:\n> - dropped dependency on another patch series (for the clock\n> controller's embedded reset controller, which is needed to boot\n> the secondary CPUs) from the cover-letter as that series is now\n> merged\n> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n> Russell King for spotting these). removed the paragraph about\n> preemption, cache coherency and interrupts as we're powering on\n> a CPU core (the text was copied from the original scu_power_mode\n> but simply not adjusted). also changed \"Set the executing CPUs\"\n> to \"Set the given (logical) CPU's\" as we're not modifying the\n> current CPU. this affects only patch #2\n> - extended the commit message of patch #3 with a short sentence\n> about why SCU_CPU_STATUS_MASK was introduced\n>\n> Changes since v4 from [4]:\n> - use __pa_symbol(secondary_startup) instead of\n> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n> (affects patch #4)\n> - (cover-letter) removed dependency on my other patch\n> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n> was merged into Kevin's Amlogic repo today\n> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n> lines\") again because the reset controller series exposes the\n> preprocessor macros now directly, see [1]\n> - refreshed the .dts patches so they now include the new header for\n> the reset line preprocessor macros\n>\n> Changes since v3 from [3]:\n> - added Rob's ACK to patch #1\n> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n> - removed all \"pen\" code from patch #4 as that code was not needed\n> at all (it was left-over while trying to fix Meson8 secondary CPU\n> boot - which turned out to have nothing to do with this \"pen\" code)\n> - removed all memory barrier operations as they were added based on\n> the code in the Amlogic GPL kernel tree (while trying to fix the\n> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n> still works fine with these on my Meson8m2 and Meson8b boards.\n> - added PATCH #5 as we now have to export the reset identifiers\n> (just like we do it with the clock identifiers / preprocessor\n> macros) - this is the result of a change in the reset controller\n> patch in version 2, see [1]\n> - use the reset line preprocessor macros (from patch #5) in patches\n> #6 and #7\n>\n> Changes since v2 from [0]:\n> - added support for Meson8 (which requires a slightly different\n> enable-method)\n> - implemented CPU hotplug support which allows taking a CPU core\n> offline for both, Meson8 and Meson8b\n> - add a function to smp_scu.c which allows enabling a CPU core from\n> a different CPU (previously only the power mode for the current CPU\n> could be changed). Without this the CPU cores on Meson8 won't come\n> up (Amlogic's vendor GPL kernel sources also enable power through\n> SCU as very first step for Meson8b as well)\n> - add a function to smp_scu.c to get the power status of a CPU core\n> (which is needed because the code in .cpu_kill needs to wait until\n> the core is actually powered off)\n> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n> as it is already applied (for both, Meson8 and Meson8b)\n> - dropped the patches which implement the reset controller which is\n> built into the clock-controller, these are a separate series: [1]\n> - moved the enable-method property to each CPU node\n>\n>\n> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n>\n> Carlo Caione (2):\n> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n> ARM: dts: meson8b: add support for booting the secondary CPU cores\n>\n> Martin Blumenstingl (4):\n> ARM: smp_scu: add a helper for powering on a specific CPU\n> ARM: smp_scu: allow the platform code to read the SCU CPU status\n> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n> ARM: dts: meson8: add support for booting the secondary CPU cores\n@Russel: should Kevin take all patches including the two smp_scu ones?\nor do you want to take them through your own tree?\n\n> .../devicetree/bindings/arm/amlogic/pmu.txt | 18 +\n> .../devicetree/bindings/arm/amlogic/smp-sram.txt | 32 ++\n> Documentation/devicetree/bindings/arm/cpus.txt | 2 +\n> arch/arm/Makefile | 1 +\n> arch/arm/boot/dts/meson8.dtsi | 21 +\n> arch/arm/boot/dts/meson8b.dtsi | 21 +\n> arch/arm/include/asm/smp_scu.h | 12 +\n> arch/arm/kernel/smp_scu.c | 43 +-\n> arch/arm/mach-meson/Kconfig | 1 +\n> arch/arm/mach-meson/Makefile | 1 +\n> arch/arm/mach-meson/platsmp.c | 440 +++++++++++++++++++++\n> 11 files changed, 586 insertions(+), 6 deletions(-)\n> create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt\n> create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt\n> create mode 100644 arch/arm/mach-meson/platsmp.c\n>\n> --\n> 2.14.1\n>\n\nRegards,\nMartin\n\n\n[7] http://lists.infradead.org/pipermail/linux-amlogic/2017-September/004813.html","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1781903,"web_url":"http://patchwork.ozlabs.org/comment/1781903/","msgid":"<7hpoa07yn6.fsf@baylibre.com>","list_archive_url":null,"date":"2017-10-06T21:30:05","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":68189,"url":"http://patchwork.ozlabs.org/api/people/68189/","name":"Kevin Hilman","email":"khilman@baylibre.com"},"content":"Martin Blumenstingl writes:\n\n> Hello Russel, Hi Kevin,\n>\n> On Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n> wrote:\n>> This patchset adds support for booting the secondary CPU cores (and\n>> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n>> It is based on an earlier version from Carlo Caione - this helped me\n>> a lot to get a better understanding of how SMP/CPU hotplug works\n>> (compared to the code found in Amlogic's GPL kernel sources from\n>> year 2015).\n>>\n>> Changes since v6 from [6]:\n>> - rebased on top of v4.14-rc1 (which only corrected some line\n>> numbers in the SCU patches)\n> it's been two weeks since v6 and since then Linus Lüssing has\n> confirmed that this works fine on his Odroid-C1 as well (many thanks\n> for testing!): [7]\n>\n>> Changes since v5 from [5]:\n>> - dropped dependency on another patch series (for the clock\n>> controller's embedded reset controller, which is needed to boot\n>> the secondary CPUs) from the cover-letter as that series is now\n>> merged\n>> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n>> Russell King for spotting these). removed the paragraph about\n>> preemption, cache coherency and interrupts as we're powering on\n>> a CPU core (the text was copied from the original scu_power_mode\n>> but simply not adjusted). also changed \"Set the executing CPUs\"\n>> to \"Set the given (logical) CPU's\" as we're not modifying the\n>> current CPU. this affects only patch #2\n>> - extended the commit message of patch #3 with a short sentence\n>> about why SCU_CPU_STATUS_MASK was introduced\n>>\n>> Changes since v4 from [4]:\n>> - use __pa_symbol(secondary_startup) instead of\n>> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n>> (affects patch #4)\n>> - (cover-letter) removed dependency on my other patch\n>> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n>> was merged into Kevin's Amlogic repo today\n>> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n>> lines\") again because the reset controller series exposes the\n>> preprocessor macros now directly, see [1]\n>> - refreshed the .dts patches so they now include the new header for\n>> the reset line preprocessor macros\n>>\n>> Changes since v3 from [3]:\n>> - added Rob's ACK to patch #1\n>> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n>> - removed all \"pen\" code from patch #4 as that code was not needed\n>> at all (it was left-over while trying to fix Meson8 secondary CPU\n>> boot - which turned out to have nothing to do with this \"pen\" code)\n>> - removed all memory barrier operations as they were added based on\n>> the code in the Amlogic GPL kernel tree (while trying to fix the\n>> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n>> still works fine with these on my Meson8m2 and Meson8b boards.\n>> - added PATCH #5 as we now have to export the reset identifiers\n>> (just like we do it with the clock identifiers / preprocessor\n>> macros) - this is the result of a change in the reset controller\n>> patch in version 2, see [1]\n>> - use the reset line preprocessor macros (from patch #5) in patches\n>> #6 and #7\n>>\n>> Changes since v2 from [0]:\n>> - added support for Meson8 (which requires a slightly different\n>> enable-method)\n>> - implemented CPU hotplug support which allows taking a CPU core\n>> offline for both, Meson8 and Meson8b\n>> - add a function to smp_scu.c which allows enabling a CPU core from\n>> a different CPU (previously only the power mode for the current CPU\n>> could be changed). Without this the CPU cores on Meson8 won't come\n>> up (Amlogic's vendor GPL kernel sources also enable power through\n>> SCU as very first step for Meson8b as well)\n>> - add a function to smp_scu.c to get the power status of a CPU core\n>> (which is needed because the code in .cpu_kill needs to wait until\n>> the core is actually powered off)\n>> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n>> as it is already applied (for both, Meson8 and Meson8b)\n>> - dropped the patches which implement the reset controller which is\n>> built into the clock-controller, these are a separate series: [1]\n>> - moved the enable-method property to each CPU node\n>>\n>>\n>> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n>> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n>> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n>> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n>>\n>> Carlo Caione (2):\n>> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n>> ARM: dts: meson8b: add support for booting the secondary CPU cores\n>>\n>> Martin Blumenstingl (4):\n>> ARM: smp_scu: add a helper for powering on a specific CPU\n>> ARM: smp_scu: allow the platform code to read the SCU CPU status\n>> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n>> ARM: dts: meson8: add support for booting the secondary CPU cores\n> @Russel: should Kevin take all patches including the two smp_scu ones?\n> or do you want to take them through your own tree?\n\nWith Russell's ack, I can take the series via the amlogic tree. But I'm\nalso fine if Russell wants to take the arch/arm/* via his tree, and I\nwill just queue up the DT.\n\nKevin","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"NVpwM4ie\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=baylibre-com.20150623.gappssmtp.com\n\theader.i=@baylibre-com.20150623.gappssmtp.com header.b=\"UuG+uBLd\"; \n\tdkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3y82rh5FQcz9t2Z\n\tfor ;\n\tSat, 7 Oct 2017 08:31:32 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e0aDP-0006Dp-62; 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charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1791781,"web_url":"http://patchwork.ozlabs.org/comment/1791781/","msgid":"","list_archive_url":null,"date":"2017-10-20T22:14:28","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"content":"Hi Russel,\n\nOn Fri, Oct 6, 2017 at 11:30 PM, Kevin Hilman wrote:\n> Martin Blumenstingl writes:\n>\n>> Hello Russel, Hi Kevin,\n>>\n>> On Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n>> wrote:\n>>> This patchset adds support for booting the secondary CPU cores (and\n>>> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n>>> It is based on an earlier version from Carlo Caione - this helped me\n>>> a lot to get a better understanding of how SMP/CPU hotplug works\n>>> (compared to the code found in Amlogic's GPL kernel sources from\n>>> year 2015).\n>>>\n>>> Changes since v6 from [6]:\n>>> - rebased on top of v4.14-rc1 (which only corrected some line\n>>> numbers in the SCU patches)\n>> it's been two weeks since v6 and since then Linus Lüssing has\n>> confirmed that this works fine on his Odroid-C1 as well (many thanks\n>> for testing!): [7]\n>>\n>>> Changes since v5 from [5]:\n>>> - dropped dependency on another patch series (for the clock\n>>> controller's embedded reset controller, which is needed to boot\n>>> the secondary CPUs) from the cover-letter as that series is now\n>>> merged\n>>> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n>>> Russell King for spotting these). removed the paragraph about\n>>> preemption, cache coherency and interrupts as we're powering on\n>>> a CPU core (the text was copied from the original scu_power_mode\n>>> but simply not adjusted). also changed \"Set the executing CPUs\"\n>>> to \"Set the given (logical) CPU's\" as we're not modifying the\n>>> current CPU. this affects only patch #2\n>>> - extended the commit message of patch #3 with a short sentence\n>>> about why SCU_CPU_STATUS_MASK was introduced\n>>>\n>>> Changes since v4 from [4]:\n>>> - use __pa_symbol(secondary_startup) instead of\n>>> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n>>> (affects patch #4)\n>>> - (cover-letter) removed dependency on my other patch\n>>> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n>>> was merged into Kevin's Amlogic repo today\n>>> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n>>> lines\") again because the reset controller series exposes the\n>>> preprocessor macros now directly, see [1]\n>>> - refreshed the .dts patches so they now include the new header for\n>>> the reset line preprocessor macros\n>>>\n>>> Changes since v3 from [3]:\n>>> - added Rob's ACK to patch #1\n>>> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n>>> - removed all \"pen\" code from patch #4 as that code was not needed\n>>> at all (it was left-over while trying to fix Meson8 secondary CPU\n>>> boot - which turned out to have nothing to do with this \"pen\" code)\n>>> - removed all memory barrier operations as they were added based on\n>>> the code in the Amlogic GPL kernel tree (while trying to fix the\n>>> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n>>> still works fine with these on my Meson8m2 and Meson8b boards.\n>>> - added PATCH #5 as we now have to export the reset identifiers\n>>> (just like we do it with the clock identifiers / preprocessor\n>>> macros) - this is the result of a change in the reset controller\n>>> patch in version 2, see [1]\n>>> - use the reset line preprocessor macros (from patch #5) in patches\n>>> #6 and #7\n>>>\n>>> Changes since v2 from [0]:\n>>> - added support for Meson8 (which requires a slightly different\n>>> enable-method)\n>>> - implemented CPU hotplug support which allows taking a CPU core\n>>> offline for both, Meson8 and Meson8b\n>>> - add a function to smp_scu.c which allows enabling a CPU core from\n>>> a different CPU (previously only the power mode for the current CPU\n>>> could be changed). Without this the CPU cores on Meson8 won't come\n>>> up (Amlogic's vendor GPL kernel sources also enable power through\n>>> SCU as very first step for Meson8b as well)\n>>> - add a function to smp_scu.c to get the power status of a CPU core\n>>> (which is needed because the code in .cpu_kill needs to wait until\n>>> the core is actually powered off)\n>>> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n>>> as it is already applied (for both, Meson8 and Meson8b)\n>>> - dropped the patches which implement the reset controller which is\n>>> built into the clock-controller, these are a separate series: [1]\n>>> - moved the enable-method property to each CPU node\n>>>\n>>>\n>>> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n>>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n>>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n>>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n>>> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n>>> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n>>> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n>>>\n>>> Carlo Caione (2):\n>>> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n>>> ARM: dts: meson8b: add support for booting the secondary CPU cores\n>>>\n>>> Martin Blumenstingl (4):\n>>> ARM: smp_scu: add a helper for powering on a specific CPU\n>>> ARM: smp_scu: allow the platform code to read the SCU CPU status\ncould you please have a look at these two patches? it would be great\nif you could give feedback on these, because they are needed for SMP\nsupport on the Amlogic Meson8 and Meson8b platforms\n\n>>> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n>>> ARM: dts: meson8: add support for booting the secondary CPU cores\n>> @Russel: should Kevin take all patches including the two smp_scu ones?\n>> or do you want to take them through your own tree?\n>\n> With Russell's ack, I can take the series via the amlogic tree. But I'm\n> also fine if Russell wants to take the arch/arm/* via his tree, and I\n> will just queue up the DT.\nplease also let Kevin know if you would like him to take these patches\nthrough the amlogic tree\n\nthank you in advance!\n\n\nRegards\nMartin","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"QQfInDyi\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=googlemail.com header.i=@googlemail.com\n\theader.b=\"V4M/Xhe5\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yJg8l3f9pz9sNV\n\tfor ;\n\tSat, 21 Oct 2017 09:15:19 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e5fZS-00054E-Q7; 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\n\tFri, 20 Oct 2017 15:14:48 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<7hpoa07yn6.fsf@baylibre.com>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t\n\t<7hpoa07yn6.fsf@baylibre.com>","From":"Martin Blumenstingl ","Date":"Sat, 21 Oct 2017 00:14:28 +0200","Message-ID":"","Subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","To":"Russell King ,\n\tlinux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171020_151510_018226_BFAA1D84 ","X-CRM114-Status":"GOOD ( 23.65 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2607:f8b0:4001:c06:0:0:0:241 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (martin.blumenstingl[at]googlemail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\tarnd@arndb.de, Kevin Hilman , robh+dt@kernel.org, \n\tcarlo@caione.org, linux-amlogic@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1792457,"web_url":"http://patchwork.ozlabs.org/comment/1792457/","msgid":"<20171023094921.GO20805@n2100.armlinux.org.uk>","list_archive_url":null,"date":"2017-10-23T09:49:21","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":69080,"url":"http://patchwork.ozlabs.org/api/people/69080/","name":"Russell King (Oracle)","email":"linux@armlinux.org.uk"},"content":"On Sat, Oct 21, 2017 at 12:14:28AM +0200, Martin Blumenstingl wrote:\n> Hi Russel,\n> \n> On Fri, Oct 6, 2017 at 11:30 PM, Kevin Hilman wrote:\n> > Martin Blumenstingl writes:\n> >\n> >> Hello Russel, Hi Kevin,\n> >>\n> >> On Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n> >> wrote:\n> >>> This patchset adds support for booting the secondary CPU cores (and\n> >>> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n> >>> It is based on an earlier version from Carlo Caione - this helped me\n> >>> a lot to get a better understanding of how SMP/CPU hotplug works\n> >>> (compared to the code found in Amlogic's GPL kernel sources from\n> >>> year 2015).\n> >>>\n> >>> Changes since v6 from [6]:\n> >>> - rebased on top of v4.14-rc1 (which only corrected some line\n> >>> numbers in the SCU patches)\n> >> it's been two weeks since v6 and since then Linus Lüssing has\n> >> confirmed that this works fine on his Odroid-C1 as well (many thanks\n> >> for testing!): [7]\n> >>\n> >>> Changes since v5 from [5]:\n> >>> - dropped dependency on another patch series (for the clock\n> >>> controller's embedded reset controller, which is needed to boot\n> >>> the secondary CPUs) from the cover-letter as that series is now\n> >>> merged\n> >>> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n> >>> Russell King for spotting these). removed the paragraph about\n> >>> preemption, cache coherency and interrupts as we're powering on\n> >>> a CPU core (the text was copied from the original scu_power_mode\n> >>> but simply not adjusted). also changed \"Set the executing CPUs\"\n> >>> to \"Set the given (logical) CPU's\" as we're not modifying the\n> >>> current CPU. this affects only patch #2\n> >>> - extended the commit message of patch #3 with a short sentence\n> >>> about why SCU_CPU_STATUS_MASK was introduced\n> >>>\n> >>> Changes since v4 from [4]:\n> >>> - use __pa_symbol(secondary_startup) instead of\n> >>> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n> >>> (affects patch #4)\n> >>> - (cover-letter) removed dependency on my other patch\n> >>> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n> >>> was merged into Kevin's Amlogic repo today\n> >>> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n> >>> lines\") again because the reset controller series exposes the\n> >>> preprocessor macros now directly, see [1]\n> >>> - refreshed the .dts patches so they now include the new header for\n> >>> the reset line preprocessor macros\n> >>>\n> >>> Changes since v3 from [3]:\n> >>> - added Rob's ACK to patch #1\n> >>> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n> >>> - removed all \"pen\" code from patch #4 as that code was not needed\n> >>> at all (it was left-over while trying to fix Meson8 secondary CPU\n> >>> boot - which turned out to have nothing to do with this \"pen\" code)\n> >>> - removed all memory barrier operations as they were added based on\n> >>> the code in the Amlogic GPL kernel tree (while trying to fix the\n> >>> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n> >>> still works fine with these on my Meson8m2 and Meson8b boards.\n> >>> - added PATCH #5 as we now have to export the reset identifiers\n> >>> (just like we do it with the clock identifiers / preprocessor\n> >>> macros) - this is the result of a change in the reset controller\n> >>> patch in version 2, see [1]\n> >>> - use the reset line preprocessor macros (from patch #5) in patches\n> >>> #6 and #7\n> >>>\n> >>> Changes since v2 from [0]:\n> >>> - added support for Meson8 (which requires a slightly different\n> >>> enable-method)\n> >>> - implemented CPU hotplug support which allows taking a CPU core\n> >>> offline for both, Meson8 and Meson8b\n> >>> - add a function to smp_scu.c which allows enabling a CPU core from\n> >>> a different CPU (previously only the power mode for the current CPU\n> >>> could be changed). Without this the CPU cores on Meson8 won't come\n> >>> up (Amlogic's vendor GPL kernel sources also enable power through\n> >>> SCU as very first step for Meson8b as well)\n> >>> - add a function to smp_scu.c to get the power status of a CPU core\n> >>> (which is needed because the code in .cpu_kill needs to wait until\n> >>> the core is actually powered off)\n> >>> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n> >>> as it is already applied (for both, Meson8 and Meson8b)\n> >>> - dropped the patches which implement the reset controller which is\n> >>> built into the clock-controller, these are a separate series: [1]\n> >>> - moved the enable-method property to each CPU node\n> >>>\n> >>>\n> >>> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n> >>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n> >>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n> >>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n> >>> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n> >>> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n> >>> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n> >>>\n> >>> Carlo Caione (2):\n> >>> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n> >>> ARM: dts: meson8b: add support for booting the secondary CPU cores\n> >>>\n> >>> Martin Blumenstingl (4):\n> >>> ARM: smp_scu: add a helper for powering on a specific CPU\n> >>> ARM: smp_scu: allow the platform code to read the SCU CPU status\n> could you please have a look at these two patches? it would be great\n> if you could give feedback on these, because they are needed for SMP\n> support on the Amlogic Meson8 and Meson8b platforms\n> \n> >>> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n> >>> ARM: dts: meson8: add support for booting the secondary CPU cores\n> >> @Russel: should Kevin take all patches including the two smp_scu ones?\n> >> or do you want to take them through your own tree?\n> >\n> > With Russell's ack, I can take the series via the amlogic tree. But I'm\n> > also fine if Russell wants to take the arch/arm/* via his tree, and I\n> > will just queue up the DT.\n> please also let Kevin know if you would like him to take these patches\n> through the amlogic tree\n\nStuff in this thread seems to be sent either over the weekend, or late\non Friday, which means it gets buried by Monday. I'll look at it now.","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"g56i0ZLr\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=armlinux.org.uk header.i=@armlinux.org.uk\n\theader.b=\"ayp4sDEK\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yLBTW2hXmz9sPk\n\tfor ;\n\tMon, 23 Oct 2017 20:50:07 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e6ZMv-0002uv-R9; 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bh=zCdNxi7VhTgnWoSci6hSm/Ww6DQ8oU5+aG1dFTtdBDI=;\n\tb=g56i0ZLrJ0NnbI\n\tXs01vpGS6Z0DEeEnL3YIBcvvirTKY4ZyfRCFtjf00/7zPr5D27FCwW+aHuI/Qd7DonXDZfCtfn+gq\n\tlEZtwhO+KjwAsGG6/qbyH5S7T5XgFhvv5521QjGdsrLkiEsXKqm+x24mmKA8FQr11KZakJxXwVYEc\n\tHga0kTZkvOthoKpKi7iST9ZrAp3edN29Yy1UDp4q1BabE23iqEDhBIcVsW4YvXtyfRR62ild/z7jV\n\tHH841u9CjCeyvdhjzGqDenD96DcVd0kRWoZ0BC7Vikl9lfDdXGIY3L/Ovgq6vhjXTanQ/5iu2VqWK\n\tEFg+FQjWwbIv02/F/+Qg==;","v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=armlinux.org.uk; s=pandora-2014; \n\th=Sender:In-Reply-To:Content-Transfer-Encoding:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date;\n\tbh=K0NEHFuqOgVJiwlSislIsraa8MejZXyfUllN36c0QWs=; \n\tb=ayp4sDEKbEK7kI21uxE2fxanyEnLEKkZndBuoLDumj+t8WqX8oBYVmQJ0NKiEi+wcW1zL1xDG2hCSvG3SGVECOg0InimgtiC7EyB6KcUSebAcUobRLQ0yOqNscUdZKlkY9R7oVKKj6yTexCVquajkfbGFl5NtFI0ZGUbV8l4t90=;"],"Date":"Mon, 23 Oct 2017 10:49:21 +0100","From":"Russell King - ARM Linux ","To":"Martin Blumenstingl ","Subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","Message-ID":"<20171023094921.GO20805@n2100.armlinux.org.uk>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t\n\t<7hpoa07yn6.fsf@baylibre.com>\n\t","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171023_024955_056132_1989F84C ","X-CRM114-Status":"GOOD ( 37.21 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium\n\ttrust [2001:4d48:ad52:3201:214:fdff:fe10:1be6 listed in]\n\t[list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\tarnd@arndb.de, Kevin Hilman , robh+dt@kernel.org, \n\tcarlo@caione.org, linux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"iso-8859-1\"","Content-Transfer-Encoding":"quoted-printable","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1792461,"web_url":"http://patchwork.ozlabs.org/comment/1792461/","msgid":"<20171023095111.GP20805@n2100.armlinux.org.uk>","list_archive_url":null,"date":"2017-10-23T09:51:12","subject":"Re: [PATCH v7 2/6] ARM: smp_scu: add a helper for powering on a\n\tspecific CPU","submitter":{"id":69080,"url":"http://patchwork.ozlabs.org/api/people/69080/","name":"Russell King (Oracle)","email":"linux@armlinux.org.uk"},"content":"On Sun, Sep 17, 2017 at 06:45:19PM +0200, Martin Blumenstingl wrote:\n> To boot the secondary CPUs on the Amlogic Meson8/Meson8m2 (Cortex-A9)\n> and Meson8b (Cortex-A5) SoCs we have to enable SCU mode SCU_PM_NORMAL,\n> otherwise the secondary cores will not start.\n> This patch adds a scu_cpu_power_enable() function which can be used to\n> enable SCU_PM_NORMAL for a specific (logical) CPU. An internal helper\n> function is also created, to avoid code duplication with\n> scu_power_mode().\n> \n> Signed-off-by: Martin Blumenstingl \n\nAcked-by: Russell King ","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"b8jRK8Wm\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=armlinux.org.uk header.i=@armlinux.org.uk\n\theader.b=\"XXs4D7mc\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yLBWd0t3nz9sPk\n\tfor ;\n\tMon, 23 Oct 2017 20:51:57 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e6ZOg-0004pE-It; Mon, 23 Oct 2017 09:51:50 +0000","from pandora.armlinux.org.uk\n\t([2001:4d48:ad52:3201:214:fdff:fe10:1be6])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e6ZOZ-0004j1-3a for linux-arm-kernel@lists.infradead.org;\n\tMon, 23 Oct 2017 09:51:45 +0000","from n2100.armlinux.org.uk\n\t([2001:4d48:ad52:3201:214:fdff:fe10:4f86]:52102)\n\tby pandora.armlinux.org.uk with esmtpsa\n\t(TLSv1:DHE-RSA-AES256-SHA:256)\n\t(Exim 4.82_1-5b7a7c0-XX) (envelope-from )\n\tid 1e6ZO8-0006Zh-6J; Mon, 23 Oct 2017 10:51:16 +0100","from linux by n2100.armlinux.org.uk with local (Exim 4.76)\n\t(envelope-from )\n\tid 1e6ZO4-0001D4-NO; Mon, 23 Oct 2017 10:51:12 +0100"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=usOrw8/vjuG1hkSroQnIQ79P4FeA5p/BI8Hamixe3OQ=;\n\tb=b8jRK8WmEFVicC\n\tBCHh6vK4sedovm6MoUGJLNFLdMf6qIPOseUJNMgFkKTYr0wenJxvfXKQaQraJ+bd2IvmCvEbq9/KR\n\ti4uta3cthR/olnwQcVJMQwnvGGu4Bw2KLFcv05kbNZpi590WWoLMOAQqjNY69o/QpcDbVgoItQ1dG\n\txzhaM7jlcDtz2k2Xd6f9lXnPtxQtIQiK4GwemIK8yoh7mFf4wCbNyfd2BjEtL6Hmz9ioTwlKXf4/L\n\trNDWlChulGpgOR97IzEjLRn/hILQPQoloRRTBhMjPW+RnoQIwn/4MWuM7gDTEg2KMPKe5fEEf1Z27\n\t6gKVGHPKyfiIRUKKD5CA==;","v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=armlinux.org.uk; s=pandora-2014; \n\th=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date;\n\tbh=oc/pjCqpy8onVXCm7yEUsgoDRzKfzeCxrsnv8ycwT6s=; \n\tb=XXs4D7mc25u540wPc346rwnlGJv1JbyggoOIMDLkyuwmb1LP8x7inac14FnCZRy3TbrZgjPlPrJ4a9qck1vrHHKx2kbencC9CKyuWHJmm/RzjtC6Um6Jt+864zxhZi6QAspkat5pDw1brZoRLL7hDBieTuDE5DVEI7a3erIMKxE=;"],"Date":"Mon, 23 Oct 2017 10:51:12 +0100","From":"Russell King - ARM Linux ","To":"Martin Blumenstingl ","Subject":"Re: [PATCH v7 2/6] ARM: smp_scu: add a helper for powering on a\n\tspecific CPU","Message-ID":"<20171023095111.GP20805@n2100.armlinux.org.uk>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t<20170917164523.6970-3-martin.blumenstingl@googlemail.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170917164523.6970-3-martin.blumenstingl@googlemail.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171023_025143_497736_EADCBD95 ","X-CRM114-Status":"GOOD ( 12.45 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium\n\ttrust [2001:4d48:ad52:3201:214:fdff:fe10:1be6 listed in]\n\t[list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\tarnd@arndb.de, khilman@baylibre.com, robh+dt@kernel.org, carlo@caione.org,\n\tlinux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1792464,"web_url":"http://patchwork.ozlabs.org/comment/1792464/","msgid":"<20171023095450.GQ20805@n2100.armlinux.org.uk>","list_archive_url":null,"date":"2017-10-23T09:54:50","subject":"Re: [PATCH v7 3/6] ARM: smp_scu: allow the platform code to read the\n\tSCU CPU status","submitter":{"id":69080,"url":"http://patchwork.ozlabs.org/api/people/69080/","name":"Russell King (Oracle)","email":"linux@armlinux.org.uk"},"content":"On Sun, Sep 17, 2017 at 06:45:20PM +0200, Martin Blumenstingl wrote:\n> On Amlogic Meson8 / Meson8m2 (both Cortex-A9) and Meson8b (Cortex-A5)\n> the CPU hotplug code needs to wait until the SCU status of the CPU that\n> is being taken offline is SCU_PM_POWEROFF.\n> Provide a utility function (which can be invoked for example from\n> .cpu_kill()) which allows reading the SCU status of a CPU.\n> \n> While here, replace the magic number 0x3 with a preprocessor macro\n> (SCU_CPU_STATUS_MASK) so we don't have to duplicate this magic number in\n> the new function.\n> \n> Signed-off-by: Martin Blumenstingl \n\nAcked-by: Russell King \n\n> ---\n> arch/arm/include/asm/smp_scu.h | 6 ++++++\n> arch/arm/kernel/smp_scu.c | 18 +++++++++++++++++-\n> 2 files changed, 23 insertions(+), 1 deletion(-)\n> \n> diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h\n> index 4c47bdfd4f61..1529d1ae2f8d 100644\n> --- a/arch/arm/include/asm/smp_scu.h\n> +++ b/arch/arm/include/asm/smp_scu.h\n> @@ -28,6 +28,7 @@ static inline unsigned long scu_a9_get_base(void)\n> unsigned int scu_get_core_count(void __iomem *);\n> int scu_power_mode(void __iomem *, unsigned int);\n> int scu_cpu_power_enable(void __iomem *, unsigned int);\n> +int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu);\n> #else\n> static inline unsigned int scu_get_core_count(void __iomem *scu_base)\n> {\n> @@ -42,6 +43,11 @@ static inline int scu_cpu_power_enable(void __iomem *scu_base,\n> {\n> \treturn -EINVAL;\n> }\n> +static inline int scu_get_cpu_power_mode(void __iomem *scu_base,\n> +\t\t\t\t\t unsigned int logical_cpu)\n> +{\n> +\treturn -EINVAL;\n> +}\n> #endif\n> \n> #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)\n> diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c\n> index 1d549c16b5fc..c6b33074c393 100644\n> --- a/arch/arm/kernel/smp_scu.c\n> +++ b/arch/arm/kernel/smp_scu.c\n> @@ -21,6 +21,7 @@\n> #define SCU_STANDBY_ENABLE\t(1 << 5)\n> #define SCU_CONFIG\t\t0x04\n> #define SCU_CPU_STATUS\t\t0x08\n> +#define SCU_CPU_STATUS_MASK\tGENMASK(1, 0)\n> #define SCU_INVALIDATE\t\t0x0c\n> #define SCU_FPGA_REVISION\t0x10\n> \n> @@ -82,7 +83,8 @@ static int scu_set_power_mode_internal(void __iomem *scu_base,\n> \tif (mode > 3 || mode == 1 || cpu > 3)\n> \t\treturn -EINVAL;\n> \n> -\tval = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;\n> +\tval = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);\n> +\tval &= ~SCU_CPU_STATUS_MASK;\n> \tval |= mode;\n> \twriteb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);\n> \n> @@ -109,3 +111,17 @@ int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)\n> {\n> \treturn scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);\n> }\n> +\n> +int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)\n> +{\n> +\tunsigned int val;\n> +\tint cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);\n> +\n> +\tif (cpu > 3)\n> +\t\treturn -EINVAL;\n> +\n> +\tval = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);\n> +\tval &= SCU_CPU_STATUS_MASK;\n> +\n> +\treturn val;\n> +}\n> -- \n> 2.14.1\n>","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"I3wn+Sj8\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=armlinux.org.uk header.i=@armlinux.org.uk\n\theader.b=\"quwP2dtM\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yLBbt0Jysz9sPk\n\tfor ;\n\tMon, 23 Oct 2017 20:55:37 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e6ZSI-0006i4-5u; Mon, 23 Oct 2017 09:55:34 +0000","from pandora.armlinux.org.uk\n\t([2001:4d48:ad52:3201:214:fdff:fe10:1be6])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e6ZSA-0005Qg-9H for linux-arm-kernel@lists.infradead.org;\n\tMon, 23 Oct 2017 09:55:29 +0000","from n2100.armlinux.org.uk\n\t([2001:4d48:ad52:3201:214:fdff:fe10:4f86]:52141)\n\tby pandora.armlinux.org.uk with esmtpsa\n\t(TLSv1:DHE-RSA-AES256-SHA:256)\n\t(Exim 4.82_1-5b7a7c0-XX) (envelope-from )\n\tid 1e6ZRg-0006al-1s; Mon, 23 Oct 2017 10:54:56 +0100","from linux by n2100.armlinux.org.uk with local (Exim 4.76)\n\t(envelope-from )\n\tid 1e6ZRb-0001Fn-Kc; Mon, 23 Oct 2017 10:54:51 +0100"],"DKIM-Signature":["v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=/XZaJFdkP767jPxX6re8e5kfcRFQ/hidSrDtv3eVQBc=;\n\tb=I3wn+Sj8IdWIfN\n\th8Tu5Qflj97NYZ7ljPHuIXXLRCxxu9h50uehVxM/7RpmlcWGi1wmtBKb2yGsp3MaJ7eyivF/zEdEW\n\tm2O0pkrtqgwUN2G39sN3vpF1aRgtMh0Oz1mohFGfEFaeLKclSSaPaagMkiuoJjNWvAih68M+1x8ys\n\tgV0T6A7k3yH2riEJrVae7IUqbi5R+jLv6TBM2mK3lZ9vMCJWtimdIoDqcEWuBKUQ97UHWGe6AmvGv\n\t24O3Q7gKjf7WRtuhC9YQPUFenNGi8Yx1psgqSjTVTTAbTtPCIuAepnZN1yhl2+x9akY79uA3IKMQu\n\tQ2KxtAlpgeInaQx6hBQw==;","v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=armlinux.org.uk; s=pandora-2014; \n\th=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date;\n\tbh=C4cjqh5CCgOXG5irOG2j8x2dLgtuoaLrKRZNL+W2GA0=; \n\tb=quwP2dtMu/T4ZRyVJNp2I9JqMPTYaSKAMO9YqDLGp4j9w1xfrrnw9ac/ewYQmGsOLoUifMypaC5jZYd2D6SH/XdVq5ZeUnt4Mc3EsS5RZwYy33cpmTllCfM76IcIRJ3f5KJ440HCvwCbqsGuFoPMnPSCCZky2kVZ1l1tPFGo9nM=;"],"Date":"Mon, 23 Oct 2017 10:54:50 +0100","From":"Russell King - ARM Linux ","To":"Martin Blumenstingl ","Subject":"Re: [PATCH v7 3/6] ARM: smp_scu: allow the platform code to read the\n\tSCU CPU status","Message-ID":"<20171023095450.GQ20805@n2100.armlinux.org.uk>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t<20170917164523.6970-4-martin.blumenstingl@googlemail.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170917164523.6970-4-martin.blumenstingl@googlemail.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171023_025526_834137_3B56C60D ","X-CRM114-Status":"GOOD ( 20.52 )","X-Spam-Score":"-4.3 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.3 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium\n\ttrust [2001:4d48:ad52:3201:214:fdff:fe10:1be6 listed in]\n\t[list.dnswl.org]\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\tarnd@arndb.de, khilman@baylibre.com, robh+dt@kernel.org, carlo@caione.org,\n\tlinux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1793929,"web_url":"http://patchwork.ozlabs.org/comment/1793929/","msgid":"","list_archive_url":null,"date":"2017-10-25T21:05:09","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"content":"Hi Russel,\n\nOn Mon, Oct 23, 2017 at 11:49 AM, Russell King - ARM Linux\n wrote:\n> On Sat, Oct 21, 2017 at 12:14:28AM +0200, Martin Blumenstingl wrote:\n>> Hi Russel,\n>>\n>> On Fri, Oct 6, 2017 at 11:30 PM, Kevin Hilman wrote:\n>> > Martin Blumenstingl writes:\n>> >\n>> >> Hello Russel, Hi Kevin,\n>> >>\n>> >> On Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n>> >> wrote:\n>> >>> This patchset adds support for booting the secondary CPU cores (and\n>> >>> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n>> >>> It is based on an earlier version from Carlo Caione - this helped me\n>> >>> a lot to get a better understanding of how SMP/CPU hotplug works\n>> >>> (compared to the code found in Amlogic's GPL kernel sources from\n>> >>> year 2015).\n>> >>>\n>> >>> Changes since v6 from [6]:\n>> >>> - rebased on top of v4.14-rc1 (which only corrected some line\n>> >>> numbers in the SCU patches)\n>> >> it's been two weeks since v6 and since then Linus Lüssing has\n>> >> confirmed that this works fine on his Odroid-C1 as well (many thanks\n>> >> for testing!): [7]\n>> >>\n>> >>> Changes since v5 from [5]:\n>> >>> - dropped dependency on another patch series (for the clock\n>> >>> controller's embedded reset controller, which is needed to boot\n>> >>> the secondary CPUs) from the cover-letter as that series is now\n>> >>> merged\n>> >>> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n>> >>> Russell King for spotting these). removed the paragraph about\n>> >>> preemption, cache coherency and interrupts as we're powering on\n>> >>> a CPU core (the text was copied from the original scu_power_mode\n>> >>> but simply not adjusted). also changed \"Set the executing CPUs\"\n>> >>> to \"Set the given (logical) CPU's\" as we're not modifying the\n>> >>> current CPU. this affects only patch #2\n>> >>> - extended the commit message of patch #3 with a short sentence\n>> >>> about why SCU_CPU_STATUS_MASK was introduced\n>> >>>\n>> >>> Changes since v4 from [4]:\n>> >>> - use __pa_symbol(secondary_startup) instead of\n>> >>> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n>> >>> (affects patch #4)\n>> >>> - (cover-letter) removed dependency on my other patch\n>> >>> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n>> >>> was merged into Kevin's Amlogic repo today\n>> >>> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n>> >>> lines\") again because the reset controller series exposes the\n>> >>> preprocessor macros now directly, see [1]\n>> >>> - refreshed the .dts patches so they now include the new header for\n>> >>> the reset line preprocessor macros\n>> >>>\n>> >>> Changes since v3 from [3]:\n>> >>> - added Rob's ACK to patch #1\n>> >>> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n>> >>> - removed all \"pen\" code from patch #4 as that code was not needed\n>> >>> at all (it was left-over while trying to fix Meson8 secondary CPU\n>> >>> boot - which turned out to have nothing to do with this \"pen\" code)\n>> >>> - removed all memory barrier operations as they were added based on\n>> >>> the code in the Amlogic GPL kernel tree (while trying to fix the\n>> >>> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n>> >>> still works fine with these on my Meson8m2 and Meson8b boards.\n>> >>> - added PATCH #5 as we now have to export the reset identifiers\n>> >>> (just like we do it with the clock identifiers / preprocessor\n>> >>> macros) - this is the result of a change in the reset controller\n>> >>> patch in version 2, see [1]\n>> >>> - use the reset line preprocessor macros (from patch #5) in patches\n>> >>> #6 and #7\n>> >>>\n>> >>> Changes since v2 from [0]:\n>> >>> - added support for Meson8 (which requires a slightly different\n>> >>> enable-method)\n>> >>> - implemented CPU hotplug support which allows taking a CPU core\n>> >>> offline for both, Meson8 and Meson8b\n>> >>> - add a function to smp_scu.c which allows enabling a CPU core from\n>> >>> a different CPU (previously only the power mode for the current CPU\n>> >>> could be changed). Without this the CPU cores on Meson8 won't come\n>> >>> up (Amlogic's vendor GPL kernel sources also enable power through\n>> >>> SCU as very first step for Meson8b as well)\n>> >>> - add a function to smp_scu.c to get the power status of a CPU core\n>> >>> (which is needed because the code in .cpu_kill needs to wait until\n>> >>> the core is actually powered off)\n>> >>> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n>> >>> as it is already applied (for both, Meson8 and Meson8b)\n>> >>> - dropped the patches which implement the reset controller which is\n>> >>> built into the clock-controller, these are a separate series: [1]\n>> >>> - moved the enable-method property to each CPU node\n>> >>>\n>> >>>\n>> >>> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n>> >>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n>> >>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n>> >>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n>> >>> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n>> >>> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n>> >>> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n>> >>>\n>> >>> Carlo Caione (2):\n>> >>> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n>> >>> ARM: dts: meson8b: add support for booting the secondary CPU cores\n>> >>>\n>> >>> Martin Blumenstingl (4):\n>> >>> ARM: smp_scu: add a helper for powering on a specific CPU\n>> >>> ARM: smp_scu: allow the platform code to read the SCU CPU status\n>> could you please have a look at these two patches? it would be great\n>> if you could give feedback on these, because they are needed for SMP\n>> support on the Amlogic Meson8 and Meson8b platforms\n>>\n>> >>> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n>> >>> ARM: dts: meson8: add support for booting the secondary CPU cores\n>> >> @Russel: should Kevin take all patches including the two smp_scu ones?\n>> >> or do you want to take them through your own tree?\n>> >\n>> > With Russell's ack, I can take the series via the amlogic tree. But I'm\n>> > also fine if Russell wants to take the arch/arm/* via his tree, and I\n>> > will just queue up the DT.\n>> please also let Kevin know if you would like him to take these patches\n>> through the amlogic tree\n>\n> Stuff in this thread seems to be sent either over the weekend, or late\n> on Friday, which means it gets buried by Monday. I'll look at it now.\nthank you for reviewing my patches!\n\nI do this in my spare time - so I typically end up having all bugs\nfixed at some point during the weekend\nhowever, you still found my patches - problem solved. :)\n\n\nThank you!\nRegards\nMartin","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org header.b=\"njcYz2q+\"; \n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=googlemail.com header.i=@googlemail.com\n\theader.b=\"V4IEl7+q\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3yMjNS0ZhJz9t3n\n\tfor ;\n\tThu, 26 Oct 2017 08:06:00 +1100 (AEDT)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1e7Ss7-0000EB-MR; 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Wed,\n\t25 Oct 2017 14:05:29 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20171023094921.GO20805@n2100.armlinux.org.uk>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t\n\t<7hpoa07yn6.fsf@baylibre.com>\n\t\n\t<20171023094921.GO20805@n2100.armlinux.org.uk>","From":"Martin Blumenstingl ","Date":"Wed, 25 Oct 2017 23:05:09 +0200","Message-ID":"","Subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","To":"Russell King - ARM Linux ","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20171025_140552_038876_BB0AE103 ","X-CRM114-Status":"GOOD ( 28.70 )","X-Spam-Score":"-2.0 (--)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-2.0 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/,\n\tno\n\ttrust [2607:f8b0:4001:c0b:0:0:0:241 listed in] [list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (martin.blumenstingl[at]googlemail.com)\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.1 DKIM_VALID Message has at least one valid DKIM or DK signature\n\t0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n\tnot necessarily valid\n\t-0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from\n\tauthor's domain","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, f.fainelli@gmail.com, \n\tarnd@arndb.de, Kevin Hilman , robh+dt@kernel.org, \n\tcarlo@caione.org, linux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org","Content-Type":"text/plain; charset=\"utf-8\"","Content-Transfer-Encoding":"base64","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1795474,"web_url":"http://patchwork.ozlabs.org/comment/1795474/","msgid":"<7hwp3eug0k.fsf@baylibre.com>","list_archive_url":null,"date":"2017-10-29T15:31:55","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":68189,"url":"http://patchwork.ozlabs.org/api/people/68189/","name":"Kevin Hilman","email":"khilman@baylibre.com"},"content":"Martin Blumenstingl writes:\n\n> This patchset adds support for booting the secondary CPU cores (and\n> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n> It is based on an earlier version from Carlo Caione - this helped me\n> a lot to get a better understanding of how SMP/CPU hotplug works\n> (compared to the code found in Amlogic's GPL kernel sources from\n> year 2015).\n\n[...]\n\n> Carlo Caione (2):\n> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n> ARM: dts: meson8b: add support for booting the secondary CPU cores\n\nApplied to v4.15/dt...\n\n> Martin Blumenstingl (4):\n> ARM: smp_scu: add a helper for powering on a specific CPU\n> ARM: smp_scu: allow the platform code to read the SCU CPU status\n> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n> ARM: dts: meson8: add support for booting the secondary CPU cores\n\nApplied to v4.15/soc with Russell's ack.\n\nThanks,\n\nKevin","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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