[{"id":1778007,"web_url":"http://patchwork.ozlabs.org/comment/1778007/","msgid":"","list_archive_url":null,"date":"2017-10-01T12:19:11","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"content":"Hello Russel, Hi Kevin,\n\nOn Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n wrote:\n> This patchset adds support for booting the secondary CPU cores (and\n> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n> It is based on an earlier version from Carlo Caione - this helped me\n> a lot to get a better understanding of how SMP/CPU hotplug works\n> (compared to the code found in Amlogic's GPL kernel sources from\n> year 2015).\n>\n> Changes since v6 from [6]:\n> - rebased on top of v4.14-rc1 (which only corrected some line\n> numbers in the SCU patches)\nit's been two weeks since v6 and since then Linus Lüssing has\nconfirmed that this works fine on his Odroid-C1 as well (many thanks\nfor testing!): [7]\n\n> Changes since v5 from [5]:\n> - dropped dependency on another patch series (for the clock\n> controller's embedded reset controller, which is needed to boot\n> the secondary CPUs) from the cover-letter as that series is now\n> merged\n> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n> Russell King for spotting these). removed the paragraph about\n> preemption, cache coherency and interrupts as we're powering on\n> a CPU core (the text was copied from the original scu_power_mode\n> but simply not adjusted). also changed \"Set the executing CPUs\"\n> to \"Set the given (logical) CPU's\" as we're not modifying the\n> current CPU. this affects only patch #2\n> - extended the commit message of patch #3 with a short sentence\n> about why SCU_CPU_STATUS_MASK was introduced\n>\n> Changes since v4 from [4]:\n> - use __pa_symbol(secondary_startup) instead of\n> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n> (affects patch #4)\n> - (cover-letter) removed dependency on my other patch\n> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n> was merged into Kevin's Amlogic repo today\n> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n> lines\") again because the reset controller series exposes the\n> preprocessor macros now directly, see [1]\n> - refreshed the .dts patches so they now include the new header for\n> the reset line preprocessor macros\n>\n> Changes since v3 from [3]:\n> - added Rob's ACK to patch #1\n> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n> - removed all \"pen\" code from patch #4 as that code was not needed\n> at all (it was left-over while trying to fix Meson8 secondary CPU\n> boot - which turned out to have nothing to do with this \"pen\" code)\n> - removed all memory barrier operations as they were added based on\n> the code in the Amlogic GPL kernel tree (while trying to fix the\n> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n> still works fine with these on my Meson8m2 and Meson8b boards.\n> - added PATCH #5 as we now have to export the reset identifiers\n> (just like we do it with the clock identifiers / preprocessor\n> macros) - this is the result of a change in the reset controller\n> patch in version 2, see [1]\n> - use the reset line preprocessor macros (from patch #5) in patches\n> #6 and #7\n>\n> Changes since v2 from [0]:\n> - added support for Meson8 (which requires a slightly different\n> enable-method)\n> - implemented CPU hotplug support which allows taking a CPU core\n> offline for both, Meson8 and Meson8b\n> - add a function to smp_scu.c which allows enabling a CPU core from\n> a different CPU (previously only the power mode for the current CPU\n> could be changed). Without this the CPU cores on Meson8 won't come\n> up (Amlogic's vendor GPL kernel sources also enable power through\n> SCU as very first step for Meson8b as well)\n> - add a function to smp_scu.c to get the power status of a CPU core\n> (which is needed because the code in .cpu_kill needs to wait until\n> the core is actually powered off)\n> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n> as it is already applied (for both, Meson8 and Meson8b)\n> - dropped the patches which implement the reset controller which is\n> built into the clock-controller, these are a separate series: [1]\n> - moved the enable-method property to each CPU node\n>\n>\n> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n>\n> Carlo Caione (2):\n> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n> ARM: dts: meson8b: add support for booting the secondary CPU cores\n>\n> Martin Blumenstingl (4):\n> ARM: smp_scu: add a helper for powering on a specific CPU\n> ARM: smp_scu: allow the platform code to read the SCU CPU status\n> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n> ARM: dts: meson8: add support for booting the secondary CPU cores\n@Russel: should Kevin take all patches including the two smp_scu ones?\nor do you want to take them through your own tree?\n\n> .../devicetree/bindings/arm/amlogic/pmu.txt | 18 +\n> .../devicetree/bindings/arm/amlogic/smp-sram.txt | 32 ++\n> Documentation/devicetree/bindings/arm/cpus.txt | 2 +\n> arch/arm/Makefile | 1 +\n> arch/arm/boot/dts/meson8.dtsi | 21 +\n> arch/arm/boot/dts/meson8b.dtsi | 21 +\n> arch/arm/include/asm/smp_scu.h | 12 +\n> arch/arm/kernel/smp_scu.c | 43 +-\n> arch/arm/mach-meson/Kconfig | 1 +\n> arch/arm/mach-meson/Makefile | 1 +\n> arch/arm/mach-meson/platsmp.c | 440 +++++++++++++++++++++\n> 11 files changed, 586 insertions(+), 6 deletions(-)\n> create mode 100644 Documentation/devicetree/bindings/arm/amlogic/pmu.txt\n> create mode 100644 Documentation/devicetree/bindings/arm/amlogic/smp-sram.txt\n> create mode 100644 arch/arm/mach-meson/platsmp.c\n>\n> --\n> 2.14.1\n>\n\nRegards,\nMartin\n\n\n[7] http://lists.infradead.org/pipermail/linux-amlogic/2017-September/004813.html\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=googlemail.com header.i=@googlemail.com\n\theader.b=\"TcSaoFwG\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y4krG29Xxz9t2M\n\tfor ;\n\tSun, 1 Oct 2017 23:19:42 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750988AbdJAMTd (ORCPT\n\t);\n\tSun, 1 Oct 2017 08:19:33 -0400","from mail-io0-f195.google.com ([209.85.223.195]:37141 \"EHLO\n\tmail-io0-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1750965AbdJAMTc (ORCPT\n\t); Sun, 1 Oct 2017 08:19:32 -0400","by mail-io0-f195.google.com with SMTP id 93so1871370iol.4\n\tfor ;\n\tSun, 01 Oct 2017 05:19:32 -0700 (PDT)","by 10.2.51.84 with HTTP; Sun, 1 Oct 2017 05:19:11 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=googlemail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc:content-transfer-encoding;\n\tbh=B3ii01uvIAuFlXTtNElp0Rwllk75hKFWkiVLnTcSCys=;\n\tb=TcSaoFwGjahaAOJyM5IjvQVNJN6OgpMvY/GKmo2xGJLbdIzAy48etE6V7tMQcvPqc1\n\tReqU3rJkryyxkQGPRcAsVi64aA6kd1OiNcf5LKiFrLnnnjPxy6o2s0PuJnY128r7yZlP\n\tXHOgm8DupYa0WyufBzRQHCqs+3fqGkRyK6HXeN2NqYvSlBUysm658/vVJfOvzyubinZ+\n\t4ieLmNrNdw2y8USdSDP7l0IWpvxZWbBHg0nmdkTj3aFaCwLAXl98BCye+Q3WqkF/TDCz\n\tonWHSNP6yHkJZuEnd5LvR0bLCvTP8aPXA9ajM3PiHy9AmUy9Hw/0vk6GowbfyFePKYUU\n\t8dJg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc:content-transfer-encoding;\n\tbh=B3ii01uvIAuFlXTtNElp0Rwllk75hKFWkiVLnTcSCys=;\n\tb=Z8K0yJkmm8srvXcVb7oKoMruxg76zZy7iGPeWMV23ZO8LOl9RENh81T1ZkrSanACOH\n\tNJklpx2HQyHsB7qHJIupO2KGS6toP4sfvLtmbkQ+Uzli99KZB1jtD6ID0p4jMI5GSVLX\n\tCgdH5QxYSd0JJSjml9jdRULbAi0hYvsjPFxzv6lxmJZ7PrSLdJP0xQwoQ/vGyTfHbuJ8\n\tixjyL4mSEe/35WpBgvUaq3tfpPGedQckVaCIsOZqHuLV1QMSYnCdJUZh2woJkb86GqOk\n\tBVIEKN1yqehH9m3pxu3YOScyE4j6la693gOh8At00cs6oHOvkC8i7si2ug/ZdCIUNIN+\n\tYwnQ==","X-Gm-Message-State":"AMCzsaWFsyt57fz3GETWa8huBUaCw45DkHHVYfScem9+RiKtDVDkeJfJ\n\tO/RqK44stTbuT9aK/zwkQRlNfRue9OWRJpN4zMQ=","X-Google-Smtp-Source":"AOwi7QC+z4Jmi2rmuhp5zdmI4Gtjcs7KENDGIJeI/PgUWGf3ntiEmMlBWeASvWlAgPU4kgsD+AvT76rXiz80asbwoxc=","X-Received":"by 10.107.81.1 with SMTP id f1mr20038945iob.17.1506860371470;\n\tSun, 01 Oct 2017 05:19:31 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>","From":"Martin Blumenstingl ","Date":"Sun, 1 Oct 2017 14:19:11 +0200","Message-ID":"","Subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","To":"khilman@baylibre.com, linux@armlinux.org.uk","Cc":"carlo@caione.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-amlogic@lists.infradead.org, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org, arnd@arndb.de, mark.rutland@arm.com,\n\tf.fainelli@gmail.com,\n\tMartin Blumenstingl ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1781900,"web_url":"http://patchwork.ozlabs.org/comment/1781900/","msgid":"<7hpoa07yn6.fsf@baylibre.com>","list_archive_url":null,"date":"2017-10-06T21:30:05","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":68189,"url":"http://patchwork.ozlabs.org/api/people/68189/","name":"Kevin Hilman","email":"khilman@baylibre.com"},"content":"Martin Blumenstingl writes:\n\n> Hello Russel, Hi Kevin,\n>\n> On Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n> wrote:\n>> This patchset adds support for booting the secondary CPU cores (and\n>> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n>> It is based on an earlier version from Carlo Caione - this helped me\n>> a lot to get a better understanding of how SMP/CPU hotplug works\n>> (compared to the code found in Amlogic's GPL kernel sources from\n>> year 2015).\n>>\n>> Changes since v6 from [6]:\n>> - rebased on top of v4.14-rc1 (which only corrected some line\n>> numbers in the SCU patches)\n> it's been two weeks since v6 and since then Linus Lüssing has\n> confirmed that this works fine on his Odroid-C1 as well (many thanks\n> for testing!): [7]\n>\n>> Changes since v5 from [5]:\n>> - dropped dependency on another patch series (for the clock\n>> controller's embedded reset controller, which is needed to boot\n>> the secondary CPUs) from the cover-letter as that series is now\n>> merged\n>> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n>> Russell King for spotting these). removed the paragraph about\n>> preemption, cache coherency and interrupts as we're powering on\n>> a CPU core (the text was copied from the original scu_power_mode\n>> but simply not adjusted). also changed \"Set the executing CPUs\"\n>> to \"Set the given (logical) CPU's\" as we're not modifying the\n>> current CPU. this affects only patch #2\n>> - extended the commit message of patch #3 with a short sentence\n>> about why SCU_CPU_STATUS_MASK was introduced\n>>\n>> Changes since v4 from [4]:\n>> - use __pa_symbol(secondary_startup) instead of\n>> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n>> (affects patch #4)\n>> - (cover-letter) removed dependency on my other patch\n>> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n>> was merged into Kevin's Amlogic repo today\n>> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n>> lines\") again because the reset controller series exposes the\n>> preprocessor macros now directly, see [1]\n>> - refreshed the .dts patches so they now include the new header for\n>> the reset line preprocessor macros\n>>\n>> Changes since v3 from [3]:\n>> - added Rob's ACK to patch #1\n>> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n>> - removed all \"pen\" code from patch #4 as that code was not needed\n>> at all (it was left-over while trying to fix Meson8 secondary CPU\n>> boot - which turned out to have nothing to do with this \"pen\" code)\n>> - removed all memory barrier operations as they were added based on\n>> the code in the Amlogic GPL kernel tree (while trying to fix the\n>> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n>> still works fine with these on my Meson8m2 and Meson8b boards.\n>> - added PATCH #5 as we now have to export the reset identifiers\n>> (just like we do it with the clock identifiers / preprocessor\n>> macros) - this is the result of a change in the reset controller\n>> patch in version 2, see [1]\n>> - use the reset line preprocessor macros (from patch #5) in patches\n>> #6 and #7\n>>\n>> Changes since v2 from [0]:\n>> - added support for Meson8 (which requires a slightly different\n>> enable-method)\n>> - implemented CPU hotplug support which allows taking a CPU core\n>> offline for both, Meson8 and Meson8b\n>> - add a function to smp_scu.c which allows enabling a CPU core from\n>> a different CPU (previously only the power mode for the current CPU\n>> could be changed). Without this the CPU cores on Meson8 won't come\n>> up (Amlogic's vendor GPL kernel sources also enable power through\n>> SCU as very first step for Meson8b as well)\n>> - add a function to smp_scu.c to get the power status of a CPU core\n>> (which is needed because the code in .cpu_kill needs to wait until\n>> the core is actually powered off)\n>> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n>> as it is already applied (for both, Meson8 and Meson8b)\n>> - dropped the patches which implement the reset controller which is\n>> built into the clock-controller, these are a separate series: [1]\n>> - moved the enable-method property to each CPU node\n>>\n>>\n>> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n>> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n>> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n>> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n>>\n>> Carlo Caione (2):\n>> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n>> ARM: dts: meson8b: add support for booting the secondary CPU cores\n>>\n>> Martin Blumenstingl (4):\n>> ARM: smp_scu: add a helper for powering on a specific CPU\n>> ARM: smp_scu: allow the platform code to read the SCU CPU status\n>> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n>> ARM: dts: meson8: add support for booting the secondary CPU cores\n> @Russel: should Kevin take all patches including the two smp_scu ones?\n> or do you want to take them through your own tree?\n\nWith Russell's ack, I can take the series via the amlogic tree. But I'm\nalso fine if Russell wants to take the arch/arm/* via his tree, and I\nwill just queue up the DT.\n\nKevin\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=baylibre-com.20150623.gappssmtp.com\n\theader.i=@baylibre-com.20150623.gappssmtp.com header.b=\"UuG+uBLd\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y82qP0PcLz9t3R\n\tfor ;\n\tSat, 7 Oct 2017 08:30:24 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1752729AbdJFVaX (ORCPT\n\t);\n\tFri, 6 Oct 2017 17:30:23 -0400","from mail-pf0-f176.google.com ([209.85.192.176]:49151 \"EHLO\n\tmail-pf0-f176.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751618AbdJFVaU (ORCPT\n\t); Fri, 6 Oct 2017 17:30:20 -0400","by mail-pf0-f176.google.com with SMTP id n24so10128534pfk.5\n\tfor ;\n\tFri, 06 Oct 2017 14:30:19 -0700 (PDT)","from localhost (c-98-203-232-209.hsd1.wa.comcast.net.\n\t[98.203.232.209]) by smtp.gmail.com with ESMTPSA id\n\tl12sm3999083pgr.10.2017.10.06.14.30.17\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tFri, 06 Oct 2017 14:30:17 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=baylibre-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:organization:references:date:in-reply-to\n\t:message-id:user-agent:mime-version:content-transfer-encoding;\n\tbh=A3RwkwoUc6bylFRYuVgeGDHkvS1jEOnDdplcGiKdNII=;\n\tb=UuG+uBLdoQ5oDswHzSYFczvs+hfe/nI0U5eRt4EEoL19PWVy4HFFFkjMu6s1bkfIg4\n\tJYTHuJXjtf60kwuoeagNYeSXMG69nbwK/HpcKCyFYdyGWPlIEyq0X2E3BjSVxb1HZPTo\n\tvx94+yjwshZFqTpgBOn+nC8P48XH98LQ/RDETiPb1Jr72V3JgLoihnUkeKlLcQEvhEtX\n\tsrZUB4hEpTZ8fAyvs0NgbKyvkUTVpn8VhmkCqdPCHjFVu4W1Q3IWgUB2OFOgu8xZ3qB+\n\tD6BATgdxoyAc1F8g5Y7tw1q8jqHHZJ5hc10gYUx769D3n9RCCQlPOkm+BKhIl5PNwqkb\n\tMvNw==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:organization:references:date\n\t:in-reply-to:message-id:user-agent:mime-version\n\t:content-transfer-encoding;\n\tbh=A3RwkwoUc6bylFRYuVgeGDHkvS1jEOnDdplcGiKdNII=;\n\tb=kWtZspdDurHH4RgSiCIFLA5jp82Ln2GaqawArOX4OLdk/lYDG9B/AX6HE3v22bXxtR\n\tOGq7VwPJtH8cTeYJIblPF9Xu9XFeE/FpuowZ2Hrxon2C7SMsCfUUGBoHYBg9CnRjmEht\n\tBeFwDTonPZLQVkJaWZdtcU3a1fkD50UE1f5/FUn3/oUUeT3t4kpD9Dktd0LckWVZaQxL\n\tpxMSa4orV4j2zi+qJVke8IhXTET3rxKNzFc8+Njzx9P//8RLcIMdKO/2Cyjo3jfZhx7S\n\tDl52BRxK6XHKpCkL/AXgkCKreGgERHW2zGlgwt8+ygbsqQUyGTjFH5Yp3CeEG5af9dQ+\n\tjWzQ==","X-Gm-Message-State":"AMCzsaWbPLIXRuZmaaXxGk48sjuhLMdUHjVoemHq4UHta7S8isCPQti0\n\trZzRU76xvEo3m2gMMWnhs7OoYQ==","X-Google-Smtp-Source":"AOwi7QALLTEPNvr/58S8G/VT8LA61+gJxg902d0xcErlF0v6vs0KyMY2QDSlvs1R0KVBYbWLJeZl/g==","X-Received":"by 10.99.55.1 with SMTP id e1mr2990828pga.175.1507325419293;\n\tFri, 06 Oct 2017 14:30:19 -0700 (PDT)","From":"Kevin Hilman ","To":"Martin Blumenstingl ,\n\tRussell King ","Cc":"linux@armlinux.org.uk, carlo@caione.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tlinux-amlogic@lists.infradead.org, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org, arnd@arndb.de, mark.rutland@arm.com,\n\tf.fainelli@gmail.com","Subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","Organization":"BayLibre","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t","Date":"Fri, 06 Oct 2017 14:30:05 -0700","In-Reply-To":"\n\t(Martin Blumenstingl's message of \"Sun, 1 Oct 2017 14:19:11 +0200\")","Message-ID":"<7hpoa07yn6.fsf@baylibre.com>","User-Agent":"Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux)","MIME-Version":"1.0","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1791780,"web_url":"http://patchwork.ozlabs.org/comment/1791780/","msgid":"","list_archive_url":null,"date":"2017-10-20T22:14:28","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"content":"Hi Russel,\n\nOn Fri, Oct 6, 2017 at 11:30 PM, Kevin Hilman wrote:\n> Martin Blumenstingl writes:\n>\n>> Hello Russel, Hi Kevin,\n>>\n>> On Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n>> wrote:\n>>> This patchset adds support for booting the secondary CPU cores (and\n>>> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n>>> It is based on an earlier version from Carlo Caione - this helped me\n>>> a lot to get a better understanding of how SMP/CPU hotplug works\n>>> (compared to the code found in Amlogic's GPL kernel sources from\n>>> year 2015).\n>>>\n>>> Changes since v6 from [6]:\n>>> - rebased on top of v4.14-rc1 (which only corrected some line\n>>> numbers in the SCU patches)\n>> it's been two weeks since v6 and since then Linus Lüssing has\n>> confirmed that this works fine on his Odroid-C1 as well (many thanks\n>> for testing!): [7]\n>>\n>>> Changes since v5 from [5]:\n>>> - dropped dependency on another patch series (for the clock\n>>> controller's embedded reset controller, which is needed to boot\n>>> the secondary CPUs) from the cover-letter as that series is now\n>>> merged\n>>> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n>>> Russell King for spotting these). removed the paragraph about\n>>> preemption, cache coherency and interrupts as we're powering on\n>>> a CPU core (the text was copied from the original scu_power_mode\n>>> but simply not adjusted). also changed \"Set the executing CPUs\"\n>>> to \"Set the given (logical) CPU's\" as we're not modifying the\n>>> current CPU. this affects only patch #2\n>>> - extended the commit message of patch #3 with a short sentence\n>>> about why SCU_CPU_STATUS_MASK was introduced\n>>>\n>>> Changes since v4 from [4]:\n>>> - use __pa_symbol(secondary_startup) instead of\n>>> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n>>> (affects patch #4)\n>>> - (cover-letter) removed dependency on my other patch\n>>> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n>>> was merged into Kevin's Amlogic repo today\n>>> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n>>> lines\") again because the reset controller series exposes the\n>>> preprocessor macros now directly, see [1]\n>>> - refreshed the .dts patches so they now include the new header for\n>>> the reset line preprocessor macros\n>>>\n>>> Changes since v3 from [3]:\n>>> - added Rob's ACK to patch #1\n>>> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n>>> - removed all \"pen\" code from patch #4 as that code was not needed\n>>> at all (it was left-over while trying to fix Meson8 secondary CPU\n>>> boot - which turned out to have nothing to do with this \"pen\" code)\n>>> - removed all memory barrier operations as they were added based on\n>>> the code in the Amlogic GPL kernel tree (while trying to fix the\n>>> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n>>> still works fine with these on my Meson8m2 and Meson8b boards.\n>>> - added PATCH #5 as we now have to export the reset identifiers\n>>> (just like we do it with the clock identifiers / preprocessor\n>>> macros) - this is the result of a change in the reset controller\n>>> patch in version 2, see [1]\n>>> - use the reset line preprocessor macros (from patch #5) in patches\n>>> #6 and #7\n>>>\n>>> Changes since v2 from [0]:\n>>> - added support for Meson8 (which requires a slightly different\n>>> enable-method)\n>>> - implemented CPU hotplug support which allows taking a CPU core\n>>> offline for both, Meson8 and Meson8b\n>>> - add a function to smp_scu.c which allows enabling a CPU core from\n>>> a different CPU (previously only the power mode for the current CPU\n>>> could be changed). Without this the CPU cores on Meson8 won't come\n>>> up (Amlogic's vendor GPL kernel sources also enable power through\n>>> SCU as very first step for Meson8b as well)\n>>> - add a function to smp_scu.c to get the power status of a CPU core\n>>> (which is needed because the code in .cpu_kill needs to wait until\n>>> the core is actually powered off)\n>>> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n>>> as it is already applied (for both, Meson8 and Meson8b)\n>>> - dropped the patches which implement the reset controller which is\n>>> built into the clock-controller, these are a separate series: [1]\n>>> - moved the enable-method property to each CPU node\n>>>\n>>>\n>>> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n>>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n>>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n>>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n>>> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n>>> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n>>> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n>>>\n>>> Carlo Caione (2):\n>>> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n>>> ARM: dts: meson8b: add support for booting the secondary CPU cores\n>>>\n>>> Martin Blumenstingl (4):\n>>> ARM: smp_scu: add a helper for powering on a specific CPU\n>>> ARM: smp_scu: allow the platform code to read the SCU CPU status\ncould you please have a look at these two patches? it would be great\nif you could give feedback on these, because they are needed for SMP\nsupport on the Amlogic Meson8 and Meson8b platforms\n\n>>> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n>>> ARM: dts: meson8: add support for booting the secondary CPU cores\n>> @Russel: should Kevin take all patches including the two smp_scu ones?\n>> or do you want to take them through your own tree?\n>\n> With Russell's ack, I can take the series via the amlogic tree. But I'm\n> also fine if Russell wants to take the arch/arm/* via his tree, and I\n> will just queue up the DT.\nplease also let Kevin know if you would like him to take these patches\nthrough the amlogic tree\n\nthank you in advance!\n\n\nRegards\nMartin\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=googlemail.com header.i=@googlemail.com\n\theader.b=\"V4M/Xhe5\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yJg8C4fdnz9t3H\n\tfor ;\n\tSat, 21 Oct 2017 09:14:51 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751721AbdJTWOu (ORCPT\n\t);\n\tFri, 20 Oct 2017 18:14:50 -0400","from mail-io0-f196.google.com ([209.85.223.196]:52922 \"EHLO\n\tmail-io0-f196.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751498AbdJTWOt (ORCPT\n\t); Fri, 20 Oct 2017 18:14:49 -0400","by mail-io0-f196.google.com with SMTP id f20so14697239ioj.9\n\tfor ;\n\tFri, 20 Oct 2017 15:14:49 -0700 (PDT)","by 10.2.151.236 with HTTP; Fri, 20 Oct 2017 15:14:28 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=googlemail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc:content-transfer-encoding;\n\tbh=LCTSbx/hpv6KyjEd9D6ikgrUsHIkCQTHx8c4mmYNSk8=;\n\tb=V4M/Xhe5PPxNCZizSAl3yZN38fAzXDfryisYhWIK8XAPrmg0+jmcy7CHzMfcAEP4PF\n\tTu140ZDqrfYd9AUG2w7NeXM9YuFTkaSnGFp3UOzVwpXLUfFXvzwXtsn40ywN+cgwAPZW\n\tEBDrXDjp7UhTxOCsVo4z4IDcGNm4C96jBBKgIsrOxtwc/tYJlCUY1qH+GyURuDqVOz02\n\t0TJQEwOfM2KHbg+FL3fYOoGDuo6MfGhJXzuTRpKcCwQhXmM/y4oaDZfP6Ubnl/7QsLX/\n\tA4zEIYrS78Q7j9+JFmZp1lpVW95eQbt7Ec7m/N17IHEDdV5hgjg2Oij9Hw/50MJSEENt\n\tjwbQ==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc:content-transfer-encoding;\n\tbh=LCTSbx/hpv6KyjEd9D6ikgrUsHIkCQTHx8c4mmYNSk8=;\n\tb=oz5skqHa1xJBmMRq5zFDcbaq03zEbGyuDDj0l3Fx8WBib1JyVShRKFHXi5HXsVNBOx\n\tiutguk2CdWOPeyyC0RxEOKIDe9b1GZ6ssCFu1p8k6n4R+d3WL4j16XNku3HO+X89/4L0\n\tcP+oVQhiPw6fnWFh9BVsevEwsGZzBDE+tXZGwggVMmqrjXNwTwTmMIDMfbeJjJwCb9BO\n\tKzanIOpPOPmS9EYXvXwFKGN26+AIH0wf5QCDsS/k+EZqW3h9ME99nCGM9IOHV3YWv/hC\n\teYtdCZwO9g1SGJMttg1GkJdRx8/8KL1F2jbj06E5l6f/1k9BPGFJ+dQUfBluMfCwUikJ\n\tstgg==","X-Gm-Message-State":"AMCzsaVkPxa6gjt/4S+A6KGlWSGCNZnXCcRl7GKpEzUw2P+QcoVpmLfj\n\tZPpSrIdMixWM6X5ioW3nNgai9N3/Ffu1pt6q8BI=","X-Google-Smtp-Source":"ABhQp+RrxaU8QUTRakyhToadr1tABdkmo8LCV8Xz2m9hendZ6TC4ONeK2iIzQEXcFICwrfgkmUW+GQbjSs2CfUagjrA=","X-Received":"by 10.107.107.21 with SMTP id g21mr8060474ioc.101.1508537688476; \n\tFri, 20 Oct 2017 15:14:48 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<7hpoa07yn6.fsf@baylibre.com>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t\n\t<7hpoa07yn6.fsf@baylibre.com>","From":"Martin Blumenstingl ","Date":"Sat, 21 Oct 2017 00:14:28 +0200","Message-ID":"","Subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","To":"Russell King ,\n\tlinux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk","Cc":"Kevin Hilman , carlo@caione.org,\n\tlinux-amlogic@lists.infradead.org, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org, arnd@arndb.de, mark.rutland@arm.com,\n\tf.fainelli@gmail.com","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1792458,"web_url":"http://patchwork.ozlabs.org/comment/1792458/","msgid":"<20171023094921.GO20805@n2100.armlinux.org.uk>","list_archive_url":null,"date":"2017-10-23T09:49:21","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":69080,"url":"http://patchwork.ozlabs.org/api/people/69080/","name":"Russell King (Oracle)","email":"linux@armlinux.org.uk"},"content":"On Sat, Oct 21, 2017 at 12:14:28AM +0200, Martin Blumenstingl wrote:\n> Hi Russel,\n> \n> On Fri, Oct 6, 2017 at 11:30 PM, Kevin Hilman wrote:\n> > Martin Blumenstingl writes:\n> >\n> >> Hello Russel, Hi Kevin,\n> >>\n> >> On Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n> >> wrote:\n> >>> This patchset adds support for booting the secondary CPU cores (and\n> >>> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n> >>> It is based on an earlier version from Carlo Caione - this helped me\n> >>> a lot to get a better understanding of how SMP/CPU hotplug works\n> >>> (compared to the code found in Amlogic's GPL kernel sources from\n> >>> year 2015).\n> >>>\n> >>> Changes since v6 from [6]:\n> >>> - rebased on top of v4.14-rc1 (which only corrected some line\n> >>> numbers in the SCU patches)\n> >> it's been two weeks since v6 and since then Linus Lüssing has\n> >> confirmed that this works fine on his Odroid-C1 as well (many thanks\n> >> for testing!): [7]\n> >>\n> >>> Changes since v5 from [5]:\n> >>> - dropped dependency on another patch series (for the clock\n> >>> controller's embedded reset controller, which is needed to boot\n> >>> the secondary CPUs) from the cover-letter as that series is now\n> >>> merged\n> >>> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n> >>> Russell King for spotting these). removed the paragraph about\n> >>> preemption, cache coherency and interrupts as we're powering on\n> >>> a CPU core (the text was copied from the original scu_power_mode\n> >>> but simply not adjusted). also changed \"Set the executing CPUs\"\n> >>> to \"Set the given (logical) CPU's\" as we're not modifying the\n> >>> current CPU. this affects only patch #2\n> >>> - extended the commit message of patch #3 with a short sentence\n> >>> about why SCU_CPU_STATUS_MASK was introduced\n> >>>\n> >>> Changes since v4 from [4]:\n> >>> - use __pa_symbol(secondary_startup) instead of\n> >>> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n> >>> (affects patch #4)\n> >>> - (cover-letter) removed dependency on my other patch\n> >>> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n> >>> was merged into Kevin's Amlogic repo today\n> >>> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n> >>> lines\") again because the reset controller series exposes the\n> >>> preprocessor macros now directly, see [1]\n> >>> - refreshed the .dts patches so they now include the new header for\n> >>> the reset line preprocessor macros\n> >>>\n> >>> Changes since v3 from [3]:\n> >>> - added Rob's ACK to patch #1\n> >>> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n> >>> - removed all \"pen\" code from patch #4 as that code was not needed\n> >>> at all (it was left-over while trying to fix Meson8 secondary CPU\n> >>> boot - which turned out to have nothing to do with this \"pen\" code)\n> >>> - removed all memory barrier operations as they were added based on\n> >>> the code in the Amlogic GPL kernel tree (while trying to fix the\n> >>> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n> >>> still works fine with these on my Meson8m2 and Meson8b boards.\n> >>> - added PATCH #5 as we now have to export the reset identifiers\n> >>> (just like we do it with the clock identifiers / preprocessor\n> >>> macros) - this is the result of a change in the reset controller\n> >>> patch in version 2, see [1]\n> >>> - use the reset line preprocessor macros (from patch #5) in patches\n> >>> #6 and #7\n> >>>\n> >>> Changes since v2 from [0]:\n> >>> - added support for Meson8 (which requires a slightly different\n> >>> enable-method)\n> >>> - implemented CPU hotplug support which allows taking a CPU core\n> >>> offline for both, Meson8 and Meson8b\n> >>> - add a function to smp_scu.c which allows enabling a CPU core from\n> >>> a different CPU (previously only the power mode for the current CPU\n> >>> could be changed). Without this the CPU cores on Meson8 won't come\n> >>> up (Amlogic's vendor GPL kernel sources also enable power through\n> >>> SCU as very first step for Meson8b as well)\n> >>> - add a function to smp_scu.c to get the power status of a CPU core\n> >>> (which is needed because the code in .cpu_kill needs to wait until\n> >>> the core is actually powered off)\n> >>> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n> >>> as it is already applied (for both, Meson8 and Meson8b)\n> >>> - dropped the patches which implement the reset controller which is\n> >>> built into the clock-controller, these are a separate series: [1]\n> >>> - moved the enable-method property to each CPU node\n> >>>\n> >>>\n> >>> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n> >>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n> >>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n> >>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n> >>> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n> >>> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n> >>> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n> >>>\n> >>> Carlo Caione (2):\n> >>> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n> >>> ARM: dts: meson8b: add support for booting the secondary CPU cores\n> >>>\n> >>> Martin Blumenstingl (4):\n> >>> ARM: smp_scu: add a helper for powering on a specific CPU\n> >>> ARM: smp_scu: allow the platform code to read the SCU CPU status\n> could you please have a look at these two patches? it would be great\n> if you could give feedback on these, because they are needed for SMP\n> support on the Amlogic Meson8 and Meson8b platforms\n> \n> >>> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n> >>> ARM: dts: meson8: add support for booting the secondary CPU cores\n> >> @Russel: should Kevin take all patches including the two smp_scu ones?\n> >> or do you want to take them through your own tree?\n> >\n> > With Russell's ack, I can take the series via the amlogic tree. But I'm\n> > also fine if Russell wants to take the arch/arm/* via his tree, and I\n> > will just queue up the DT.\n> please also let Kevin know if you would like him to take these patches\n> through the amlogic tree\n\nStuff in this thread seems to be sent either over the weekend, or late\non Friday, which means it gets buried by Monday. I'll look at it now.","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=armlinux.org.uk header.i=@armlinux.org.uk\n\theader.b=\"ayp4sDEK\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yLBTX63PJz9sPk\n\tfor ;\n\tMon, 23 Oct 2017 20:50:08 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751207AbdJWJuD (ORCPT\n\t);\n\tMon, 23 Oct 2017 05:50:03 -0400","from pandora.armlinux.org.uk ([78.32.30.218]:40664 \"EHLO\n\tpandora.armlinux.org.uk\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751200AbdJWJuC (ORCPT\n\t); Mon, 23 Oct 2017 05:50:02 -0400","from n2100.armlinux.org.uk\n\t([2002:4e20:1eda:1:214:fdff:fe10:4f86]:39188)\n\tby pandora.armlinux.org.uk with esmtpsa\n\t(TLSv1:DHE-RSA-AES256-SHA:256)\n\t(Exim 4.82_1-5b7a7c0-XX) (envelope-from )\n\tid 1e6ZML-0006Ys-T0; Mon, 23 Oct 2017 10:49:26 +0100","from linux by n2100.armlinux.org.uk with local (Exim 4.76)\n\t(envelope-from )\n\tid 1e6ZMI-0001Bf-Bl; Mon, 23 Oct 2017 10:49:22 +0100"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=armlinux.org.uk; s=pandora-2014; \n\th=Sender:In-Reply-To:Content-Transfer-Encoding:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date;\n\tbh=K0NEHFuqOgVJiwlSislIsraa8MejZXyfUllN36c0QWs=; \n\tb=ayp4sDEKbEK7kI21uxE2fxanyEnLEKkZndBuoLDumj+t8WqX8oBYVmQJ0NKiEi+wcW1zL1xDG2hCSvG3SGVECOg0InimgtiC7EyB6KcUSebAcUobRLQ0yOqNscUdZKlkY9R7oVKKj6yTexCVquajkfbGFl5NtFI0ZGUbV8l4t90=;","Date":"Mon, 23 Oct 2017 10:49:21 +0100","From":"Russell King - ARM Linux ","To":"Martin Blumenstingl ","Cc":"linux-arm-kernel@lists.infradead.org,\n\tKevin Hilman , carlo@caione.org,\n\tlinux-amlogic@lists.infradead.org, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org, arnd@arndb.de, mark.rutland@arm.com,\n\tf.fainelli@gmail.com","Subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","Message-ID":"<20171023094921.GO20805@n2100.armlinux.org.uk>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t\n\t<7hpoa07yn6.fsf@baylibre.com>\n\t","MIME-Version":"1.0","Content-Type":"text/plain; charset=iso-8859-1","Content-Disposition":"inline","Content-Transfer-Encoding":"8bit","In-Reply-To":"","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1792460,"web_url":"http://patchwork.ozlabs.org/comment/1792460/","msgid":"<20171023095111.GP20805@n2100.armlinux.org.uk>","list_archive_url":null,"date":"2017-10-23T09:51:12","subject":"Re: [PATCH v7 2/6] ARM: smp_scu: add a helper for powering on a\n\tspecific CPU","submitter":{"id":69080,"url":"http://patchwork.ozlabs.org/api/people/69080/","name":"Russell King (Oracle)","email":"linux@armlinux.org.uk"},"content":"On Sun, Sep 17, 2017 at 06:45:19PM +0200, Martin Blumenstingl wrote:\n> To boot the secondary CPUs on the Amlogic Meson8/Meson8m2 (Cortex-A9)\n> and Meson8b (Cortex-A5) SoCs we have to enable SCU mode SCU_PM_NORMAL,\n> otherwise the secondary cores will not start.\n> This patch adds a scu_cpu_power_enable() function which can be used to\n> enable SCU_PM_NORMAL for a specific (logical) CPU. An internal helper\n> function is also created, to avoid code duplication with\n> scu_power_mode().\n> \n> Signed-off-by: Martin Blumenstingl \n\nAcked-by: Russell King ","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=armlinux.org.uk header.i=@armlinux.org.uk\n\theader.b=\"XXs4D7mc\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yLBWS5xDPz9sPt\n\tfor ;\n\tMon, 23 Oct 2017 20:51:48 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751209AbdJWJvr (ORCPT\n\t);\n\tMon, 23 Oct 2017 05:51:47 -0400","from pandora.armlinux.org.uk ([78.32.30.218]:40708 \"EHLO\n\tpandora.armlinux.org.uk\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751200AbdJWJvr (ORCPT\n\t); Mon, 23 Oct 2017 05:51:47 -0400","from n2100.armlinux.org.uk\n\t([2001:4d48:ad52:3201:214:fdff:fe10:4f86]:52102)\n\tby pandora.armlinux.org.uk with esmtpsa\n\t(TLSv1:DHE-RSA-AES256-SHA:256)\n\t(Exim 4.82_1-5b7a7c0-XX) (envelope-from )\n\tid 1e6ZO8-0006Zh-6J; Mon, 23 Oct 2017 10:51:16 +0100","from linux by n2100.armlinux.org.uk with local (Exim 4.76)\n\t(envelope-from )\n\tid 1e6ZO4-0001D4-NO; Mon, 23 Oct 2017 10:51:12 +0100"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=armlinux.org.uk; s=pandora-2014; \n\th=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date;\n\tbh=oc/pjCqpy8onVXCm7yEUsgoDRzKfzeCxrsnv8ycwT6s=; \n\tb=XXs4D7mc25u540wPc346rwnlGJv1JbyggoOIMDLkyuwmb1LP8x7inac14FnCZRy3TbrZgjPlPrJ4a9qck1vrHHKx2kbencC9CKyuWHJmm/RzjtC6Um6Jt+864zxhZi6QAspkat5pDw1brZoRLL7hDBieTuDE5DVEI7a3erIMKxE=;","Date":"Mon, 23 Oct 2017 10:51:12 +0100","From":"Russell King - ARM Linux ","To":"Martin Blumenstingl ","Cc":"linux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, khilman@baylibre.com,\n\tcarlo@caione.org, robh+dt@kernel.org, devicetree@vger.kernel.org,\n\tarnd@arndb.de, mark.rutland@arm.com, f.fainelli@gmail.com","Subject":"Re: [PATCH v7 2/6] ARM: smp_scu: add a helper for powering on a\n\tspecific CPU","Message-ID":"<20171023095111.GP20805@n2100.armlinux.org.uk>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t<20170917164523.6970-3-martin.blumenstingl@googlemail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170917164523.6970-3-martin.blumenstingl@googlemail.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1792463,"web_url":"http://patchwork.ozlabs.org/comment/1792463/","msgid":"<20171023095450.GQ20805@n2100.armlinux.org.uk>","list_archive_url":null,"date":"2017-10-23T09:54:50","subject":"Re: [PATCH v7 3/6] ARM: smp_scu: allow the platform code to read the\n\tSCU CPU status","submitter":{"id":69080,"url":"http://patchwork.ozlabs.org/api/people/69080/","name":"Russell King (Oracle)","email":"linux@armlinux.org.uk"},"content":"On Sun, Sep 17, 2017 at 06:45:20PM +0200, Martin Blumenstingl wrote:\n> On Amlogic Meson8 / Meson8m2 (both Cortex-A9) and Meson8b (Cortex-A5)\n> the CPU hotplug code needs to wait until the SCU status of the CPU that\n> is being taken offline is SCU_PM_POWEROFF.\n> Provide a utility function (which can be invoked for example from\n> .cpu_kill()) which allows reading the SCU status of a CPU.\n> \n> While here, replace the magic number 0x3 with a preprocessor macro\n> (SCU_CPU_STATUS_MASK) so we don't have to duplicate this magic number in\n> the new function.\n> \n> Signed-off-by: Martin Blumenstingl \n\nAcked-by: Russell King \n\n> ---\n> arch/arm/include/asm/smp_scu.h | 6 ++++++\n> arch/arm/kernel/smp_scu.c | 18 +++++++++++++++++-\n> 2 files changed, 23 insertions(+), 1 deletion(-)\n> \n> diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h\n> index 4c47bdfd4f61..1529d1ae2f8d 100644\n> --- a/arch/arm/include/asm/smp_scu.h\n> +++ b/arch/arm/include/asm/smp_scu.h\n> @@ -28,6 +28,7 @@ static inline unsigned long scu_a9_get_base(void)\n> unsigned int scu_get_core_count(void __iomem *);\n> int scu_power_mode(void __iomem *, unsigned int);\n> int scu_cpu_power_enable(void __iomem *, unsigned int);\n> +int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu);\n> #else\n> static inline unsigned int scu_get_core_count(void __iomem *scu_base)\n> {\n> @@ -42,6 +43,11 @@ static inline int scu_cpu_power_enable(void __iomem *scu_base,\n> {\n> \treturn -EINVAL;\n> }\n> +static inline int scu_get_cpu_power_mode(void __iomem *scu_base,\n> +\t\t\t\t\t unsigned int logical_cpu)\n> +{\n> +\treturn -EINVAL;\n> +}\n> #endif\n> \n> #if defined(CONFIG_SMP) && defined(CONFIG_HAVE_ARM_SCU)\n> diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c\n> index 1d549c16b5fc..c6b33074c393 100644\n> --- a/arch/arm/kernel/smp_scu.c\n> +++ b/arch/arm/kernel/smp_scu.c\n> @@ -21,6 +21,7 @@\n> #define SCU_STANDBY_ENABLE\t(1 << 5)\n> #define SCU_CONFIG\t\t0x04\n> #define SCU_CPU_STATUS\t\t0x08\n> +#define SCU_CPU_STATUS_MASK\tGENMASK(1, 0)\n> #define SCU_INVALIDATE\t\t0x0c\n> #define SCU_FPGA_REVISION\t0x10\n> \n> @@ -82,7 +83,8 @@ static int scu_set_power_mode_internal(void __iomem *scu_base,\n> \tif (mode > 3 || mode == 1 || cpu > 3)\n> \t\treturn -EINVAL;\n> \n> -\tval = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu) & ~0x03;\n> +\tval = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);\n> +\tval &= ~SCU_CPU_STATUS_MASK;\n> \tval |= mode;\n> \twriteb_relaxed(val, scu_base + SCU_CPU_STATUS + cpu);\n> \n> @@ -109,3 +111,17 @@ int scu_cpu_power_enable(void __iomem *scu_base, unsigned int cpu)\n> {\n> \treturn scu_set_power_mode_internal(scu_base, cpu, SCU_PM_NORMAL);\n> }\n> +\n> +int scu_get_cpu_power_mode(void __iomem *scu_base, unsigned int logical_cpu)\n> +{\n> +\tunsigned int val;\n> +\tint cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(logical_cpu), 0);\n> +\n> +\tif (cpu > 3)\n> +\t\treturn -EINVAL;\n> +\n> +\tval = readb_relaxed(scu_base + SCU_CPU_STATUS + cpu);\n> +\tval &= SCU_CPU_STATUS_MASK;\n> +\n> +\treturn val;\n> +}\n> -- \n> 2.14.1\n>","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=armlinux.org.uk header.i=@armlinux.org.uk\n\theader.b=\"quwP2dtM\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yLBbm5DLvz9sPk\n\tfor ;\n\tMon, 23 Oct 2017 20:55:32 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751250AbdJWJzb (ORCPT\n\t);\n\tMon, 23 Oct 2017 05:55:31 -0400","from pandora.armlinux.org.uk ([78.32.30.218]:40770 \"EHLO\n\tpandora.armlinux.org.uk\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751200AbdJWJzb (ORCPT\n\t); Mon, 23 Oct 2017 05:55:31 -0400","from n2100.armlinux.org.uk\n\t([2001:4d48:ad52:3201:214:fdff:fe10:4f86]:52141)\n\tby pandora.armlinux.org.uk with esmtpsa\n\t(TLSv1:DHE-RSA-AES256-SHA:256)\n\t(Exim 4.82_1-5b7a7c0-XX) (envelope-from )\n\tid 1e6ZRg-0006al-1s; Mon, 23 Oct 2017 10:54:56 +0100","from linux by n2100.armlinux.org.uk with local (Exim 4.76)\n\t(envelope-from )\n\tid 1e6ZRb-0001Fn-Kc; Mon, 23 Oct 2017 10:54:51 +0100"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=armlinux.org.uk; s=pandora-2014; \n\th=Sender:In-Reply-To:Content-Type:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date;\n\tbh=C4cjqh5CCgOXG5irOG2j8x2dLgtuoaLrKRZNL+W2GA0=; \n\tb=quwP2dtMu/T4ZRyVJNp2I9JqMPTYaSKAMO9YqDLGp4j9w1xfrrnw9ac/ewYQmGsOLoUifMypaC5jZYd2D6SH/XdVq5ZeUnt4Mc3EsS5RZwYy33cpmTllCfM76IcIRJ3f5KJ440HCvwCbqsGuFoPMnPSCCZky2kVZ1l1tPFGo9nM=;","Date":"Mon, 23 Oct 2017 10:54:50 +0100","From":"Russell King - ARM Linux ","To":"Martin Blumenstingl ","Cc":"linux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, khilman@baylibre.com,\n\tcarlo@caione.org, robh+dt@kernel.org, devicetree@vger.kernel.org,\n\tarnd@arndb.de, mark.rutland@arm.com, f.fainelli@gmail.com","Subject":"Re: [PATCH v7 3/6] ARM: smp_scu: allow the platform code to read the\n\tSCU CPU status","Message-ID":"<20171023095450.GQ20805@n2100.armlinux.org.uk>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t<20170917164523.6970-4-martin.blumenstingl@googlemail.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<20170917164523.6970-4-martin.blumenstingl@googlemail.com>","User-Agent":"Mutt/1.5.23 (2014-03-12)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1793928,"web_url":"http://patchwork.ozlabs.org/comment/1793928/","msgid":"","list_archive_url":null,"date":"2017-10-25T21:05:09","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":66366,"url":"http://patchwork.ozlabs.org/api/people/66366/","name":"Martin Blumenstingl","email":"martin.blumenstingl@googlemail.com"},"content":"Hi Russel,\n\nOn Mon, Oct 23, 2017 at 11:49 AM, Russell King - ARM Linux\n wrote:\n> On Sat, Oct 21, 2017 at 12:14:28AM +0200, Martin Blumenstingl wrote:\n>> Hi Russel,\n>>\n>> On Fri, Oct 6, 2017 at 11:30 PM, Kevin Hilman wrote:\n>> > Martin Blumenstingl writes:\n>> >\n>> >> Hello Russel, Hi Kevin,\n>> >>\n>> >> On Sun, Sep 17, 2017 at 6:45 PM, Martin Blumenstingl\n>> >> wrote:\n>> >>> This patchset adds support for booting the secondary CPU cores (and\n>> >>> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n>> >>> It is based on an earlier version from Carlo Caione - this helped me\n>> >>> a lot to get a better understanding of how SMP/CPU hotplug works\n>> >>> (compared to the code found in Amlogic's GPL kernel sources from\n>> >>> year 2015).\n>> >>>\n>> >>> Changes since v6 from [6]:\n>> >>> - rebased on top of v4.14-rc1 (which only corrected some line\n>> >>> numbers in the SCU patches)\n>> >> it's been two weeks since v6 and since then Linus Lüssing has\n>> >> confirmed that this works fine on his Odroid-C1 as well (many thanks\n>> >> for testing!): [7]\n>> >>\n>> >>> Changes since v5 from [5]:\n>> >>> - dropped dependency on another patch series (for the clock\n>> >>> controller's embedded reset controller, which is needed to boot\n>> >>> the secondary CPUs) from the cover-letter as that series is now\n>> >>> merged\n>> >>> - fix incorrect documentation of scu_cpu_power_enable (thanks to\n>> >>> Russell King for spotting these). removed the paragraph about\n>> >>> preemption, cache coherency and interrupts as we're powering on\n>> >>> a CPU core (the text was copied from the original scu_power_mode\n>> >>> but simply not adjusted). also changed \"Set the executing CPUs\"\n>> >>> to \"Set the given (logical) CPU's\" as we're not modifying the\n>> >>> current CPU. this affects only patch #2\n>> >>> - extended the commit message of patch #3 with a short sentence\n>> >>> about why SCU_CPU_STATUS_MASK was introduced\n>> >>>\n>> >>> Changes since v4 from [4]:\n>> >>> - use __pa_symbol(secondary_startup) instead of\n>> >>> virt_to_phys(secondary_startup) as suggested by Florian Fainelli\n>> >>> (affects patch #4)\n>> >>> - (cover-letter) removed dependency on my other patch\n>> >>> \"ARM: dts: meson: add a node which describes the SRAM\" [2] as that\n>> >>> was merged into Kevin's Amlogic repo today\n>> >>> - dropped patch #5 (\"clk: meson: meson8b: export the CPU soft reset\n>> >>> lines\") again because the reset controller series exposes the\n>> >>> preprocessor macros now directly, see [1]\n>> >>> - refreshed the .dts patches so they now include the new header for\n>> >>> the reset line preprocessor macros\n>> >>>\n>> >>> Changes since v3 from [3]:\n>> >>> - added Rob's ACK to patch #1\n>> >>> - replaced a msleep(10) with usleep_range(10000, 15000) in patch #4\n>> >>> - removed all \"pen\" code from patch #4 as that code was not needed\n>> >>> at all (it was left-over while trying to fix Meson8 secondary CPU\n>> >>> boot - which turned out to have nothing to do with this \"pen\" code)\n>> >>> - removed all memory barrier operations as they were added based on\n>> >>> the code in the Amlogic GPL kernel tree (while trying to fix the\n>> >>> Meson8 secondary CPU boot - just like the \"pen\" code). Everything\n>> >>> still works fine with these on my Meson8m2 and Meson8b boards.\n>> >>> - added PATCH #5 as we now have to export the reset identifiers\n>> >>> (just like we do it with the clock identifiers / preprocessor\n>> >>> macros) - this is the result of a change in the reset controller\n>> >>> patch in version 2, see [1]\n>> >>> - use the reset line preprocessor macros (from patch #5) in patches\n>> >>> #6 and #7\n>> >>>\n>> >>> Changes since v2 from [0]:\n>> >>> - added support for Meson8 (which requires a slightly different\n>> >>> enable-method)\n>> >>> - implemented CPU hotplug support which allows taking a CPU core\n>> >>> offline for both, Meson8 and Meson8b\n>> >>> - add a function to smp_scu.c which allows enabling a CPU core from\n>> >>> a different CPU (previously only the power mode for the current CPU\n>> >>> could be changed). Without this the CPU cores on Meson8 won't come\n>> >>> up (Amlogic's vendor GPL kernel sources also enable power through\n>> >>> SCU as very first step for Meson8b as well)\n>> >>> - add a function to smp_scu.c to get the power status of a CPU core\n>> >>> (which is needed because the code in .cpu_kill needs to wait until\n>> >>> the core is actually powered off)\n>> >>> - dropped patch \"ARM: DTS: meson8b: Extend L2 cache controller node\"\n>> >>> as it is already applied (for both, Meson8 and Meson8b)\n>> >>> - dropped the patches which implement the reset controller which is\n>> >>> built into the clock-controller, these are a separate series: [1]\n>> >>> - moved the enable-method property to each CPU node\n>> >>>\n>> >>>\n>> >>> [0] http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/390355.html\n>> >>> [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004456.html\n>> >>> [2] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004282.html\n>> >>> [3] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004297.html\n>> >>> [4] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004354.html\n>> >>> [5] http://lists.infradead.org/pipermail/linux-amlogic/2017-July/004460.html\n>> >>> [6] http://lists.infradead.org/pipermail/linux-amlogic/2017-August/004588.html\n>> >>>\n>> >>> Carlo Caione (2):\n>> >>> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n>> >>> ARM: dts: meson8b: add support for booting the secondary CPU cores\n>> >>>\n>> >>> Martin Blumenstingl (4):\n>> >>> ARM: smp_scu: add a helper for powering on a specific CPU\n>> >>> ARM: smp_scu: allow the platform code to read the SCU CPU status\n>> could you please have a look at these two patches? it would be great\n>> if you could give feedback on these, because they are needed for SMP\n>> support on the Amlogic Meson8 and Meson8b platforms\n>>\n>> >>> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n>> >>> ARM: dts: meson8: add support for booting the secondary CPU cores\n>> >> @Russel: should Kevin take all patches including the two smp_scu ones?\n>> >> or do you want to take them through your own tree?\n>> >\n>> > With Russell's ack, I can take the series via the amlogic tree. But I'm\n>> > also fine if Russell wants to take the arch/arm/* via his tree, and I\n>> > will just queue up the DT.\n>> please also let Kevin know if you would like him to take these patches\n>> through the amlogic tree\n>\n> Stuff in this thread seems to be sent either over the weekend, or late\n> on Friday, which means it gets buried by Monday. I'll look at it now.\nthank you for reviewing my patches!\n\nI do this in my spare time - so I typically end up having all bugs\nfixed at some point during the weekend\nhowever, you still found my patches - problem solved. :)\n\n\nThank you!\nRegards\nMartin\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=googlemail.com header.i=@googlemail.com\n\theader.b=\"V4IEl7+q\"; dkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yMjMw4dwpz9t5C\n\tfor ;\n\tThu, 26 Oct 2017 08:05:32 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751753AbdJYVFb (ORCPT\n\t);\n\tWed, 25 Oct 2017 17:05:31 -0400","from mail-it0-f66.google.com ([209.85.214.66]:48145 \"EHLO\n\tmail-it0-f66.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751668AbdJYVFa (ORCPT\n\t); Wed, 25 Oct 2017 17:05:30 -0400","by mail-it0-f66.google.com with SMTP id c3so2767599itc.3\n\tfor ;\n\tWed, 25 Oct 2017 14:05:30 -0700 (PDT)","by 10.2.151.236 with HTTP; Wed, 25 Oct 2017 14:05:09 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=googlemail.com; s=20161025;\n\th=mime-version:in-reply-to:references:from:date:message-id:subject:to\n\t:cc:content-transfer-encoding;\n\tbh=TDQkYTcyx6N25GWQm/I/6m2rM87FoCCZPTfvvcBq3WI=;\n\tb=V4IEl7+qLnEQSmIBJs1rgu5yq/gZfKiVd/wYuBW4/mCvfoQ2zwulnLV7rYQ7JRNC1Y\n\tIJBUISVvJtYjVQ2MO3cj0H2EbBaCEbTiNPjjzoL5uXIUta8c248nPPGhdDqlhsx28bnW\n\tYMkULgmvDySA54CJY/J3orCAIPRuKEkIVkUq9/or87ZRoZMtqu9Z+Vw0p971f5PcqaMh\n\t6/pnJmmWUanyYTf/xxSZAETPLu8w1t6cdoipfUPALdm0PeAE/IpaVhecDBcEr+W1OJJD\n\tXHxt6OVyNgO9z3gVzE2l4lcgF5M5UzIHBDkgLaFURY9S50xEJIEFRA1/10rH1lGxSbxN\n\t5J5w==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:mime-version:in-reply-to:references:from:date\n\t:message-id:subject:to:cc:content-transfer-encoding;\n\tbh=TDQkYTcyx6N25GWQm/I/6m2rM87FoCCZPTfvvcBq3WI=;\n\tb=Jwrz+b+XAxwLMtMw1ltRpkt3WjOtt1Sj2DKeJspOinXIqNj3Z+x6erfCLxBHSzdpxo\n\t6UhgJ7Jd4xRnkRcM2K9TchMnrRMPoV9wrbo7Xt4BLdL04t+a6KjyvcB7EVkcWkrGMexx\n\t29W9aczSsiqgHI2rmmvif/syET/BRN3pA/yl8Y4HQ/mxdoCbONIrjP5Lze/8/Dcs8T/C\n\tuo1JLzUINj1oovoEcEw05LN6H/eH2+ypSzeVxxOYGsLP7P8ue+x5A5J7UmZiCF7eoRM/\n\twL4n3APKyutNxeIaVfuqChTFti3iaSO4g407ZZUY/BSqBFJFIInXTtcub+6V0R4ldAWF\n\tM4Wg==","X-Gm-Message-State":"AMCzsaUCJWOg/r2d6266VJVcPOJ4Mm9wBAv7uqX+MwfWQ1iL9GYoqrt6\n\tv/jvzw7Krj/AECxV0jfyLdPR4n0PjJ2y7WLg6qQ=","X-Google-Smtp-Source":"ABhQp+ToY0rTi9ReH+kdDSsKfPi5VKKILEO7f07vAt6ObG2WZFRznZZPQVQrM6VRxoAyt0qovrHVmUpes89rAVjAjBQ=","X-Received":"by 10.36.76.1 with SMTP id a1mr4005146itb.94.1508965529483; Wed,\n\t25 Oct 2017 14:05:29 -0700 (PDT)","MIME-Version":"1.0","In-Reply-To":"<20171023094921.GO20805@n2100.armlinux.org.uk>","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t\n\t<7hpoa07yn6.fsf@baylibre.com>\n\t\n\t<20171023094921.GO20805@n2100.armlinux.org.uk>","From":"Martin Blumenstingl ","Date":"Wed, 25 Oct 2017 23:05:09 +0200","Message-ID":"","Subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","To":"Russell King - ARM Linux ","Cc":"linux-arm-kernel@lists.infradead.org,\n\tKevin Hilman , carlo@caione.org,\n\tlinux-amlogic@lists.infradead.org, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org, arnd@arndb.de, mark.rutland@arm.com,\n\tf.fainelli@gmail.com","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1795473,"web_url":"http://patchwork.ozlabs.org/comment/1795473/","msgid":"<7hwp3eug0k.fsf@baylibre.com>","list_archive_url":null,"date":"2017-10-29T15:31:55","subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","submitter":{"id":68189,"url":"http://patchwork.ozlabs.org/api/people/68189/","name":"Kevin Hilman","email":"khilman@baylibre.com"},"content":"Martin Blumenstingl writes:\n\n> This patchset adds support for booting the secondary CPU cores (and\n> taking them offline again) on Amlogic Meson8 and Meson8b SoCs.\n> It is based on an earlier version from Carlo Caione - this helped me\n> a lot to get a better understanding of how SMP/CPU hotplug works\n> (compared to the code found in Amlogic's GPL kernel sources from\n> year 2015).\n\n[...]\n\n> Carlo Caione (2):\n> dt-bindings: Amlogic: Add Meson8 and Meson8b SMP related documentation\n> ARM: dts: meson8b: add support for booting the secondary CPU cores\n\nApplied to v4.15/dt...\n\n> Martin Blumenstingl (4):\n> ARM: smp_scu: add a helper for powering on a specific CPU\n> ARM: smp_scu: allow the platform code to read the SCU CPU status\n> ARM: meson: Add SMP bringup code for Meson8 and Meson8b\n> ARM: dts: meson8: add support for booting the secondary CPU cores\n\nApplied to v4.15/soc with Russell's ack.\n\nThanks,\n\nKevin\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=baylibre-com.20150623.gappssmtp.com\n\theader.i=@baylibre-com.20150623.gappssmtp.com header.b=\"LrjTQ7VS\"; \n\tdkim-atps=neutral"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3yQ1nH4JHPz9t2v\n\tfor ;\n\tMon, 30 Oct 2017 02:32:03 +1100 (AEDT)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751209AbdJ2PcB (ORCPT\n\t);\n\tSun, 29 Oct 2017 11:32:01 -0400","from mail-wm0-f67.google.com ([74.125.82.67]:53791 \"EHLO\n\tmail-wm0-f67.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1751207AbdJ2PcB (ORCPT\n\t); Sun, 29 Oct 2017 11:32:01 -0400","by mail-wm0-f67.google.com with SMTP id r196so11757630wmf.2\n\tfor ;\n\tSun, 29 Oct 2017 08:32:00 -0700 (PDT)","from localhost (248.8.23.109.rev.sfr.net. [109.23.8.248])\n\tby smtp.googlemail.com with ESMTPSA id\n\ty29sm8278968wrd.3.2017.10.29.08.31.58\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 29 Oct 2017 08:31:58 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=baylibre-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:organization:references:date:in-reply-to\n\t:message-id:user-agent:mime-version;\n\tbh=yngtca9DFPWiDD3TKy+CshUmvlZ0JVjJfKpQc6Pvawo=;\n\tb=LrjTQ7VSDwbw0YwsYeDgQUBlIsey9pihx9Rp9YWh9K/vReDPBNaXLlSLbdFtI+2/N1\n\tKug1Z2ULcJiUO9oVGS/qsk23hmCG2m46jX+0iD9FkiBqvMgvsSq8eHbtL82M22I/tBbr\n\tvleLn9rr6C+nShvvk2qIwIqWsXwn2vl3c+AzDI/qAnlIdfq6Fg2U0N3TaBLS1/SEv+zJ\n\tqrxGWlbV5jRPUPK9KclkhP84OmWtrM8TD0xYlNaGVCgouBKDuOHF2xasZbNGaJDwNhpF\n\tKnZPxSRl2VyYM+bvKB2QOhT3CKJccJttMl4qsJYRgsPV/mBn5aUBl0WynLll2wn7c7rW\n\thfYA==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:organization:references:date\n\t:in-reply-to:message-id:user-agent:mime-version;\n\tbh=yngtca9DFPWiDD3TKy+CshUmvlZ0JVjJfKpQc6Pvawo=;\n\tb=Z735WZun+qqWRNu7xr8VV7GxXS3DpLb+eKlnDG/2v8qqtqQiBnCcaVeCB8X6Qo2nc5\n\t/rUlsc6SJEUrrTfA5foZ4HCKdourBdRgED7CCX8BfuLesGXErxNg8uNLV5VHHHMMocRU\n\t9fL6mF9KIGC2HeRCW9hSpftMRVga/zarp7sJBZaIlK/mkH5r23oJLLYzcihQlPp2OZeV\n\tSf/cB/r8kTsOeepvncaWaDkZp5RCU7pf7BlEVQJZT9axBZHZOru5SZfZrlgT2Y9ACBhk\n\tpnLY84mlGkVBQMWcMHrfIN16wQt8OI+g//oR38zZMCm8dX4tba/Nr/L2Av0/wa5X0t2v\n\tAKuA==","X-Gm-Message-State":"AMCzsaXnSQb+D+P+9tQ+Q4HNH7V083+QMK9fdf4WdW4eGq5y6FfKXQ37\n\t+HlXz7RYND5HeAc4nX/+iQdimA==","X-Google-Smtp-Source":"ABhQp+TpJm9hjwmeg/Wd4If1wpKfGm2WAwvzRPCiVASS6q8vfQQ3MFe1GO+PFivj4aWSufUXDTfAlg==","X-Received":"by 10.28.144.140 with SMTP id s134mr1812856wmd.82.1509291119776; \n\tSun, 29 Oct 2017 08:31:59 -0700 (PDT)","From":"Kevin Hilman ","To":"Martin Blumenstingl ","Cc":"linux-amlogic@lists.infradead.org,\n\tlinux-arm-kernel@lists.infradead.org, carlo@caione.org,\n\tlinux@armlinux.org.uk, robh+dt@kernel.org,\n\tdevicetree@vger.kernel.org, arnd@arndb.de, mark.rutland@arm.com,\n\tf.fainelli@gmail.com","Subject":"Re: [PATCH v7 0/6] SMP and CPU hotplug support for Meson8/Meson8b","Organization":"BayLibre","References":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>","Date":"Sun, 29 Oct 2017 16:31:55 +0100","In-Reply-To":"<20170917164523.6970-1-martin.blumenstingl@googlemail.com>\n\t(Martin Blumenstingl's message of \"Sun, 17 Sep 2017 18:45:17 +0200\")","Message-ID":"<7hwp3eug0k.fsf@baylibre.com>","User-Agent":"Gnus/5.13 (Gnus v5.13) Emacs/24.5 (gnu/linux)","MIME-Version":"1.0","Content-Type":"text/plain","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]